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c2be5bfc | 1 | /* |
7469688e | 2 | * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved. |
c2be5bfc JL |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #ifndef __MACH_TEGRA_SLEEP_H | |
18 | #define __MACH_TEGRA_SLEEP_H | |
19 | ||
2be39c07 | 20 | #include "iomap.h" |
c2be5bfc | 21 | |
59b0f682 JL |
22 | #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ |
23 | + IO_CPU_VIRT) | |
c2be5bfc JL |
24 | #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ |
25 | + IO_PPSB_VIRT) | |
453689e4 JL |
26 | #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ |
27 | + IO_PPSB_VIRT) | |
5c1350bd JL |
28 | #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) |
29 | ||
30 | /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */ | |
31 | #define PMC_SCRATCH37 0x130 | |
32 | #define PMC_SCRATCH38 0x134 | |
33 | #define PMC_SCRATCH39 0x138 | |
34 | #define PMC_SCRATCH41 0x140 | |
35 | ||
36 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | |
37 | #define CPU_RESETTABLE 2 | |
38 | #define CPU_RESETTABLE_SOON 1 | |
39 | #define CPU_NOT_RESETTABLE 0 | |
40 | #endif | |
c2be5bfc JL |
41 | |
42 | #ifdef __ASSEMBLY__ | |
43 | /* returns the offset of the flow controller halt register for a cpu */ | |
44 | .macro cpu_to_halt_reg rd, rcpu | |
45 | cmp \rcpu, #0 | |
46 | subne \rd, \rcpu, #1 | |
47 | movne \rd, \rd, lsl #3 | |
48 | addne \rd, \rd, #0x14 | |
49 | moveq \rd, #0 | |
50 | .endm | |
51 | ||
52 | /* returns the offset of the flow controller csr register for a cpu */ | |
53 | .macro cpu_to_csr_reg rd, rcpu | |
54 | cmp \rcpu, #0 | |
55 | subne \rd, \rcpu, #1 | |
56 | movne \rd, \rd, lsl #3 | |
57 | addne \rd, \rd, #0x18 | |
58 | moveq \rd, #8 | |
59 | .endm | |
60 | ||
61 | /* returns the ID of the current processor */ | |
62 | .macro cpu_id, rd | |
63 | mrc p15, 0, \rd, c0, c0, 5 | |
64 | and \rd, \rd, #0xF | |
65 | .endm | |
66 | ||
67 | /* loads a 32-bit value into a register without a data access */ | |
68 | .macro mov32, reg, val | |
69 | movw \reg, #:lower16:\val | |
70 | movt \reg, #:upper16:\val | |
71 | .endm | |
59b0f682 | 72 | |
f6d06f33 JL |
73 | /* Marco to check CPU part num */ |
74 | .macro check_cpu_part_num part_num, tmp1, tmp2 | |
75 | mrc p15, 0, \tmp1, c0, c0, 0 | |
76 | ubfx \tmp1, \tmp1, #4, #12 | |
77 | mov32 \tmp2, \part_num | |
78 | cmp \tmp1, \tmp2 | |
79 | .endm | |
80 | ||
59b0f682 JL |
81 | /* Macro to exit SMP coherency. */ |
82 | .macro exit_smp, tmp1, tmp2 | |
83 | mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR | |
84 | bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW | |
85 | mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR | |
86 | isb | |
f6d06f33 JL |
87 | #ifdef CONFIG_HAVE_ARM_SCU |
88 | check_cpu_part_num 0xc09, \tmp1, \tmp2 | |
89 | mrceq p15, 0, \tmp1, c0, c0, 5 | |
90 | andeq \tmp1, \tmp1, #0xF | |
91 | moveq \tmp1, \tmp1, lsl #2 | |
92 | moveq \tmp2, #0xf | |
93 | moveq \tmp2, \tmp2, lsl \tmp1 | |
94 | ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC) | |
95 | streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU | |
59b0f682 | 96 | dsb |
f6d06f33 | 97 | #endif |
59b0f682 | 98 | .endm |
29a0e7be | 99 | |
4b3e2eda JL |
100 | /* Macro to check Tegra revision */ |
101 | #define APB_MISC_GP_HIDREV 0x804 | |
102 | .macro tegra_get_soc_id base, tmp1 | |
103 | mov32 \tmp1, \base | |
104 | ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV] | |
105 | and \tmp1, \tmp1, #0xff00 | |
106 | mov \tmp1, \tmp1, lsr #8 | |
107 | .endm | |
108 | ||
29a0e7be JL |
109 | /* Macro to resume & re-enable L2 cache */ |
110 | #ifndef L2X0_CTRL_EN | |
111 | #define L2X0_CTRL_EN 1 | |
112 | #endif | |
113 | ||
114 | #ifdef CONFIG_CACHE_L2X0 | |
115 | .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs | |
c312908a | 116 | W(adr) \tmp1, \phys_l2x0_saved_regs |
29a0e7be JL |
117 | ldr \tmp1, [\tmp1] |
118 | ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] | |
119 | ldr \tmp3, [\tmp2, #L2X0_CTRL] | |
120 | tst \tmp3, #L2X0_CTRL_EN | |
121 | bne exit_l2_resume | |
122 | ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY] | |
123 | str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL] | |
124 | ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY] | |
125 | str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL] | |
126 | ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL] | |
127 | str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL] | |
128 | ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL] | |
129 | str \tmp3, [\tmp2, #L2X0_POWER_CTRL] | |
130 | ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL] | |
131 | str \tmp3, [\tmp2, #L2X0_AUX_CTRL] | |
132 | mov \tmp3, #L2X0_CTRL_EN | |
133 | str \tmp3, [\tmp2, #L2X0_CTRL] | |
134 | exit_l2_resume: | |
135 | .endm | |
136 | #else /* CONFIG_CACHE_L2X0 */ | |
137 | .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs | |
138 | .endm | |
139 | #endif /* CONFIG_CACHE_L2X0 */ | |
59b0f682 | 140 | #else |
5c1350bd JL |
141 | void tegra_pen_lock(void); |
142 | void tegra_pen_unlock(void); | |
d3f29365 | 143 | void tegra_resume(void); |
d552920a | 144 | int tegra_sleep_cpu_finish(unsigned long); |
57886616 | 145 | void tegra_disable_clean_inv_dcache(void); |
59b0f682 JL |
146 | |
147 | #ifdef CONFIG_HOTPLUG_CPU | |
7469688e HD |
148 | void tegra20_hotplug_shutdown(void); |
149 | void tegra30_hotplug_shutdown(void); | |
150 | void tegra_hotplug_init(void); | |
59b0f682 | 151 | #else |
7469688e | 152 | static inline void tegra_hotplug_init(void) {} |
59b0f682 JL |
153 | #endif |
154 | ||
1d328606 JL |
155 | void tegra20_cpu_shutdown(int cpu); |
156 | int tegra20_cpu_is_resettable_soon(void); | |
5c1350bd JL |
157 | void tegra20_cpu_clear_resettable(void); |
158 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | |
159 | void tegra20_cpu_set_resettable_soon(void); | |
160 | #else | |
161 | static inline void tegra20_cpu_set_resettable_soon(void) {} | |
162 | #endif | |
163 | ||
164 | int tegra20_sleep_cpu_secondary_finish(unsigned long); | |
1d328606 | 165 | void tegra20_tear_down_cpu(void); |
d457ef35 | 166 | int tegra30_sleep_cpu_secondary_finish(unsigned long); |
d552920a | 167 | void tegra30_tear_down_cpu(void); |
d457ef35 | 168 | |
c2be5bfc JL |
169 | #endif |
170 | #endif |