projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c2be5bfc JL |
1 | /* |
| 2 | * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License | |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef __MACH_TEGRA_SLEEP_H | |
| 18 | #define __MACH_TEGRA_SLEEP_H | |
| 19 | ||
| 20 | #include <mach/iomap.h> | |
| 21 | ||
| 59b0f682 JL |
22 | #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ |
| 23 | + IO_CPU_VIRT) | |
| c2be5bfc JL |
24 | #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ |
| 25 | + IO_PPSB_VIRT) | |
| 26 | ||
| 27 | #ifdef __ASSEMBLY__ | |
| 28 | /* returns the offset of the flow controller halt register for a cpu */ | |
| 29 | .macro cpu_to_halt_reg rd, rcpu | |
| 30 | cmp \rcpu, #0 | |
| 31 | subne \rd, \rcpu, #1 | |
| 32 | movne \rd, \rd, lsl #3 | |
| 33 | addne \rd, \rd, #0x14 | |
| 34 | moveq \rd, #0 | |
| 35 | .endm | |
| 36 | ||
| 37 | /* returns the offset of the flow controller csr register for a cpu */ | |
| 38 | .macro cpu_to_csr_reg rd, rcpu | |
| 39 | cmp \rcpu, #0 | |
| 40 | subne \rd, \rcpu, #1 | |
| 41 | movne \rd, \rd, lsl #3 | |
| 42 | addne \rd, \rd, #0x18 | |
| 43 | moveq \rd, #8 | |
| 44 | .endm | |
| 45 | ||
| 46 | /* returns the ID of the current processor */ | |
| 47 | .macro cpu_id, rd | |
| 48 | mrc p15, 0, \rd, c0, c0, 5 | |
| 49 | and \rd, \rd, #0xF | |
| 50 | .endm | |
| 51 | ||
| 52 | /* loads a 32-bit value into a register without a data access */ | |
| 53 | .macro mov32, reg, val | |
| 54 | movw \reg, #:lower16:\val | |
| 55 | movt \reg, #:upper16:\val | |
| 56 | .endm | |
| 59b0f682 JL |
57 | |
| 58 | /* Macro to exit SMP coherency. */ | |
| 59 | .macro exit_smp, tmp1, tmp2 | |
| 60 | mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR | |
| 61 | bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW | |
| 62 | mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR | |
| 63 | isb | |
| 64 | cpu_id \tmp1 | |
| 65 | mov \tmp1, \tmp1, lsl #2 | |
| 66 | mov \tmp2, #0xf | |
| 67 | mov \tmp2, \tmp2, lsl \tmp1 | |
| 68 | mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC | |
| 69 | str \tmp2, [\tmp1] @ invalidate SCU tags for CPU | |
| 70 | dsb | |
| 71 | .endm | |
| 72 | #else | |
| 73 | ||
| 74 | #ifdef CONFIG_HOTPLUG_CPU | |
| 75 | void tegra30_hotplug_init(void); | |
| 76 | #else | |
| 77 | static inline void tegra30_hotplug_init(void) {} | |
| 78 | #endif | |
| 79 | ||
| c2be5bfc JL |
80 | #endif |
| 81 | #endif |