Commit | Line | Data |
---|---|---|
8e267f3d | 1 | /* |
1b14f3a5 | 2 | * NVIDIA Tegra SoC device tree board support |
8e267f3d | 3 | * |
1b14f3a5 | 4 | * Copyright (C) 2011, 2013, NVIDIA Corporation |
8e267f3d GL |
5 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. |
6 | * Copyright (C) 2010 Google, Inc. | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
1711b1e1 | 19 | #include <linux/clocksource.h> |
8e267f3d GL |
20 | #include <linux/kernel.h> |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/serial_8250.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/irqdomain.h> | |
27 | #include <linux/of.h> | |
28 | #include <linux/of_address.h> | |
29 | #include <linux/of_fdt.h> | |
8e267f3d GL |
30 | #include <linux/of_platform.h> |
31 | #include <linux/pda_power.h> | |
bab53ce3 | 32 | #include <linux/platform_data/tegra_usb.h> |
8e267f3d | 33 | #include <linux/io.h> |
d591fdf8 DH |
34 | #include <linux/slab.h> |
35 | #include <linux/sys_soc.h> | |
bab53ce3 | 36 | #include <linux/usb/tegra_usb_phy.h> |
8e267f3d GL |
37 | |
38 | #include <asm/mach-types.h> | |
39 | #include <asm/mach/arch.h> | |
40 | #include <asm/mach/time.h> | |
41 | #include <asm/setup.h> | |
42 | ||
8e267f3d | 43 | #include "board.h" |
a1725732 | 44 | #include "common.h" |
d591fdf8 | 45 | #include "fuse.h" |
2be39c07 | 46 | #include "iomap.h" |
bab53ce3 | 47 | |
deeb8d19 | 48 | static struct tegra_ehci_platform_data tegra_ehci1_pdata = { |
bab53ce3 SW |
49 | .operating_mode = TEGRA_USB_OTG, |
50 | .power_down_on_bus_suspend = 1, | |
51 | .vbus_gpio = -1, | |
52 | }; | |
53 | ||
deeb8d19 | 54 | static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { |
bab53ce3 SW |
55 | .reset_gpio = -1, |
56 | .clk = "cdev2", | |
57 | }; | |
58 | ||
deeb8d19 | 59 | static struct tegra_ehci_platform_data tegra_ehci2_pdata = { |
bab53ce3 SW |
60 | .phy_config = &tegra_ehci2_ulpi_phy_config, |
61 | .operating_mode = TEGRA_USB_HOST, | |
62 | .power_down_on_bus_suspend = 1, | |
63 | .vbus_gpio = -1, | |
64 | }; | |
65 | ||
deeb8d19 | 66 | static struct tegra_ehci_platform_data tegra_ehci3_pdata = { |
bab53ce3 SW |
67 | .operating_mode = TEGRA_USB_HOST, |
68 | .power_down_on_bus_suspend = 1, | |
69 | .vbus_gpio = -1, | |
70 | }; | |
8e267f3d | 71 | |
deeb8d19 | 72 | static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { |
16a665f8 | 73 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5000000, "tegra-ehci.0", |
8c3ec841 | 74 | &tegra_ehci1_pdata), |
16a665f8 | 75 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5004000, "tegra-ehci.1", |
8c3ec841 | 76 | &tegra_ehci2_pdata), |
16a665f8 | 77 | OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5008000, "tegra-ehci.2", |
8c3ec841 | 78 | &tegra_ehci3_pdata), |
8e267f3d GL |
79 | {} |
80 | }; | |
81 | ||
8e267f3d GL |
82 | static void __init tegra_dt_init(void) |
83 | { | |
d591fdf8 DH |
84 | struct soc_device_attribute *soc_dev_attr; |
85 | struct soc_device *soc_dev; | |
86 | struct device *parent = NULL; | |
87 | ||
88 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
89 | if (!soc_dev_attr) | |
90 | goto out; | |
91 | ||
92 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); | |
93 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision); | |
94 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id); | |
95 | ||
96 | soc_dev = soc_device_register(soc_dev_attr); | |
97 | if (IS_ERR(soc_dev)) { | |
98 | kfree(soc_dev_attr->family); | |
99 | kfree(soc_dev_attr->revision); | |
100 | kfree(soc_dev_attr->soc_id); | |
101 | kfree(soc_dev_attr); | |
102 | goto out; | |
103 | } | |
104 | ||
105 | parent = soc_device_to_device(soc_dev); | |
106 | ||
a58116f3 SW |
107 | /* |
108 | * Finished with the static registrations now; fill in the missing | |
109 | * devices | |
110 | */ | |
d591fdf8 | 111 | out: |
2553dcc6 | 112 | of_platform_populate(NULL, of_default_bus_match_table, |
d591fdf8 | 113 | tegra20_auxdata_lookup, parent); |
8e267f3d GL |
114 | } |
115 | ||
c554dee3 SW |
116 | static void __init trimslice_init(void) |
117 | { | |
be6a9194 | 118 | #ifdef CONFIG_TEGRA_PCI |
c554dee3 SW |
119 | int ret; |
120 | ||
121 | ret = tegra_pcie_init(true, true); | |
122 | if (ret) | |
123 | pr_err("tegra_pci_init() failed: %d\n", ret); | |
c554dee3 | 124 | #endif |
be6a9194 | 125 | } |
c554dee3 | 126 | |
a12c0efc SW |
127 | static void __init harmony_init(void) |
128 | { | |
3cc404de | 129 | #ifdef CONFIG_TEGRA_PCI |
a12c0efc SW |
130 | int ret; |
131 | ||
a12c0efc SW |
132 | ret = harmony_pcie_init(); |
133 | if (ret) | |
134 | pr_err("harmony_pcie_init() failed: %d\n", ret); | |
a12c0efc | 135 | #endif |
bb25af81 | 136 | } |
a12c0efc | 137 | |
b64a02c6 SW |
138 | static void __init paz00_init(void) |
139 | { | |
1b14f3a5 HD |
140 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
141 | tegra_paz00_wifikill_init(); | |
b64a02c6 | 142 | } |
b64a02c6 | 143 | |
c554dee3 SW |
144 | static struct { |
145 | char *machine; | |
146 | void (*init)(void); | |
147 | } board_init_funcs[] = { | |
c554dee3 | 148 | { "compulab,trimslice", trimslice_init }, |
a12c0efc | 149 | { "nvidia,harmony", harmony_init }, |
b64a02c6 | 150 | { "compal,paz00", paz00_init }, |
c554dee3 SW |
151 | }; |
152 | ||
153 | static void __init tegra_dt_init_late(void) | |
154 | { | |
155 | int i; | |
156 | ||
157 | tegra_init_late(); | |
158 | ||
159 | for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { | |
160 | if (of_machine_is_compatible(board_init_funcs[i].machine)) { | |
161 | board_init_funcs[i].init(); | |
162 | break; | |
163 | } | |
164 | } | |
165 | } | |
166 | ||
1b14f3a5 HD |
167 | static const char * const tegra_dt_board_compat[] = { |
168 | "nvidia,tegra114", | |
169 | "nvidia,tegra30", | |
c5444f39 | 170 | "nvidia,tegra20", |
8e267f3d GL |
171 | NULL |
172 | }; | |
173 | ||
1b14f3a5 | 174 | DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") |
8e267f3d | 175 | .map_io = tegra_map_common_io, |
a1725732 | 176 | .smp = smp_ops(tegra_smp_ops), |
7469688e | 177 | .init_early = tegra_init_early, |
0d4f7479 | 178 | .init_irq = tegra_dt_init_irq, |
1711b1e1 | 179 | .init_time = clocksource_of_init, |
8e267f3d | 180 | .init_machine = tegra_dt_init, |
c554dee3 | 181 | .init_late = tegra_dt_init_late, |
abea3f2c | 182 | .restart = tegra_assert_system_reset, |
1b14f3a5 | 183 | .dt_compat = tegra_dt_board_compat, |
8e267f3d | 184 | MACHINE_END |