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1 | /* |
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/bug.h> | |
19 | ||
20 | #include "fuse.h" | |
21 | ||
22 | #define CPU_SPEEDO_LSBIT 20 | |
23 | #define CPU_SPEEDO_MSBIT 29 | |
24 | #define CPU_SPEEDO_REDUND_LSBIT 30 | |
25 | #define CPU_SPEEDO_REDUND_MSBIT 39 | |
26 | #define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT) | |
27 | ||
28 | #define CORE_SPEEDO_LSBIT 40 | |
29 | #define CORE_SPEEDO_MSBIT 47 | |
30 | #define CORE_SPEEDO_REDUND_LSBIT 48 | |
31 | #define CORE_SPEEDO_REDUND_MSBIT 55 | |
32 | #define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT) | |
33 | ||
34 | #define SPEEDO_MULT 4 | |
35 | ||
36 | #define PROCESS_CORNERS_NUM 4 | |
37 | ||
38 | #define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2) | |
39 | #define SPEEDO_ID_SELECT_1(sku) \ | |
40 | (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \ | |
41 | ((sku) != 27) && ((sku) != 28)) | |
42 | ||
43 | enum { | |
44 | SPEEDO_ID_0, | |
45 | SPEEDO_ID_1, | |
46 | SPEEDO_ID_2, | |
47 | SPEEDO_ID_COUNT, | |
48 | }; | |
49 | ||
50 | static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = { | |
51 | {315, 366, 420, UINT_MAX}, | |
52 | {303, 368, 419, UINT_MAX}, | |
53 | {316, 331, 383, UINT_MAX}, | |
54 | }; | |
55 | ||
56 | static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = { | |
57 | {165, 195, 224, UINT_MAX}, | |
58 | {165, 195, 224, UINT_MAX}, | |
59 | {165, 195, 224, UINT_MAX}, | |
60 | }; | |
61 | ||
62 | void tegra20_init_speedo_data(void) | |
63 | { | |
64 | u32 reg; | |
65 | u32 val; | |
66 | int i; | |
67 | ||
68 | BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT); | |
69 | BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT); | |
70 | ||
71 | if (SPEEDO_ID_SELECT_0(tegra_revision)) | |
72 | tegra_soc_speedo_id = SPEEDO_ID_0; | |
73 | else if (SPEEDO_ID_SELECT_1(tegra_sku_id)) | |
74 | tegra_soc_speedo_id = SPEEDO_ID_1; | |
75 | else | |
76 | tegra_soc_speedo_id = SPEEDO_ID_2; | |
77 | ||
78 | val = 0; | |
79 | for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) { | |
80 | reg = tegra_spare_fuse(i) | | |
81 | tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS); | |
82 | val = (val << 1) | (reg & 0x1); | |
83 | } | |
84 | val = val * SPEEDO_MULT; | |
85 | pr_debug("%s CPU speedo value %u\n", __func__, val); | |
86 | ||
87 | for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) { | |
88 | if (val <= cpu_process_speedos[tegra_soc_speedo_id][i]) | |
89 | break; | |
90 | } | |
91 | tegra_cpu_process_id = i; | |
92 | ||
93 | val = 0; | |
94 | for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) { | |
95 | reg = tegra_spare_fuse(i) | | |
96 | tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS); | |
97 | val = (val << 1) | (reg & 0x1); | |
98 | } | |
99 | val = val * SPEEDO_MULT; | |
100 | pr_debug("%s Core speedo value %u\n", __func__, val); | |
101 | ||
102 | for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) { | |
103 | if (val <= core_process_speedos[tegra_soc_speedo_id][i]) | |
104 | break; | |
105 | } | |
106 | tegra_core_process_id = i; | |
107 | ||
108 | pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id); | |
109 | } |