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d8611961 CC |
1 | /* |
2 | * arch/arm/mach-tegra/tegra2_clocks.c | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/hrtimer.h> | |
27 | ||
28 | #include <asm/clkdev.h> | |
29 | ||
30 | #include <mach/iomap.h> | |
31 | ||
32 | #include "clock.h" | |
33 | ||
34 | #define RST_DEVICES 0x004 | |
35 | #define RST_DEVICES_SET 0x300 | |
36 | #define RST_DEVICES_CLR 0x304 | |
37 | ||
38 | #define CLK_OUT_ENB 0x010 | |
39 | #define CLK_OUT_ENB_SET 0x320 | |
40 | #define CLK_OUT_ENB_CLR 0x324 | |
41 | ||
42 | #define OSC_CTRL 0x50 | |
43 | #define OSC_CTRL_OSC_FREQ_MASK (3<<30) | |
44 | #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) | |
45 | #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) | |
46 | #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) | |
47 | #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) | |
48 | ||
49 | #define OSC_FREQ_DET 0x58 | |
50 | #define OSC_FREQ_DET_TRIG (1<<31) | |
51 | ||
52 | #define OSC_FREQ_DET_STATUS 0x5C | |
53 | #define OSC_FREQ_DET_BUSY (1<<31) | |
54 | #define OSC_FREQ_DET_CNT_MASK 0xFFFF | |
55 | ||
56 | #define PERIPH_CLK_SOURCE_MASK (3<<30) | |
57 | #define PERIPH_CLK_SOURCE_SHIFT 30 | |
58 | #define PERIPH_CLK_SOURCE_ENABLE (1<<28) | |
59 | #define PERIPH_CLK_SOURCE_DIV_MASK 0xFF | |
60 | #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 | |
61 | ||
62 | #define PLL_BASE 0x0 | |
63 | #define PLL_BASE_BYPASS (1<<31) | |
64 | #define PLL_BASE_ENABLE (1<<30) | |
65 | #define PLL_BASE_REF_ENABLE (1<<29) | |
66 | #define PLL_BASE_OVERRIDE (1<<28) | |
67 | #define PLL_BASE_LOCK (1<<27) | |
68 | #define PLL_BASE_DIVP_MASK (0x7<<20) | |
69 | #define PLL_BASE_DIVP_SHIFT 20 | |
70 | #define PLL_BASE_DIVN_MASK (0x3FF<<8) | |
71 | #define PLL_BASE_DIVN_SHIFT 8 | |
72 | #define PLL_BASE_DIVM_MASK (0x1F) | |
73 | #define PLL_BASE_DIVM_SHIFT 0 | |
74 | ||
75 | #define PLL_OUT_RATIO_MASK (0xFF<<8) | |
76 | #define PLL_OUT_RATIO_SHIFT 8 | |
77 | #define PLL_OUT_OVERRIDE (1<<2) | |
78 | #define PLL_OUT_CLKEN (1<<1) | |
79 | #define PLL_OUT_RESET_DISABLE (1<<0) | |
80 | ||
81 | #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) | |
82 | #define PLL_MISC_DCCON_SHIFT 20 | |
83 | #define PLL_MISC_LOCK_ENABLE (1<<18) | |
84 | #define PLL_MISC_CPCON_SHIFT 8 | |
85 | #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) | |
86 | #define PLL_MISC_LFCON_SHIFT 4 | |
87 | #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) | |
88 | #define PLL_MISC_VCOCON_SHIFT 0 | |
89 | #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) | |
90 | ||
91 | #define PLLD_MISC_CLKENABLE (1<<30) | |
92 | #define PLLD_MISC_DIV_RST (1<<23) | |
93 | #define PLLD_MISC_DCCON_SHIFT 12 | |
94 | ||
95 | #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4) | |
96 | #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8) | |
97 | #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32)) | |
98 | ||
99 | #define SUPER_CLK_MUX 0x00 | |
100 | #define SUPER_STATE_SHIFT 28 | |
101 | #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) | |
102 | #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) | |
103 | #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) | |
104 | #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) | |
105 | #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) | |
106 | #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) | |
107 | #define SUPER_SOURCE_MASK 0xF | |
108 | #define SUPER_FIQ_SOURCE_SHIFT 12 | |
109 | #define SUPER_IRQ_SOURCE_SHIFT 8 | |
110 | #define SUPER_RUN_SOURCE_SHIFT 4 | |
111 | #define SUPER_IDLE_SOURCE_SHIFT 0 | |
112 | ||
113 | #define SUPER_CLK_DIVIDER 0x04 | |
114 | ||
115 | #define BUS_CLK_DISABLE (1<<3) | |
116 | #define BUS_CLK_DIV_MASK 0x3 | |
117 | ||
118 | static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); | |
119 | ||
120 | #define clk_writel(value, reg) \ | |
121 | __raw_writel(value, (u32)reg_clk_base + (reg)) | |
122 | #define clk_readl(reg) \ | |
123 | __raw_readl((u32)reg_clk_base + (reg)) | |
124 | ||
125 | unsigned long clk_measure_input_freq(void) | |
126 | { | |
127 | u32 clock_autodetect; | |
128 | clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); | |
129 | do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); | |
130 | clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); | |
131 | if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { | |
132 | return 12000000; | |
133 | } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { | |
134 | return 13000000; | |
135 | } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { | |
136 | return 19200000; | |
137 | } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { | |
138 | return 26000000; | |
139 | } else { | |
140 | pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect); | |
141 | BUG(); | |
142 | return 0; | |
143 | } | |
144 | } | |
145 | ||
146 | static int clk_div71_get_divider(struct clk *c, unsigned long rate) | |
147 | { | |
148 | unsigned long divider_u71; | |
149 | ||
150 | divider_u71 = DIV_ROUND_UP(c->rate * 2, rate); | |
151 | ||
152 | if (divider_u71 - 2 > 255 || divider_u71 - 2 < 0) | |
153 | return -EINVAL; | |
154 | ||
155 | return divider_u71 - 2; | |
156 | } | |
157 | ||
158 | static unsigned long tegra2_clk_recalculate_rate(struct clk *c) | |
159 | { | |
160 | unsigned long rate; | |
161 | rate = c->parent->rate; | |
162 | ||
163 | if (c->mul != 0 && c->div != 0) | |
164 | c->rate = rate * c->mul / c->div; | |
165 | else | |
166 | c->rate = rate; | |
167 | return c->rate; | |
168 | } | |
169 | ||
170 | ||
171 | /* clk_m functions */ | |
172 | static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c) | |
173 | { | |
174 | u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK; | |
175 | ||
176 | c->rate = clk_measure_input_freq(); | |
177 | switch (c->rate) { | |
178 | case 12000000: | |
179 | auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; | |
180 | break; | |
181 | case 13000000: | |
182 | auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; | |
183 | break; | |
184 | case 19200000: | |
185 | auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; | |
186 | break; | |
187 | case 26000000: | |
188 | auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; | |
189 | break; | |
190 | default: | |
191 | pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); | |
192 | BUG(); | |
193 | } | |
194 | clk_writel(auto_clock_control, OSC_CTRL); | |
195 | return c->rate; | |
196 | } | |
197 | ||
198 | static void tegra2_clk_m_init(struct clk *c) | |
199 | { | |
200 | pr_debug("%s on clock %s\n", __func__, c->name); | |
201 | tegra2_clk_m_autodetect_rate(c); | |
202 | } | |
203 | ||
204 | static int tegra2_clk_m_enable(struct clk *c) | |
205 | { | |
206 | pr_debug("%s on clock %s\n", __func__, c->name); | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static void tegra2_clk_m_disable(struct clk *c) | |
211 | { | |
212 | pr_debug("%s on clock %s\n", __func__, c->name); | |
213 | BUG(); | |
214 | } | |
215 | ||
216 | static struct clk_ops tegra_clk_m_ops = { | |
217 | .init = tegra2_clk_m_init, | |
218 | .enable = tegra2_clk_m_enable, | |
219 | .disable = tegra2_clk_m_disable, | |
220 | }; | |
221 | ||
222 | /* super clock functions */ | |
223 | /* "super clocks" on tegra have two-stage muxes and a clock skipping | |
224 | * super divider. We will ignore the clock skipping divider, since we | |
225 | * can't lower the voltage when using the clock skip, but we can if we | |
226 | * lower the PLL frequency. | |
227 | */ | |
228 | static void tegra2_super_clk_init(struct clk *c) | |
229 | { | |
230 | u32 val; | |
231 | int source; | |
232 | int shift; | |
233 | const struct clk_mux_sel *sel; | |
234 | val = clk_readl(c->reg + SUPER_CLK_MUX); | |
235 | c->state = ON; | |
236 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | |
237 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
238 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
239 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
240 | source = (val >> shift) & SUPER_SOURCE_MASK; | |
241 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
242 | if (sel->value == source) | |
243 | break; | |
244 | } | |
245 | BUG_ON(sel->input == NULL); | |
246 | c->parent = sel->input; | |
247 | tegra2_clk_recalculate_rate(c); | |
248 | } | |
249 | ||
250 | static int tegra2_super_clk_enable(struct clk *c) | |
251 | { | |
252 | clk_writel(0, c->reg + SUPER_CLK_DIVIDER); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static void tegra2_super_clk_disable(struct clk *c) | |
257 | { | |
258 | pr_debug("%s on clock %s\n", __func__, c->name); | |
259 | ||
260 | /* oops - don't disable the CPU clock! */ | |
261 | BUG(); | |
262 | } | |
263 | ||
264 | static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) | |
265 | { | |
266 | u32 val; | |
267 | const struct clk_mux_sel *sel; | |
268 | int shift; | |
269 | val = clk_readl(c->reg + SUPER_CLK_MUX);; | |
270 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | |
271 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
272 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
273 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
274 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
275 | if (sel->input == p) { | |
276 | clk_reparent(c, p); | |
277 | val &= ~(SUPER_SOURCE_MASK << shift); | |
278 | val |= sel->value << shift; | |
279 | clk_writel(val, c->reg); | |
280 | c->rate = c->parent->rate; | |
281 | return 0; | |
282 | } | |
283 | } | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | static struct clk_ops tegra_super_ops = { | |
288 | .init = tegra2_super_clk_init, | |
289 | .enable = tegra2_super_clk_enable, | |
290 | .disable = tegra2_super_clk_disable, | |
291 | .set_parent = tegra2_super_clk_set_parent, | |
292 | .recalculate_rate = tegra2_clk_recalculate_rate, | |
293 | }; | |
294 | ||
295 | /* bus clock functions */ | |
296 | static void tegra2_bus_clk_init(struct clk *c) | |
297 | { | |
298 | u32 val = clk_readl(c->reg); | |
299 | c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; | |
300 | c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; | |
301 | c->mul = 1; | |
302 | tegra2_clk_recalculate_rate(c); | |
303 | } | |
304 | ||
305 | static int tegra2_bus_clk_enable(struct clk *c) | |
306 | { | |
307 | u32 val = clk_readl(c->reg); | |
308 | val &= ~(BUS_CLK_DISABLE << c->reg_shift); | |
309 | clk_writel(val, c->reg); | |
310 | return 0; | |
311 | } | |
312 | ||
313 | static void tegra2_bus_clk_disable(struct clk *c) | |
314 | { | |
315 | u32 val = clk_readl(c->reg); | |
316 | val |= BUS_CLK_DISABLE << c->reg_shift; | |
317 | clk_writel(val, c->reg); | |
318 | } | |
319 | ||
320 | static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate) | |
321 | { | |
322 | u32 val = clk_readl(c->reg); | |
323 | unsigned long parent_rate = c->parent->rate; | |
324 | int i; | |
325 | for (i = 1; i <= 4; i++) { | |
326 | if (rate == parent_rate / i) { | |
327 | val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); | |
328 | val |= (i - 1) << c->reg_shift; | |
329 | clk_writel(val, c->reg); | |
330 | c->div = i; | |
331 | c->mul = 1; | |
332 | return 0; | |
333 | } | |
334 | } | |
335 | return -EINVAL; | |
336 | } | |
337 | ||
338 | static struct clk_ops tegra_bus_ops = { | |
339 | .init = tegra2_bus_clk_init, | |
340 | .enable = tegra2_bus_clk_enable, | |
341 | .disable = tegra2_bus_clk_disable, | |
342 | .set_rate = tegra2_bus_clk_set_rate, | |
343 | .recalculate_rate = tegra2_clk_recalculate_rate, | |
344 | }; | |
345 | ||
346 | /* PLL Functions */ | |
347 | static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c) | |
348 | { | |
349 | u64 rate; | |
350 | rate = c->parent->rate; | |
351 | rate *= c->n; | |
352 | do_div(rate, c->m); | |
353 | if (c->p == 2) | |
354 | rate >>= 1; | |
355 | c->rate = rate; | |
356 | return c->rate; | |
357 | } | |
358 | ||
359 | static int tegra2_pll_clk_wait_for_lock(struct clk *c) | |
360 | { | |
361 | ktime_t before; | |
362 | ||
363 | before = ktime_get(); | |
364 | while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) { | |
365 | if (ktime_us_delta(ktime_get(), before) > 5000) { | |
366 | pr_err("Timed out waiting for lock bit on pll %s", | |
367 | c->name); | |
368 | return -1; | |
369 | } | |
370 | } | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | static void tegra2_pll_clk_init(struct clk *c) | |
376 | { | |
377 | u32 val = clk_readl(c->reg + PLL_BASE); | |
378 | ||
379 | c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; | |
380 | ||
381 | if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { | |
382 | pr_warning("Clock %s has unknown fixed frequency\n", c->name); | |
383 | c->n = 1; | |
384 | c->m = 0; | |
385 | c->p = 1; | |
386 | } else if (val & PLL_BASE_BYPASS) { | |
387 | c->n = 1; | |
388 | c->m = 1; | |
389 | c->p = 1; | |
390 | } else { | |
391 | c->n = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; | |
392 | c->m = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; | |
393 | c->p = (val & PLL_BASE_DIVP_MASK) ? 2 : 1; | |
394 | } | |
395 | ||
396 | val = clk_readl(c->reg + PLL_MISC(c)); | |
397 | if (c->flags & PLL_HAS_CPCON) | |
398 | c->cpcon = (val & PLL_MISC_CPCON_MASK) >> PLL_MISC_CPCON_SHIFT; | |
399 | ||
400 | tegra2_pll_clk_recalculate_rate(c); | |
401 | } | |
402 | ||
403 | static int tegra2_pll_clk_enable(struct clk *c) | |
404 | { | |
405 | u32 val; | |
406 | pr_debug("%s on clock %s\n", __func__, c->name); | |
407 | ||
408 | val = clk_readl(c->reg + PLL_BASE); | |
409 | val &= ~PLL_BASE_BYPASS; | |
410 | val |= PLL_BASE_ENABLE; | |
411 | clk_writel(val, c->reg + PLL_BASE); | |
412 | ||
413 | val = clk_readl(c->reg + PLL_MISC(c)); | |
414 | val |= PLL_MISC_LOCK_ENABLE; | |
415 | clk_writel(val, c->reg + PLL_MISC(c)); | |
416 | ||
417 | tegra2_pll_clk_wait_for_lock(c); | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static void tegra2_pll_clk_disable(struct clk *c) | |
423 | { | |
424 | u32 val; | |
425 | pr_debug("%s on clock %s\n", __func__, c->name); | |
426 | ||
427 | val = clk_readl(c->reg); | |
428 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); | |
429 | clk_writel(val, c->reg); | |
430 | } | |
431 | ||
432 | static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) | |
433 | { | |
434 | u32 val; | |
435 | unsigned long input_rate; | |
436 | const struct clk_pll_table *sel; | |
437 | ||
438 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); | |
439 | BUG_ON(c->refcnt != 0); | |
440 | ||
441 | input_rate = c->parent->rate; | |
442 | for (sel = c->pll_table; sel->input_rate != 0; sel++) { | |
443 | if (sel->input_rate == input_rate && sel->output_rate == rate) { | |
444 | c->n = sel->n; | |
445 | c->m = sel->m; | |
446 | c->p = sel->p; | |
447 | c->cpcon = sel->cpcon; | |
448 | ||
449 | val = clk_readl(c->reg + PLL_BASE); | |
450 | if (c->flags & PLL_FIXED) | |
451 | val |= PLL_BASE_OVERRIDE; | |
452 | val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK | | |
453 | PLL_BASE_DIVM_MASK); | |
454 | val |= (c->m << PLL_BASE_DIVM_SHIFT) | | |
455 | (c->n << PLL_BASE_DIVN_SHIFT); | |
456 | BUG_ON(c->p > 2); | |
457 | if (c->p == 2) | |
458 | val |= 1 << PLL_BASE_DIVP_SHIFT; | |
459 | clk_writel(val, c->reg + PLL_BASE); | |
460 | ||
461 | if (c->flags & PLL_HAS_CPCON) { | |
462 | val = c->cpcon << PLL_MISC_CPCON_SHIFT; | |
463 | val |= PLL_MISC_LOCK_ENABLE; | |
464 | clk_writel(val, c->reg + PLL_MISC(c)); | |
465 | } | |
466 | ||
467 | if (c->state == ON) | |
468 | tegra2_pll_clk_enable(c); | |
469 | ||
470 | c->rate = rate; | |
471 | return 0; | |
472 | } | |
473 | } | |
474 | return -EINVAL; | |
475 | } | |
476 | ||
477 | static struct clk_ops tegra_pll_ops = { | |
478 | .init = tegra2_pll_clk_init, | |
479 | .enable = tegra2_pll_clk_enable, | |
480 | .disable = tegra2_pll_clk_disable, | |
481 | .set_rate = tegra2_pll_clk_set_rate, | |
482 | .recalculate_rate = tegra2_pll_clk_recalculate_rate, | |
483 | }; | |
484 | ||
485 | /* Clock divider ops */ | |
486 | static void tegra2_pll_div_clk_init(struct clk *c) | |
487 | { | |
488 | u32 val = clk_readl(c->reg); | |
489 | u32 divu71; | |
490 | val >>= c->reg_shift; | |
491 | c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; | |
492 | if (!(val & PLL_OUT_RESET_DISABLE)) | |
493 | c->state = OFF; | |
494 | ||
495 | if (c->flags & DIV_U71) { | |
496 | divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; | |
497 | c->div = (divu71 + 2); | |
498 | c->mul = 2; | |
499 | } else if (c->flags & DIV_2) { | |
500 | c->div = 2; | |
501 | c->mul = 1; | |
502 | } else { | |
503 | c->div = 1; | |
504 | c->mul = 1; | |
505 | } | |
506 | ||
507 | tegra2_clk_recalculate_rate(c); | |
508 | } | |
509 | ||
510 | static int tegra2_pll_div_clk_enable(struct clk *c) | |
511 | { | |
512 | u32 val; | |
513 | u32 new_val; | |
514 | ||
515 | pr_debug("%s: %s\n", __func__, c->name); | |
516 | if (c->flags & DIV_U71) { | |
517 | val = clk_readl(c->reg); | |
518 | new_val = val >> c->reg_shift; | |
519 | new_val &= 0xFFFF; | |
520 | ||
521 | new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; | |
522 | ||
523 | val &= ~(0xFFFF << c->reg_shift); | |
524 | val |= new_val << c->reg_shift; | |
525 | clk_writel(val, c->reg); | |
526 | return 0; | |
527 | } else if (c->flags & DIV_2) { | |
528 | BUG_ON(!(c->flags & PLLD)); | |
529 | val = clk_readl(c->reg); | |
530 | val &= ~PLLD_MISC_DIV_RST; | |
531 | clk_writel(val, c->reg); | |
532 | return 0; | |
533 | } | |
534 | return -EINVAL; | |
535 | } | |
536 | ||
537 | static void tegra2_pll_div_clk_disable(struct clk *c) | |
538 | { | |
539 | u32 val; | |
540 | u32 new_val; | |
541 | ||
542 | pr_debug("%s: %s\n", __func__, c->name); | |
543 | if (c->flags & DIV_U71) { | |
544 | val = clk_readl(c->reg); | |
545 | new_val = val >> c->reg_shift; | |
546 | new_val &= 0xFFFF; | |
547 | ||
548 | new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); | |
549 | ||
550 | val &= ~(0xFFFF << c->reg_shift); | |
551 | val |= new_val << c->reg_shift; | |
552 | clk_writel(val, c->reg); | |
553 | } else if (c->flags & DIV_2) { | |
554 | BUG_ON(!(c->flags & PLLD)); | |
555 | val = clk_readl(c->reg); | |
556 | val |= PLLD_MISC_DIV_RST; | |
557 | clk_writel(val, c->reg); | |
558 | } | |
559 | } | |
560 | ||
561 | static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) | |
562 | { | |
563 | u32 val; | |
564 | u32 new_val; | |
565 | int divider_u71; | |
566 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); | |
567 | if (c->flags & DIV_U71) { | |
568 | divider_u71 = clk_div71_get_divider(c->parent, rate); | |
569 | if (divider_u71 >= 0) { | |
570 | val = clk_readl(c->reg); | |
571 | new_val = val >> c->reg_shift; | |
572 | new_val &= 0xFFFF; | |
573 | if (c->flags & DIV_U71_FIXED) | |
574 | new_val |= PLL_OUT_OVERRIDE; | |
575 | new_val &= ~PLL_OUT_RATIO_MASK; | |
576 | new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; | |
577 | ||
578 | val &= ~(0xFFFF << c->reg_shift); | |
579 | val |= new_val << c->reg_shift; | |
580 | clk_writel(val, c->reg); | |
581 | c->div = divider_u71 + 2; | |
582 | c->mul = 2; | |
583 | tegra2_clk_recalculate_rate(c); | |
584 | return 0; | |
585 | } | |
586 | } else if (c->flags & DIV_2) { | |
587 | if (c->parent->rate == rate * 2) { | |
588 | c->rate = rate; | |
589 | return 0; | |
590 | } | |
591 | } | |
592 | return -EINVAL; | |
593 | } | |
594 | ||
595 | ||
596 | static struct clk_ops tegra_pll_div_ops = { | |
597 | .init = tegra2_pll_div_clk_init, | |
598 | .enable = tegra2_pll_div_clk_enable, | |
599 | .disable = tegra2_pll_div_clk_disable, | |
600 | .set_rate = tegra2_pll_div_clk_set_rate, | |
601 | .recalculate_rate = tegra2_clk_recalculate_rate, | |
602 | }; | |
603 | ||
604 | /* Periph clk ops */ | |
605 | ||
606 | static void tegra2_periph_clk_init(struct clk *c) | |
607 | { | |
608 | u32 val = clk_readl(c->reg); | |
609 | const struct clk_mux_sel *mux = 0; | |
610 | const struct clk_mux_sel *sel; | |
611 | if (c->flags & MUX) { | |
612 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
613 | if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value) | |
614 | mux = sel; | |
615 | } | |
616 | BUG_ON(!mux); | |
617 | ||
618 | c->parent = mux->input; | |
619 | } else { | |
620 | c->parent = c->inputs[0].input; | |
621 | } | |
622 | ||
623 | if (c->flags & DIV_U71) { | |
624 | u32 divu71 = val & PERIPH_CLK_SOURCE_DIV_MASK; | |
625 | c->div = divu71 + 2; | |
626 | c->mul = 2; | |
627 | } else { | |
628 | c->div = 1; | |
629 | c->mul = 1; | |
630 | } | |
631 | ||
632 | c->state = ON; | |
633 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & | |
634 | PERIPH_CLK_TO_ENB_BIT(c))) | |
635 | c->state = OFF; | |
636 | if (!(c->flags & PERIPH_NO_RESET)) | |
637 | if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & | |
638 | PERIPH_CLK_TO_ENB_BIT(c)) | |
639 | c->state = OFF; | |
640 | tegra2_clk_recalculate_rate(c); | |
641 | } | |
642 | ||
643 | static int tegra2_periph_clk_enable(struct clk *c) | |
644 | { | |
645 | u32 val; | |
646 | pr_debug("%s on clock %s\n", __func__, c->name); | |
647 | ||
648 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
649 | CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
650 | if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) | |
651 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
652 | RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
653 | if (c->flags & PERIPH_EMC_ENB) { | |
654 | /* The EMC peripheral clock has 2 extra enable bits */ | |
655 | /* FIXME: Do they need to be disabled? */ | |
656 | val = clk_readl(c->reg); | |
657 | val |= 0x3 << 24; | |
658 | clk_writel(val, c->reg); | |
659 | } | |
660 | return 0; | |
661 | } | |
662 | ||
663 | static void tegra2_periph_clk_disable(struct clk *c) | |
664 | { | |
665 | pr_debug("%s on clock %s\n", __func__, c->name); | |
666 | ||
667 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
668 | CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
669 | } | |
670 | ||
671 | void tegra2_periph_reset_deassert(struct clk *c) | |
672 | { | |
673 | pr_debug("%s on clock %s\n", __func__, c->name); | |
674 | if (!(c->flags & PERIPH_NO_RESET)) | |
675 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
676 | RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
677 | } | |
678 | ||
679 | void tegra2_periph_reset_assert(struct clk *c) | |
680 | { | |
681 | pr_debug("%s on clock %s\n", __func__, c->name); | |
682 | if (!(c->flags & PERIPH_NO_RESET)) | |
683 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
684 | RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
685 | } | |
686 | ||
687 | ||
688 | static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) | |
689 | { | |
690 | u32 val; | |
691 | const struct clk_mux_sel *sel; | |
692 | pr_debug("%s: %s %s\n", __func__, c->name, p->name); | |
693 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
694 | if (sel->input == p) { | |
695 | clk_reparent(c, p); | |
696 | val = clk_readl(c->reg); | |
697 | val &= ~PERIPH_CLK_SOURCE_MASK; | |
698 | val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; | |
699 | clk_writel(val, c->reg); | |
700 | c->rate = c->parent->rate; | |
701 | return 0; | |
702 | } | |
703 | } | |
704 | ||
705 | return -EINVAL; | |
706 | } | |
707 | ||
708 | static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) | |
709 | { | |
710 | u32 val; | |
711 | int divider_u71; | |
712 | pr_debug("%s: %lu\n", __func__, rate); | |
713 | if (c->flags & DIV_U71) { | |
714 | divider_u71 = clk_div71_get_divider(c->parent, rate); | |
715 | if (divider_u71 >= 0) { | |
716 | val = clk_readl(c->reg); | |
717 | val &= ~PERIPH_CLK_SOURCE_DIV_MASK; | |
718 | val |= divider_u71; | |
719 | clk_writel(val, c->reg); | |
720 | c->div = divider_u71 + 2; | |
721 | c->mul = 2; | |
722 | tegra2_clk_recalculate_rate(c); | |
723 | return 0; | |
724 | } | |
725 | } | |
726 | return -EINVAL; | |
727 | } | |
728 | ||
729 | static struct clk_ops tegra_periph_clk_ops = { | |
730 | .init = &tegra2_periph_clk_init, | |
731 | .enable = &tegra2_periph_clk_enable, | |
732 | .disable = &tegra2_periph_clk_disable, | |
733 | .set_parent = &tegra2_periph_clk_set_parent, | |
734 | .set_rate = &tegra2_periph_clk_set_rate, | |
735 | .recalculate_rate = &tegra2_clk_recalculate_rate, | |
736 | }; | |
737 | ||
738 | /* Clock doubler ops */ | |
739 | static void tegra2_clk_double_init(struct clk *c) | |
740 | { | |
741 | c->mul = 2; | |
742 | c->div = 1; | |
743 | c->state = ON; | |
744 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & | |
745 | PERIPH_CLK_TO_ENB_BIT(c))) | |
746 | c->state = OFF; | |
747 | tegra2_clk_recalculate_rate(c); | |
748 | }; | |
749 | ||
750 | static struct clk_ops tegra_clk_double_ops = { | |
751 | .init = &tegra2_clk_double_init, | |
752 | .enable = &tegra2_periph_clk_enable, | |
753 | .disable = &tegra2_periph_clk_disable, | |
754 | .recalculate_rate = &tegra2_clk_recalculate_rate, | |
755 | }; | |
756 | ||
757 | /* Clock definitions */ | |
758 | static struct clk tegra_clk_32k = { | |
759 | .name = "clk_32k", | |
760 | .rate = 32678, | |
761 | .ops = NULL, | |
762 | }; | |
763 | ||
764 | static struct clk_pll_table tegra_pll_s_table[] = { | |
765 | {32768, 12000000, 366, 1, 1, 0}, | |
766 | {32768, 13000000, 397, 1, 1, 0}, | |
767 | {32768, 19200000, 586, 1, 1, 0}, | |
768 | {32768, 26000000, 793, 1, 1, 0}, | |
769 | {0, 0, 0, 0, 0, 0}, | |
770 | }; | |
771 | ||
772 | static struct clk tegra_pll_s = { | |
773 | .name = "pll_s", | |
774 | .flags = PLL_ALT_MISC_REG, | |
775 | .ops = &tegra_pll_ops, | |
776 | .reg = 0xf0, | |
777 | .input_min = 32768, | |
778 | .input_max = 32768, | |
779 | .parent = &tegra_clk_32k, | |
780 | .cf_min = 0, /* FIXME */ | |
781 | .cf_max = 0, /* FIXME */ | |
782 | .vco_min = 12000000, | |
783 | .vco_max = 26000000, | |
784 | .pll_table = tegra_pll_s_table, | |
785 | }; | |
786 | ||
787 | static struct clk_mux_sel tegra_clk_m_sel[] = { | |
788 | { .input = &tegra_clk_32k, .value = 0}, | |
789 | { .input = &tegra_pll_s, .value = 1}, | |
790 | { 0, 0}, | |
791 | }; | |
792 | static struct clk tegra_clk_m = { | |
793 | .name = "clk_m", | |
794 | .flags = ENABLE_ON_INIT, | |
795 | .ops = &tegra_clk_m_ops, | |
796 | .inputs = tegra_clk_m_sel, | |
797 | .reg = 0x1fc, | |
798 | .reg_mask = (1<<28), | |
799 | .reg_shift = 28, | |
800 | }; | |
801 | ||
802 | static struct clk_pll_table tegra_pll_c_table[] = { | |
803 | { 0, 0, 0, 0, 0, 0 }, | |
804 | }; | |
805 | ||
806 | static struct clk tegra_pll_c = { | |
807 | .name = "pll_c", | |
808 | .flags = PLL_HAS_CPCON, | |
809 | .ops = &tegra_pll_ops, | |
810 | .reg = 0x80, | |
811 | .input_min = 2000000, | |
812 | .input_max = 31000000, | |
813 | .parent = &tegra_clk_m, | |
814 | .cf_min = 1000000, | |
815 | .cf_max = 6000000, | |
816 | .vco_min = 20000000, | |
817 | .vco_max = 1400000000, | |
818 | .pll_table = tegra_pll_c_table, | |
819 | }; | |
820 | ||
821 | static struct clk tegra_pll_c_out1 = { | |
822 | .name = "pll_c_out1", | |
823 | .ops = &tegra_pll_div_ops, | |
824 | .flags = DIV_U71, | |
825 | .parent = &tegra_pll_c, | |
826 | .reg = 0x84, | |
827 | .reg_shift = 0, | |
828 | }; | |
829 | ||
830 | static struct clk_pll_table tegra_pll_m_table[] = { | |
831 | { 0, 0, 0, 0, 0, 0 }, | |
832 | }; | |
833 | ||
834 | static struct clk tegra_pll_m = { | |
835 | .name = "pll_m", | |
836 | .flags = PLL_HAS_CPCON, | |
837 | .ops = &tegra_pll_ops, | |
838 | .reg = 0x90, | |
839 | .input_min = 2000000, | |
840 | .input_max = 31000000, | |
841 | .parent = &tegra_clk_m, | |
842 | .cf_min = 1000000, | |
843 | .cf_max = 6000000, | |
844 | .vco_min = 20000000, | |
845 | .vco_max = 1200000000, | |
846 | .pll_table = tegra_pll_m_table, | |
847 | }; | |
848 | ||
849 | static struct clk tegra_pll_m_out1 = { | |
850 | .name = "pll_m_out1", | |
851 | .ops = &tegra_pll_div_ops, | |
852 | .flags = DIV_U71, | |
853 | .parent = &tegra_pll_m, | |
854 | .reg = 0x94, | |
855 | .reg_shift = 0, | |
856 | }; | |
857 | ||
858 | static struct clk_pll_table tegra_pll_p_table[] = { | |
859 | { 12000000, 216000000, 432, 12, 2, 8}, | |
860 | { 13000000, 216000000, 432, 13, 2, 8}, | |
861 | { 19200000, 216000000, 90, 4, 2, 1}, | |
862 | { 26000000, 216000000, 432, 26, 2, 8}, | |
863 | { 12000000, 432000000, 432, 12, 1, 8}, | |
864 | { 13000000, 432000000, 432, 13, 1, 8}, | |
865 | { 19200000, 432000000, 90, 4, 1, 1}, | |
866 | { 26000000, 432000000, 432, 26, 1, 8}, | |
867 | { 0, 0, 0, 0, 0, 0 }, | |
868 | }; | |
869 | ||
870 | static struct clk tegra_pll_p = { | |
871 | .name = "pll_p", | |
872 | .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, | |
873 | .ops = &tegra_pll_ops, | |
874 | .reg = 0xa0, | |
875 | .input_min = 2000000, | |
876 | .input_max = 31000000, | |
877 | .parent = &tegra_clk_m, | |
878 | .cf_min = 1000000, | |
879 | .cf_max = 6000000, | |
880 | .vco_min = 20000000, | |
881 | .vco_max = 1400000000, | |
882 | .pll_table = tegra_pll_p_table, | |
883 | }; | |
884 | ||
885 | static struct clk tegra_pll_p_out1 = { | |
886 | .name = "pll_p_out1", | |
887 | .ops = &tegra_pll_div_ops, | |
888 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
889 | .parent = &tegra_pll_p, | |
890 | .reg = 0xa4, | |
891 | .reg_shift = 0, | |
892 | }; | |
893 | ||
894 | static struct clk tegra_pll_p_out2 = { | |
895 | .name = "pll_p_out2", | |
896 | .ops = &tegra_pll_div_ops, | |
897 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
898 | .parent = &tegra_pll_p, | |
899 | .reg = 0xa4, | |
900 | .reg_shift = 16, | |
901 | }; | |
902 | ||
903 | static struct clk tegra_pll_p_out3 = { | |
904 | .name = "pll_p_out3", | |
905 | .ops = &tegra_pll_div_ops, | |
906 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
907 | .parent = &tegra_pll_p, | |
908 | .reg = 0xa8, | |
909 | .reg_shift = 0, | |
910 | }; | |
911 | ||
912 | static struct clk tegra_pll_p_out4 = { | |
913 | .name = "pll_p_out4", | |
914 | .ops = &tegra_pll_div_ops, | |
915 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
916 | .parent = &tegra_pll_p, | |
917 | .reg = 0xa8, | |
918 | .reg_shift = 16, | |
919 | }; | |
920 | ||
921 | static struct clk_pll_table tegra_pll_a_table[] = { | |
922 | { 28800000, 56448000, 49, 25, 1, 1}, | |
923 | { 28800000, 73728000, 64, 25, 1, 1}, | |
924 | { 28800000, 11289600, 49, 25, 1, 1}, | |
925 | { 28800000, 12288000, 64, 25, 1, 1}, | |
926 | { 0, 0, 0, 0, 0, 0 }, | |
927 | }; | |
928 | ||
929 | static struct clk tegra_pll_a = { | |
930 | .name = "pll_a", | |
931 | .flags = PLL_HAS_CPCON, | |
932 | .ops = &tegra_pll_ops, | |
933 | .reg = 0xb0, | |
934 | .input_min = 2000000, | |
935 | .input_max = 31000000, | |
936 | .parent = &tegra_pll_p_out1, | |
937 | .cf_min = 1000000, | |
938 | .cf_max = 6000000, | |
939 | .vco_min = 20000000, | |
940 | .vco_max = 1400000000, | |
941 | .pll_table = tegra_pll_a_table, | |
942 | }; | |
943 | ||
944 | static struct clk tegra_pll_a_out0 = { | |
945 | .name = "pll_a_out0", | |
946 | .ops = &tegra_pll_div_ops, | |
947 | .flags = DIV_U71, | |
948 | .parent = &tegra_pll_a, | |
949 | .reg = 0xb4, | |
950 | .reg_shift = 0, | |
951 | }; | |
952 | ||
953 | static struct clk_pll_table tegra_pll_d_table[] = { | |
954 | { 12000000, 1000000000, 1000, 12, 1, 12}, | |
955 | { 13000000, 1000000000, 1000, 13, 1, 12}, | |
956 | { 19200000, 1000000000, 625, 12, 1, 8}, | |
957 | { 26000000, 1000000000, 1000, 26, 1, 12}, | |
958 | { 0, 0, 0, 0, 0, 0 }, | |
959 | }; | |
960 | ||
961 | static struct clk tegra_pll_d = { | |
962 | .name = "pll_d", | |
963 | .flags = PLL_HAS_CPCON | PLLD, | |
964 | .ops = &tegra_pll_ops, | |
965 | .reg = 0xd0, | |
966 | .input_min = 2000000, | |
967 | .input_max = 40000000, | |
968 | .parent = &tegra_clk_m, | |
969 | .cf_min = 1000000, | |
970 | .cf_max = 6000000, | |
971 | .vco_min = 40000000, | |
972 | .vco_max = 1000000000, | |
973 | .pll_table = tegra_pll_d_table, | |
974 | }; | |
975 | ||
976 | static struct clk tegra_pll_d_out0 = { | |
977 | .name = "pll_d_out0", | |
978 | .ops = &tegra_pll_div_ops, | |
979 | .flags = DIV_2 | PLLD, | |
980 | .parent = &tegra_pll_d, | |
981 | }; | |
982 | ||
983 | static struct clk_pll_table tegra_pll_u_table[] = { | |
984 | { 12000000, 480000000, 960, 12, 1, 0}, | |
985 | { 13000000, 480000000, 960, 13, 1, 0}, | |
986 | { 19200000, 480000000, 200, 4, 1, 0}, | |
987 | { 26000000, 480000000, 960, 26, 1, 0}, | |
988 | { 0, 0, 0, 0, 0, 0 }, | |
989 | }; | |
990 | ||
991 | static struct clk tegra_pll_u = { | |
992 | .name = "pll_u", | |
993 | .flags = 0, | |
994 | .ops = &tegra_pll_ops, | |
995 | .reg = 0xc0, | |
996 | .input_min = 2000000, | |
997 | .input_max = 40000000, | |
998 | .parent = &tegra_clk_m, | |
999 | .cf_min = 1000000, | |
1000 | .cf_max = 6000000, | |
1001 | .vco_min = 480000000, | |
1002 | .vco_max = 960000000, | |
1003 | .pll_table = tegra_pll_u_table, | |
1004 | }; | |
1005 | ||
1006 | static struct clk_pll_table tegra_pll_x_table[] = { | |
1007 | { 12000000, 1000000000, 1000, 12, 1, 12}, | |
1008 | { 13000000, 1000000000, 1000, 13, 1, 12}, | |
1009 | { 19200000, 1000000000, 625, 12, 1, 8}, | |
1010 | { 26000000, 1000000000, 1000, 26, 1, 12}, | |
1011 | { 12000000, 750000000, 750, 12, 1, 12}, | |
1012 | { 13000000, 750000000, 750, 13, 1, 12}, | |
1013 | { 19200000, 750000000, 625, 16, 1, 8}, | |
1014 | { 26000000, 750000000, 750, 26, 1, 12}, | |
1015 | { 0, 0, 0, 0, 0, 0 }, | |
1016 | }; | |
1017 | ||
1018 | static struct clk tegra_pll_x = { | |
1019 | .name = "pll_x", | |
1020 | .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, | |
1021 | .ops = &tegra_pll_ops, | |
1022 | .reg = 0xe0, | |
1023 | .input_min = 2000000, | |
1024 | .input_max = 31000000, | |
1025 | .parent = &tegra_clk_m, | |
1026 | .cf_min = 1000000, | |
1027 | .cf_max = 6000000, | |
1028 | .vco_min = 20000000, | |
1029 | .vco_max = 1200000000, | |
1030 | .pll_table = tegra_pll_x_table, | |
1031 | }; | |
1032 | ||
1033 | static struct clk tegra_clk_d = { | |
1034 | .name = "clk_d", | |
1035 | .flags = PERIPH_NO_RESET, | |
1036 | .ops = &tegra_clk_double_ops, | |
1037 | .clk_num = 90, | |
1038 | .reg = 0x34, | |
1039 | .reg_shift = 12, | |
1040 | .parent = &tegra_clk_m, | |
1041 | }; | |
1042 | ||
1043 | /* FIXME: need tegra_audio | |
1044 | static struct clk tegra_clk_audio_2x = { | |
1045 | .name = "clk_d", | |
1046 | .flags = PERIPH_NO_RESET, | |
1047 | .ops = &tegra_clk_double_ops, | |
1048 | .clk_num = 89, | |
1049 | .reg = 0x34, | |
1050 | .reg_shift = 8, | |
1051 | .parent = &tegra_audio, | |
1052 | } | |
1053 | */ | |
1054 | ||
1055 | static struct clk_mux_sel mux_cclk[] = { | |
1056 | { .input = &tegra_clk_m, .value = 0}, | |
1057 | { .input = &tegra_pll_c, .value = 1}, | |
1058 | { .input = &tegra_clk_32k, .value = 2}, | |
1059 | { .input = &tegra_pll_m, .value = 3}, | |
1060 | { .input = &tegra_pll_p, .value = 4}, | |
1061 | { .input = &tegra_pll_p_out4, .value = 5}, | |
1062 | { .input = &tegra_pll_p_out3, .value = 6}, | |
1063 | { .input = &tegra_clk_d, .value = 7}, | |
1064 | { .input = &tegra_pll_x, .value = 8}, | |
1065 | { 0, 0}, | |
1066 | }; | |
1067 | ||
1068 | static struct clk_mux_sel mux_sclk[] = { | |
1069 | { .input = &tegra_clk_m, .value = 0}, | |
1070 | { .input = &tegra_pll_c_out1, .value = 1}, | |
1071 | { .input = &tegra_pll_p_out4, .value = 2}, | |
1072 | { .input = &tegra_pll_p_out3, .value = 3}, | |
1073 | { .input = &tegra_pll_p_out2, .value = 4}, | |
1074 | { .input = &tegra_clk_d, .value = 5}, | |
1075 | { .input = &tegra_clk_32k, .value = 6}, | |
1076 | { .input = &tegra_pll_m_out1, .value = 7}, | |
1077 | { 0, 0}, | |
1078 | }; | |
1079 | ||
1080 | static struct clk tegra_clk_cpu = { | |
1081 | .name = "cpu", | |
1082 | .inputs = mux_cclk, | |
1083 | .reg = 0x20, | |
1084 | .ops = &tegra_super_ops, | |
1085 | }; | |
1086 | ||
1087 | static struct clk tegra_clk_sys = { | |
1088 | .name = "sys", | |
1089 | .inputs = mux_sclk, | |
1090 | .reg = 0x28, | |
1091 | .ops = &tegra_super_ops, | |
1092 | }; | |
1093 | ||
1094 | static struct clk tegra_clk_hclk = { | |
1095 | .name = "hclk", | |
1096 | .flags = DIV_BUS, | |
1097 | .parent = &tegra_clk_sys, | |
1098 | .reg = 0x30, | |
1099 | .reg_shift = 4, | |
1100 | .ops = &tegra_bus_ops, | |
1101 | }; | |
1102 | ||
1103 | static struct clk tegra_clk_pclk = { | |
1104 | .name = "pclk", | |
1105 | .flags = DIV_BUS, | |
1106 | .parent = &tegra_clk_hclk, | |
1107 | .reg = 0x30, | |
1108 | .reg_shift = 0, | |
1109 | .ops = &tegra_bus_ops, | |
1110 | }; | |
1111 | ||
1112 | static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { | |
1113 | { .input = &tegra_pll_m, .value = 0}, | |
1114 | { .input = &tegra_pll_c, .value = 1}, | |
1115 | { .input = &tegra_pll_p, .value = 2}, | |
1116 | { .input = &tegra_pll_a_out0, .value = 3}, | |
1117 | { 0, 0}, | |
1118 | }; | |
1119 | ||
1120 | static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { | |
1121 | { .input = &tegra_pll_m, .value = 0}, | |
1122 | { .input = &tegra_pll_c, .value = 1}, | |
1123 | { .input = &tegra_pll_p, .value = 2}, | |
1124 | { .input = &tegra_clk_m, .value = 3}, | |
1125 | { 0, 0}, | |
1126 | }; | |
1127 | ||
1128 | static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { | |
1129 | { .input = &tegra_pll_p, .value = 0}, | |
1130 | { .input = &tegra_pll_c, .value = 1}, | |
1131 | { .input = &tegra_pll_m, .value = 2}, | |
1132 | { .input = &tegra_clk_m, .value = 3}, | |
1133 | { 0, 0}, | |
1134 | }; | |
1135 | ||
1136 | static struct clk_mux_sel mux_plla_audio_pllp_clkm[] = { | |
1137 | {.input = &tegra_pll_a, .value = 0}, | |
1138 | /* FIXME: no mux defined for tegra_audio | |
1139 | {.input = &tegra_audio, .value = 1},*/ | |
1140 | {.input = &tegra_pll_p, .value = 2}, | |
1141 | {.input = &tegra_clk_m, .value = 3}, | |
1142 | { 0, 0}, | |
1143 | }; | |
1144 | ||
1145 | static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { | |
1146 | {.input = &tegra_pll_p, .value = 0}, | |
1147 | {.input = &tegra_pll_d_out0, .value = 1}, | |
1148 | {.input = &tegra_pll_c, .value = 2}, | |
1149 | {.input = &tegra_clk_m, .value = 3}, | |
1150 | { 0, 0}, | |
1151 | }; | |
1152 | ||
1153 | static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = { | |
1154 | {.input = &tegra_pll_p, .value = 0}, | |
1155 | {.input = &tegra_pll_c, .value = 1}, | |
1156 | /* FIXME: no mux defined for tegra_audio | |
1157 | {.input = &tegra_audio, .value = 2},*/ | |
1158 | {.input = &tegra_clk_m, .value = 3}, | |
1159 | {.input = &tegra_clk_32k, .value = 4}, | |
1160 | { 0, 0}, | |
1161 | }; | |
1162 | ||
1163 | static struct clk_mux_sel mux_pllp_pllc_pllm[] = { | |
1164 | {.input = &tegra_pll_p, .value = 0}, | |
1165 | {.input = &tegra_pll_c, .value = 1}, | |
1166 | {.input = &tegra_pll_m, .value = 2}, | |
1167 | { 0, 0}, | |
1168 | }; | |
1169 | ||
1170 | static struct clk_mux_sel mux_clk_m[] = { | |
1171 | { .input = &tegra_clk_m, .value = 0}, | |
1172 | { 0, 0}, | |
1173 | }; | |
1174 | ||
1175 | static struct clk_mux_sel mux_pllp_out3[] = { | |
1176 | { .input = &tegra_pll_p_out3, .value = 0}, | |
1177 | { 0, 0}, | |
1178 | }; | |
1179 | ||
1180 | static struct clk_mux_sel mux_plld[] = { | |
1181 | { .input = &tegra_pll_d, .value = 0}, | |
1182 | { 0, 0}, | |
1183 | }; | |
1184 | ||
1185 | static struct clk_mux_sel mux_clk_32k[] = { | |
1186 | { .input = &tegra_clk_32k, .value = 0}, | |
1187 | { 0, 0}, | |
1188 | }; | |
1189 | ||
1190 | #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _inputs, _flags) \ | |
1191 | { \ | |
1192 | .name = _name, \ | |
1193 | .lookup = { \ | |
1194 | .dev_id = _dev, \ | |
1195 | .con_id = _con, \ | |
1196 | }, \ | |
1197 | .ops = &tegra_periph_clk_ops, \ | |
1198 | .clk_num = _clk_num, \ | |
1199 | .reg = _reg, \ | |
1200 | .inputs = _inputs, \ | |
1201 | .flags = _flags, \ | |
1202 | } | |
1203 | ||
1204 | struct clk tegra_periph_clks[] = { | |
1205 | PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, mux_clk_32k, PERIPH_NO_RESET), | |
1206 | PERIPH_CLK("timer", "timer", NULL, 5, 0, mux_clk_m, 0), | |
1207 | PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, mux_plla_audio_pllp_clkm, MUX | DIV_U71), | |
1208 | PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, mux_plla_audio_pllp_clkm, MUX | DIV_U71), | |
1209 | /* FIXME: spdif has 2 clocks but 1 enable */ | |
1210 | PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, mux_plla_audio_pllp_clkm, MUX | DIV_U71), | |
1211 | PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, mux_pllp_pllc_pllm, MUX | DIV_U71), | |
1212 | PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), | |
1213 | PERIPH_CLK("spi", "spi", NULL, 43, 0x114, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1214 | PERIPH_CLK("xio", "xio", NULL, 45, 0x120, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1215 | PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1216 | PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1217 | PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1218 | PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1219 | PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1220 | PERIPH_CLK("ide", "ide", NULL, 25, 0x144, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1221 | PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1222 | /* FIXME: vfir shares an enable with uartb */ | |
1223 | PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1224 | PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1225 | PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1226 | PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1227 | PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1228 | PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1229 | PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1230 | /* FIXME: what is la? */ | |
1231 | PERIPH_CLK("la", "la", NULL, 76, 0x1f8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1232 | PERIPH_CLK("owr", "owr", NULL, 71, 0x1cc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1233 | PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1234 | PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1235 | PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1236 | PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1237 | PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1238 | PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1239 | PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, mux_pllp_out3, 0), | |
1240 | PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, mux_pllp_out3, 0), | |
1241 | PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, mux_pllp_out3, 0), | |
1242 | PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, mux_pllp_out3, 0), | |
1243 | PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1244 | PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1245 | PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1246 | PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1247 | PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
1248 | PERIPH_CLK("3d", "3d", NULL, 24, 0x158, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), | |
1249 | PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), | |
1250 | /* FIXME: vi and vi_sensor share an enable */ | |
1251 | PERIPH_CLK("vi", "vi", NULL, 20, 0x148, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), | |
1252 | PERIPH_CLK("vi_sensor", "vi_sensor", NULL, 20, 0x1a8, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), | |
1253 | PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), | |
1254 | PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), | |
1255 | PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), | |
1256 | /* FIXME: cve and tvo share an enable */ | |
1257 | PERIPH_CLK("cve", "cve", NULL, 49, 0x140, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), | |
1258 | PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), | |
1259 | PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), | |
1260 | PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), | |
1261 | PERIPH_CLK("disp1", "tegrafb.0", NULL, 27, 0x138, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), | |
1262 | PERIPH_CLK("disp2", "tegrafb.1", NULL, 26, 0x13c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), | |
1263 | PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, mux_clk_m, 0), | |
1264 | PERIPH_CLK("usb2", "usb.1", NULL, 58, 0, mux_clk_m, 0), | |
1265 | PERIPH_CLK("usb3", "usb.2", NULL, 59, 0, mux_clk_m, 0), | |
1266 | PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB), | |
1267 | PERIPH_CLK("dsi", "dsi", NULL, 48, 0, mux_plld, 0), | |
1268 | }; | |
1269 | ||
1270 | #define CLK_DUPLICATE(_name, _dev, _con) \ | |
1271 | { \ | |
1272 | .name = _name, \ | |
1273 | .lookup = { \ | |
1274 | .dev_id = _dev, \ | |
1275 | .con_id = _con, \ | |
1276 | }, \ | |
1277 | } | |
1278 | ||
1279 | /* Some clocks may be used by different drivers depending on the board | |
1280 | * configuration. List those here to register them twice in the clock lookup | |
1281 | * table under two names. | |
1282 | */ | |
1283 | struct clk_duplicate tegra_clk_duplicates[] = { | |
1284 | CLK_DUPLICATE("uarta", "tegra_uart.0", NULL), | |
1285 | CLK_DUPLICATE("uartb", "tegra_uart.1", NULL), | |
1286 | CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), | |
1287 | CLK_DUPLICATE("uartd", "tegra_uart.3", NULL), | |
1288 | CLK_DUPLICATE("uarte", "tegra_uart.4", NULL), | |
1289 | }; | |
1290 | ||
1291 | #define CLK(dev, con, ck) \ | |
1292 | { \ | |
1293 | .dev_id = dev, \ | |
1294 | .con_id = con, \ | |
1295 | .clk = ck, \ | |
1296 | } | |
1297 | ||
1298 | struct clk_lookup tegra_clk_lookups[] = { | |
1299 | /* external root sources */ | |
1300 | CLK(NULL, "32k_clk", &tegra_clk_32k), | |
1301 | CLK(NULL, "pll_s", &tegra_pll_s), | |
1302 | CLK(NULL, "clk_m", &tegra_clk_m), | |
1303 | CLK(NULL, "pll_m", &tegra_pll_m), | |
1304 | CLK(NULL, "pll_m_out1", &tegra_pll_m_out1), | |
1305 | CLK(NULL, "pll_c", &tegra_pll_c), | |
1306 | CLK(NULL, "pll_c_out1", &tegra_pll_c_out1), | |
1307 | CLK(NULL, "pll_p", &tegra_pll_p), | |
1308 | CLK(NULL, "pll_p_out1", &tegra_pll_p_out1), | |
1309 | CLK(NULL, "pll_p_out2", &tegra_pll_p_out2), | |
1310 | CLK(NULL, "pll_p_out3", &tegra_pll_p_out3), | |
1311 | CLK(NULL, "pll_p_out4", &tegra_pll_p_out4), | |
1312 | CLK(NULL, "pll_a", &tegra_pll_a), | |
1313 | CLK(NULL, "pll_a_out0", &tegra_pll_a_out0), | |
1314 | CLK(NULL, "pll_d", &tegra_pll_d), | |
1315 | CLK(NULL, "pll_d_out0", &tegra_pll_d_out0), | |
1316 | CLK(NULL, "pll_u", &tegra_pll_u), | |
1317 | CLK(NULL, "pll_x", &tegra_pll_x), | |
1318 | CLK(NULL, "cpu", &tegra_clk_cpu), | |
1319 | CLK(NULL, "sys", &tegra_clk_sys), | |
1320 | CLK(NULL, "hclk", &tegra_clk_hclk), | |
1321 | CLK(NULL, "pclk", &tegra_clk_pclk), | |
1322 | CLK(NULL, "clk_d", &tegra_clk_d), | |
1323 | }; | |
1324 | ||
1325 | void __init tegra2_init_clocks(void) | |
1326 | { | |
1327 | int i; | |
1328 | struct clk_lookup *cl; | |
1329 | struct clk *c; | |
1330 | struct clk_duplicate *cd; | |
1331 | ||
1332 | for (i = 0; i < ARRAY_SIZE(tegra_clk_lookups); i++) { | |
1333 | cl = &tegra_clk_lookups[i]; | |
1334 | clk_init(cl->clk); | |
1335 | clkdev_add(cl); | |
1336 | } | |
1337 | ||
1338 | for (i = 0; i < ARRAY_SIZE(tegra_periph_clks); i++) { | |
1339 | c = &tegra_periph_clks[i]; | |
1340 | cl = &c->lookup; | |
1341 | cl->clk = c; | |
1342 | ||
1343 | clk_init(cl->clk); | |
1344 | clkdev_add(cl); | |
1345 | } | |
1346 | ||
1347 | for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { | |
1348 | cd = &tegra_clk_duplicates[i]; | |
1349 | c = tegra_get_clock_by_name(cd->name); | |
1350 | if (c) { | |
1351 | cl = &cd->lookup; | |
1352 | cl->clk = c; | |
1353 | clkdev_add(cl); | |
1354 | } else { | |
1355 | pr_err("%s: Unknown duplicate clock %s\n", __func__, | |
1356 | cd->name); | |
1357 | } | |
1358 | } | |
1359 | } |