Commit | Line | Data |
---|---|---|
d9cc6f76 PDS |
1 | /* |
2 | * arch/arm/mach-tegra/tegra30_clocks.c | |
3 | * | |
88e790a4 | 4 | * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. |
d9cc6f76 PDS |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/cpufreq.h> | |
30 | #include <linux/syscore_ops.h> | |
31 | ||
32 | #include <asm/clkdev.h> | |
33 | ||
d9cc6f76 PDS |
34 | #include "clock.h" |
35 | #include "fuse.h" | |
2be39c07 | 36 | #include "iomap.h" |
dab403ef | 37 | #include "tegra_cpu_car.h" |
d9cc6f76 PDS |
38 | |
39 | #define USE_PLL_LOCK_BITS 0 | |
40 | ||
41 | #define RST_DEVICES_L 0x004 | |
42 | #define RST_DEVICES_H 0x008 | |
43 | #define RST_DEVICES_U 0x00C | |
44 | #define RST_DEVICES_V 0x358 | |
45 | #define RST_DEVICES_W 0x35C | |
46 | #define RST_DEVICES_SET_L 0x300 | |
47 | #define RST_DEVICES_CLR_L 0x304 | |
48 | #define RST_DEVICES_SET_V 0x430 | |
49 | #define RST_DEVICES_CLR_V 0x434 | |
50 | #define RST_DEVICES_NUM 5 | |
51 | ||
52 | #define CLK_OUT_ENB_L 0x010 | |
53 | #define CLK_OUT_ENB_H 0x014 | |
54 | #define CLK_OUT_ENB_U 0x018 | |
55 | #define CLK_OUT_ENB_V 0x360 | |
56 | #define CLK_OUT_ENB_W 0x364 | |
57 | #define CLK_OUT_ENB_SET_L 0x320 | |
58 | #define CLK_OUT_ENB_CLR_L 0x324 | |
59 | #define CLK_OUT_ENB_SET_V 0x440 | |
60 | #define CLK_OUT_ENB_CLR_V 0x444 | |
61 | #define CLK_OUT_ENB_NUM 5 | |
62 | ||
63 | #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) | |
64 | #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1) | |
65 | ||
66 | #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32)) | |
67 | #define PERIPH_CLK_TO_RST_REG(c) \ | |
68 | periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4) | |
69 | #define PERIPH_CLK_TO_RST_SET_REG(c) \ | |
70 | periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8) | |
71 | #define PERIPH_CLK_TO_RST_CLR_REG(c) \ | |
72 | periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8) | |
73 | ||
74 | #define PERIPH_CLK_TO_ENB_REG(c) \ | |
75 | periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4) | |
76 | #define PERIPH_CLK_TO_ENB_SET_REG(c) \ | |
77 | periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8) | |
78 | #define PERIPH_CLK_TO_ENB_CLR_REG(c) \ | |
79 | periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8) | |
80 | ||
81 | #define CLK_MASK_ARM 0x44 | |
82 | #define MISC_CLK_ENB 0x48 | |
83 | ||
84 | #define OSC_CTRL 0x50 | |
85 | #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) | |
86 | #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28) | |
87 | #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28) | |
88 | #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28) | |
89 | #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28) | |
90 | #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28) | |
91 | #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28) | |
92 | #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28) | |
93 | #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) | |
94 | ||
95 | #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) | |
96 | #define OSC_CTRL_PLL_REF_DIV_1 (0<<26) | |
97 | #define OSC_CTRL_PLL_REF_DIV_2 (1<<26) | |
98 | #define OSC_CTRL_PLL_REF_DIV_4 (2<<26) | |
99 | ||
100 | #define OSC_FREQ_DET 0x58 | |
101 | #define OSC_FREQ_DET_TRIG (1<<31) | |
102 | ||
103 | #define OSC_FREQ_DET_STATUS 0x5C | |
104 | #define OSC_FREQ_DET_BUSY (1<<31) | |
105 | #define OSC_FREQ_DET_CNT_MASK 0xFFFF | |
106 | ||
107 | #define PERIPH_CLK_SOURCE_I2S1 0x100 | |
108 | #define PERIPH_CLK_SOURCE_EMC 0x19c | |
109 | #define PERIPH_CLK_SOURCE_OSC 0x1fc | |
110 | #define PERIPH_CLK_SOURCE_NUM1 \ | |
111 | ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) | |
112 | ||
113 | #define PERIPH_CLK_SOURCE_G3D2 0x3b0 | |
114 | #define PERIPH_CLK_SOURCE_SE 0x42c | |
115 | #define PERIPH_CLK_SOURCE_NUM2 \ | |
116 | ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) | |
117 | ||
118 | #define AUDIO_DLY_CLK 0x49c | |
119 | #define AUDIO_SYNC_CLK_SPDIF 0x4b4 | |
120 | #define PERIPH_CLK_SOURCE_NUM3 \ | |
121 | ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1) | |
122 | ||
123 | #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ | |
124 | PERIPH_CLK_SOURCE_NUM2 + \ | |
125 | PERIPH_CLK_SOURCE_NUM3) | |
126 | ||
127 | #define CPU_SOFTRST_CTRL 0x380 | |
128 | ||
129 | #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF | |
130 | #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF | |
131 | #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 | |
132 | #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8 | |
133 | #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50 | |
134 | #define PERIPH_CLK_UART_DIV_ENB (1<<24) | |
135 | #define PERIPH_CLK_VI_SEL_EX_SHIFT 24 | |
136 | #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT) | |
137 | #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8) | |
138 | #define PERIPH_CLK_DTV_POLARITY_INV (1<<25) | |
139 | ||
140 | #define AUDIO_SYNC_SOURCE_MASK 0x0F | |
141 | #define AUDIO_SYNC_DISABLE_BIT 0x10 | |
142 | #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4) | |
143 | ||
144 | #define PLL_BASE 0x0 | |
145 | #define PLL_BASE_BYPASS (1<<31) | |
146 | #define PLL_BASE_ENABLE (1<<30) | |
147 | #define PLL_BASE_REF_ENABLE (1<<29) | |
148 | #define PLL_BASE_OVERRIDE (1<<28) | |
149 | #define PLL_BASE_LOCK (1<<27) | |
150 | #define PLL_BASE_DIVP_MASK (0x7<<20) | |
151 | #define PLL_BASE_DIVP_SHIFT 20 | |
152 | #define PLL_BASE_DIVN_MASK (0x3FF<<8) | |
153 | #define PLL_BASE_DIVN_SHIFT 8 | |
154 | #define PLL_BASE_DIVM_MASK (0x1F) | |
155 | #define PLL_BASE_DIVM_SHIFT 0 | |
156 | ||
157 | #define PLL_OUT_RATIO_MASK (0xFF<<8) | |
158 | #define PLL_OUT_RATIO_SHIFT 8 | |
159 | #define PLL_OUT_OVERRIDE (1<<2) | |
160 | #define PLL_OUT_CLKEN (1<<1) | |
161 | #define PLL_OUT_RESET_DISABLE (1<<0) | |
162 | ||
163 | #define PLL_MISC(c) \ | |
164 | (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) | |
165 | #define PLL_MISC_LOCK_ENABLE(c) \ | |
166 | (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18)) | |
167 | ||
168 | #define PLL_MISC_DCCON_SHIFT 20 | |
169 | #define PLL_MISC_CPCON_SHIFT 8 | |
170 | #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) | |
171 | #define PLL_MISC_LFCON_SHIFT 4 | |
172 | #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) | |
173 | #define PLL_MISC_VCOCON_SHIFT 0 | |
174 | #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) | |
175 | #define PLLD_MISC_CLKENABLE (1<<30) | |
176 | ||
177 | #define PLLU_BASE_POST_DIV (1<<20) | |
178 | ||
179 | #define PLLD_BASE_DSIB_MUX_SHIFT 25 | |
180 | #define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT) | |
181 | #define PLLD_BASE_CSI_CLKENABLE (1<<26) | |
182 | #define PLLD_MISC_DSI_CLKENABLE (1<<30) | |
183 | #define PLLD_MISC_DIV_RST (1<<23) | |
184 | #define PLLD_MISC_DCCON_SHIFT 12 | |
185 | ||
186 | #define PLLDU_LFCON_SET_DIVN 600 | |
187 | ||
188 | /* FIXME: OUT_OF_TABLE_CPCON per pll */ | |
189 | #define OUT_OF_TABLE_CPCON 0x8 | |
190 | ||
191 | #define SUPER_CLK_MUX 0x00 | |
192 | #define SUPER_STATE_SHIFT 28 | |
193 | #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) | |
194 | #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) | |
195 | #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) | |
196 | #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) | |
197 | #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) | |
198 | #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) | |
199 | #define SUPER_LP_DIV2_BYPASS (0x1 << 16) | |
200 | #define SUPER_SOURCE_MASK 0xF | |
201 | #define SUPER_FIQ_SOURCE_SHIFT 12 | |
202 | #define SUPER_IRQ_SOURCE_SHIFT 8 | |
203 | #define SUPER_RUN_SOURCE_SHIFT 4 | |
204 | #define SUPER_IDLE_SOURCE_SHIFT 0 | |
205 | ||
206 | #define SUPER_CLK_DIVIDER 0x04 | |
207 | #define SUPER_CLOCK_DIV_U71_SHIFT 16 | |
208 | #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT) | |
209 | /* guarantees safe cpu backup */ | |
210 | #define SUPER_CLOCK_DIV_U71_MIN 0x2 | |
211 | ||
212 | #define BUS_CLK_DISABLE (1<<3) | |
213 | #define BUS_CLK_DIV_MASK 0x3 | |
214 | ||
215 | #define PMC_CTRL 0x0 | |
216 | #define PMC_CTRL_BLINK_ENB (1 << 7) | |
217 | ||
218 | #define PMC_DPD_PADS_ORIDE 0x1c | |
219 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) | |
220 | ||
221 | #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 | |
222 | #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff | |
223 | #define PMC_BLINK_TIMER_ENB (1 << 15) | |
224 | #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 | |
225 | #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff | |
226 | ||
227 | #define PMC_PLLP_WB0_OVERRIDE 0xf8 | |
228 | #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12) | |
229 | ||
230 | #define UTMIP_PLL_CFG2 0x488 | |
231 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
232 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) | |
233 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) | |
234 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) | |
235 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) | |
236 | ||
237 | #define UTMIP_PLL_CFG1 0x484 | |
238 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
239 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
240 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) | |
241 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) | |
242 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) | |
243 | ||
244 | #define PLLE_BASE_CML_ENABLE (1<<31) | |
245 | #define PLLE_BASE_ENABLE (1<<30) | |
246 | #define PLLE_BASE_DIVCML_SHIFT 24 | |
247 | #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT) | |
248 | #define PLLE_BASE_DIVP_SHIFT 16 | |
249 | #define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT) | |
250 | #define PLLE_BASE_DIVN_SHIFT 8 | |
251 | #define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT) | |
252 | #define PLLE_BASE_DIVM_SHIFT 0 | |
253 | #define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT) | |
254 | #define PLLE_BASE_DIV_MASK \ | |
255 | (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \ | |
256 | PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK) | |
257 | #define PLLE_BASE_DIV(m, n, p, cml) \ | |
258 | (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \ | |
259 | ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT)) | |
260 | ||
261 | #define PLLE_MISC_SETUP_BASE_SHIFT 16 | |
262 | #define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT) | |
263 | #define PLLE_MISC_READY (1<<15) | |
264 | #define PLLE_MISC_LOCK (1<<11) | |
265 | #define PLLE_MISC_LOCK_ENABLE (1<<9) | |
266 | #define PLLE_MISC_SETUP_EX_SHIFT 2 | |
267 | #define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT) | |
268 | #define PLLE_MISC_SETUP_MASK \ | |
269 | (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK) | |
270 | #define PLLE_MISC_SETUP_VALUE \ | |
271 | ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT)) | |
272 | ||
273 | #define PLLE_SS_CTRL 0x68 | |
274 | #define PLLE_SS_INCINTRV_SHIFT 24 | |
275 | #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT) | |
276 | #define PLLE_SS_INC_SHIFT 16 | |
277 | #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT) | |
278 | #define PLLE_SS_MAX_SHIFT 0 | |
279 | #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT) | |
280 | #define PLLE_SS_COEFFICIENTS_MASK \ | |
281 | (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK) | |
282 | #define PLLE_SS_COEFFICIENTS_12MHZ \ | |
283 | ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ | |
284 | (0x24<<PLLE_SS_MAX_SHIFT)) | |
285 | #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10)) | |
286 | ||
287 | #define PLLE_AUX 0x48c | |
288 | #define PLLE_AUX_PLLP_SEL (1<<2) | |
289 | #define PLLE_AUX_CML_SATA_ENABLE (1<<1) | |
290 | #define PLLE_AUX_CML_PCIE_ENABLE (1<<0) | |
291 | ||
292 | #define PMC_SATA_PWRGT 0x1ac | |
293 | #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5) | |
294 | #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4) | |
295 | ||
296 | #define ROUND_DIVIDER_UP 0 | |
297 | #define ROUND_DIVIDER_DOWN 1 | |
298 | ||
299 | /* FIXME: recommended safety delay after lock is detected */ | |
300 | #define PLL_POST_LOCK_DELAY 100 | |
301 | ||
dab403ef JL |
302 | /* Tegra CPU clock and reset control regs */ |
303 | #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c | |
304 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 | |
305 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 | |
306 | #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c | |
307 | #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 | |
308 | ||
309 | #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) | |
310 | #define CPU_RESET(cpu) (0x1111ul << (cpu)) | |
311 | ||
d9cc6f76 PDS |
312 | /** |
313 | * Structure defining the fields for USB UTMI clocks Parameters. | |
314 | */ | |
315 | struct utmi_clk_param { | |
316 | /* Oscillator Frequency in KHz */ | |
317 | u32 osc_frequency; | |
318 | /* UTMIP PLL Enable Delay Count */ | |
319 | u8 enable_delay_count; | |
320 | /* UTMIP PLL Stable count */ | |
321 | u8 stable_count; | |
322 | /* UTMIP PLL Active delay count */ | |
323 | u8 active_delay_count; | |
324 | /* UTMIP PLL Xtal frequency count */ | |
325 | u8 xtal_freq_count; | |
326 | }; | |
327 | ||
328 | static const struct utmi_clk_param utmi_parameters[] = { | |
329 | { | |
330 | .osc_frequency = 13000000, | |
331 | .enable_delay_count = 0x02, | |
332 | .stable_count = 0x33, | |
333 | .active_delay_count = 0x05, | |
334 | .xtal_freq_count = 0x7F | |
335 | }, | |
336 | { | |
337 | .osc_frequency = 19200000, | |
338 | .enable_delay_count = 0x03, | |
339 | .stable_count = 0x4B, | |
340 | .active_delay_count = 0x06, | |
341 | .xtal_freq_count = 0xBB}, | |
342 | { | |
343 | .osc_frequency = 12000000, | |
344 | .enable_delay_count = 0x02, | |
345 | .stable_count = 0x2F, | |
346 | .active_delay_count = 0x04, | |
347 | .xtal_freq_count = 0x76 | |
348 | }, | |
349 | { | |
350 | .osc_frequency = 26000000, | |
351 | .enable_delay_count = 0x04, | |
352 | .stable_count = 0x66, | |
353 | .active_delay_count = 0x09, | |
354 | .xtal_freq_count = 0xFE | |
355 | }, | |
356 | { | |
357 | .osc_frequency = 16800000, | |
358 | .enable_delay_count = 0x03, | |
359 | .stable_count = 0x41, | |
360 | .active_delay_count = 0x0A, | |
361 | .xtal_freq_count = 0xA4 | |
362 | }, | |
363 | }; | |
364 | ||
365 | static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); | |
366 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); | |
367 | static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); | |
368 | ||
369 | #define MISC_GP_HIDREV 0x804 | |
370 | ||
371 | /* | |
372 | * Some peripheral clocks share an enable bit, so refcount the enable bits | |
373 | * in registers CLK_ENABLE_L, ... CLK_ENABLE_W | |
374 | */ | |
375 | static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; | |
376 | ||
377 | #define clk_writel(value, reg) \ | |
fa67ccb6 | 378 | __raw_writel(value, reg_clk_base + (reg)) |
d9cc6f76 | 379 | #define clk_readl(reg) \ |
fa67ccb6 | 380 | __raw_readl(reg_clk_base + (reg)) |
d9cc6f76 | 381 | #define pmc_writel(value, reg) \ |
fa67ccb6 | 382 | __raw_writel(value, reg_pmc_base + (reg)) |
d9cc6f76 | 383 | #define pmc_readl(reg) \ |
fa67ccb6 | 384 | __raw_readl(reg_pmc_base + (reg)) |
d9cc6f76 | 385 | #define chipid_readl() \ |
fa67ccb6 | 386 | __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV) |
d9cc6f76 PDS |
387 | |
388 | #define clk_writel_delay(value, reg) \ | |
389 | do { \ | |
fa67ccb6 | 390 | __raw_writel((value), reg_clk_base + (reg)); \ |
d9cc6f76 PDS |
391 | udelay(2); \ |
392 | } while (0) | |
393 | ||
92fe58f0 | 394 | static inline int clk_set_div(struct clk_tegra *c, u32 n) |
d9cc6f76 | 395 | { |
92fe58f0 PG |
396 | struct clk *clk = c->hw.clk; |
397 | ||
398 | return clk_set_rate(clk, | |
399 | (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n); | |
d9cc6f76 PDS |
400 | } |
401 | ||
402 | static inline u32 periph_clk_to_reg( | |
92fe58f0 | 403 | struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs) |
d9cc6f76 PDS |
404 | { |
405 | u32 reg = c->u.periph.clk_num / 32; | |
406 | BUG_ON(reg >= RST_DEVICES_NUM); | |
407 | if (reg < 3) | |
408 | reg = reg_L + (reg * offs); | |
409 | else | |
410 | reg = reg_V + ((reg - 3) * offs); | |
411 | return reg; | |
412 | } | |
413 | ||
414 | static unsigned long clk_measure_input_freq(void) | |
415 | { | |
416 | u32 clock_autodetect; | |
417 | clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); | |
418 | do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); | |
419 | clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); | |
420 | if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { | |
421 | return 12000000; | |
422 | } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { | |
423 | return 13000000; | |
424 | } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { | |
425 | return 19200000; | |
426 | } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { | |
427 | return 26000000; | |
428 | } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) { | |
429 | return 16800000; | |
430 | } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) { | |
431 | return 38400000; | |
432 | } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) { | |
433 | return 48000000; | |
434 | } else { | |
435 | pr_err("%s: Unexpected clock autodetect value %d", __func__, | |
436 | clock_autodetect); | |
437 | BUG(); | |
438 | return 0; | |
439 | } | |
440 | } | |
441 | ||
442 | static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate, | |
443 | u32 flags, u32 round_mode) | |
444 | { | |
445 | s64 divider_u71 = parent_rate; | |
446 | if (!rate) | |
447 | return -EINVAL; | |
448 | ||
449 | if (!(flags & DIV_U71_INT)) | |
450 | divider_u71 *= 2; | |
451 | if (round_mode == ROUND_DIVIDER_UP) | |
452 | divider_u71 += rate - 1; | |
453 | do_div(divider_u71, rate); | |
454 | if (flags & DIV_U71_INT) | |
455 | divider_u71 *= 2; | |
456 | ||
457 | if (divider_u71 - 2 < 0) | |
458 | return 0; | |
459 | ||
460 | if (divider_u71 - 2 > 255) | |
461 | return -EINVAL; | |
462 | ||
463 | return divider_u71 - 2; | |
464 | } | |
465 | ||
466 | static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) | |
467 | { | |
468 | s64 divider_u16; | |
469 | ||
470 | divider_u16 = parent_rate; | |
471 | if (!rate) | |
472 | return -EINVAL; | |
473 | divider_u16 += rate - 1; | |
474 | do_div(divider_u16, rate); | |
475 | ||
476 | if (divider_u16 - 1 < 0) | |
477 | return 0; | |
478 | ||
479 | if (divider_u16 - 1 > 0xFFFF) | |
480 | return -EINVAL; | |
481 | ||
482 | return divider_u16 - 1; | |
483 | } | |
484 | ||
92fe58f0 PG |
485 | static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw, |
486 | unsigned long parent_rate) | |
487 | { | |
488 | return to_clk_tegra(hw)->fixed_rate; | |
489 | } | |
490 | ||
b78c030c | 491 | struct clk_ops tegra30_clk_32k_ops = { |
92fe58f0 PG |
492 | .recalc_rate = tegra30_clk_fixed_recalc_rate, |
493 | }; | |
494 | ||
d9cc6f76 | 495 | /* clk_m functions */ |
92fe58f0 PG |
496 | static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw, |
497 | unsigned long parent_rate) | |
498 | { | |
499 | if (!to_clk_tegra(hw)->fixed_rate) | |
500 | to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq(); | |
501 | return to_clk_tegra(hw)->fixed_rate; | |
502 | } | |
503 | ||
504 | static void tegra30_clk_m_init(struct clk_hw *hw) | |
d9cc6f76 PDS |
505 | { |
506 | u32 osc_ctrl = clk_readl(OSC_CTRL); | |
507 | u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; | |
508 | u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; | |
509 | ||
92fe58f0 | 510 | switch (to_clk_tegra(hw)->fixed_rate) { |
d9cc6f76 PDS |
511 | case 12000000: |
512 | auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; | |
513 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
514 | break; | |
515 | case 13000000: | |
516 | auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; | |
517 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
518 | break; | |
519 | case 19200000: | |
520 | auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; | |
521 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
522 | break; | |
523 | case 26000000: | |
524 | auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; | |
525 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
526 | break; | |
527 | case 16800000: | |
528 | auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ; | |
529 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
530 | break; | |
531 | case 38400000: | |
532 | auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ; | |
533 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); | |
534 | break; | |
535 | case 48000000: | |
536 | auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ; | |
537 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); | |
538 | break; | |
539 | default: | |
92fe58f0 PG |
540 | pr_err("%s: Unexpected clock rate %ld", __func__, |
541 | to_clk_tegra(hw)->fixed_rate); | |
d9cc6f76 PDS |
542 | BUG(); |
543 | } | |
544 | clk_writel(auto_clock_control, OSC_CTRL); | |
d9cc6f76 PDS |
545 | } |
546 | ||
92fe58f0 PG |
547 | struct clk_ops tegra30_clk_m_ops = { |
548 | .init = tegra30_clk_m_init, | |
549 | .recalc_rate = tegra30_clk_m_recalc_rate, | |
550 | }; | |
d9cc6f76 | 551 | |
92fe58f0 PG |
552 | static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw, |
553 | unsigned long parent_rate) | |
d9cc6f76 | 554 | { |
92fe58f0 PG |
555 | struct clk_tegra *c = to_clk_tegra(hw); |
556 | u64 rate = parent_rate; | |
d9cc6f76 | 557 | |
92fe58f0 PG |
558 | if (c->mul != 0 && c->div != 0) { |
559 | rate *= c->mul; | |
560 | rate += c->div - 1; /* round up */ | |
561 | do_div(rate, c->div); | |
562 | } | |
d9cc6f76 | 563 | |
92fe58f0 PG |
564 | return rate; |
565 | } | |
d9cc6f76 | 566 | |
88e790a4 | 567 | struct clk_ops tegra_clk_m_div_ops = { |
92fe58f0 | 568 | .recalc_rate = tegra30_clk_m_div_recalc_rate, |
d9cc6f76 PDS |
569 | }; |
570 | ||
571 | /* PLL reference divider functions */ | |
92fe58f0 PG |
572 | static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw, |
573 | unsigned long parent_rate) | |
d9cc6f76 | 574 | { |
92fe58f0 PG |
575 | struct clk_tegra *c = to_clk_tegra(hw); |
576 | unsigned long rate = parent_rate; | |
d9cc6f76 | 577 | u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; |
d9cc6f76 PDS |
578 | |
579 | switch (pll_ref_div) { | |
580 | case OSC_CTRL_PLL_REF_DIV_1: | |
581 | c->div = 1; | |
582 | break; | |
583 | case OSC_CTRL_PLL_REF_DIV_2: | |
584 | c->div = 2; | |
585 | break; | |
586 | case OSC_CTRL_PLL_REF_DIV_4: | |
587 | c->div = 4; | |
588 | break; | |
589 | default: | |
590 | pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div); | |
591 | BUG(); | |
592 | } | |
593 | c->mul = 1; | |
92fe58f0 PG |
594 | |
595 | if (c->mul != 0 && c->div != 0) { | |
596 | rate *= c->mul; | |
597 | rate += c->div - 1; /* round up */ | |
598 | do_div(rate, c->div); | |
599 | } | |
600 | ||
601 | return rate; | |
d9cc6f76 PDS |
602 | } |
603 | ||
88e790a4 | 604 | struct clk_ops tegra_pll_ref_ops = { |
92fe58f0 | 605 | .recalc_rate = tegra30_pll_ref_recalc_rate, |
d9cc6f76 PDS |
606 | }; |
607 | ||
608 | /* super clock functions */ | |
609 | /* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and | |
610 | * clock skipping super divider. We will ignore the clock skipping divider, | |
611 | * since we can't lower the voltage when using the clock skip, but we can if | |
612 | * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock | |
613 | * only when its parent is a fixed rate PLL, since we can't change PLL rate | |
614 | * in this case. | |
615 | */ | |
92fe58f0 | 616 | static void tegra30_super_clk_init(struct clk_hw *hw) |
d9cc6f76 | 617 | { |
92fe58f0 PG |
618 | struct clk_tegra *c = to_clk_tegra(hw); |
619 | struct clk_tegra *p = | |
620 | to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk))); | |
d9cc6f76 | 621 | |
92fe58f0 | 622 | c->state = ON; |
d9cc6f76 PDS |
623 | if (c->flags & DIV_U71) { |
624 | /* Init safe 7.1 divider value (does not affect PLLX path) */ | |
625 | clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT, | |
626 | c->reg + SUPER_CLK_DIVIDER); | |
627 | c->mul = 2; | |
628 | c->div = 2; | |
92fe58f0 | 629 | if (!(p->flags & PLLX)) |
d9cc6f76 PDS |
630 | c->div += SUPER_CLOCK_DIV_U71_MIN; |
631 | } else | |
632 | clk_writel(0, c->reg + SUPER_CLK_DIVIDER); | |
633 | } | |
634 | ||
92fe58f0 | 635 | static u8 tegra30_super_clk_get_parent(struct clk_hw *hw) |
d9cc6f76 | 636 | { |
92fe58f0 PG |
637 | struct clk_tegra *c = to_clk_tegra(hw); |
638 | u32 val; | |
639 | int source; | |
640 | int shift; | |
d9cc6f76 | 641 | |
92fe58f0 PG |
642 | val = clk_readl(c->reg + SUPER_CLK_MUX); |
643 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | |
644 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
645 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
646 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
647 | source = (val >> shift) & SUPER_SOURCE_MASK; | |
648 | if (c->flags & DIV_2) | |
649 | source |= val & SUPER_LP_DIV2_BYPASS; | |
650 | ||
651 | return source; | |
d9cc6f76 PDS |
652 | } |
653 | ||
92fe58f0 | 654 | static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 655 | { |
92fe58f0 PG |
656 | struct clk_tegra *c = to_clk_tegra(hw); |
657 | struct clk_tegra *p = | |
658 | to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk))); | |
d9cc6f76 | 659 | u32 val; |
d9cc6f76 PDS |
660 | int shift; |
661 | ||
662 | val = clk_readl(c->reg + SUPER_CLK_MUX); | |
663 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | |
664 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
665 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
666 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
d9cc6f76 | 667 | |
92fe58f0 PG |
668 | /* For LP mode super-clock switch between PLLX direct |
669 | and divided-by-2 outputs is allowed only when other | |
670 | than PLLX clock source is current parent */ | |
671 | if ((c->flags & DIV_2) && (p->flags & PLLX) && | |
672 | ((index ^ val) & SUPER_LP_DIV2_BYPASS)) { | |
673 | if (p->flags & PLLX) | |
674 | return -EINVAL; | |
675 | val ^= SUPER_LP_DIV2_BYPASS; | |
676 | clk_writel_delay(val, c->reg); | |
677 | } | |
678 | val &= ~(SUPER_SOURCE_MASK << shift); | |
679 | val |= (index & SUPER_SOURCE_MASK) << shift; | |
d9cc6f76 | 680 | |
92fe58f0 PG |
681 | /* 7.1 divider for CPU super-clock does not affect |
682 | PLLX path */ | |
683 | if (c->flags & DIV_U71) { | |
684 | u32 div = 0; | |
685 | if (!(p->flags & PLLX)) { | |
686 | div = clk_readl(c->reg + | |
687 | SUPER_CLK_DIVIDER); | |
688 | div &= SUPER_CLOCK_DIV_U71_MASK; | |
689 | div >>= SUPER_CLOCK_DIV_U71_SHIFT; | |
d9cc6f76 | 690 | } |
92fe58f0 PG |
691 | c->div = div + 2; |
692 | c->mul = 2; | |
d9cc6f76 | 693 | } |
92fe58f0 PG |
694 | clk_writel_delay(val, c->reg); |
695 | ||
696 | return 0; | |
d9cc6f76 PDS |
697 | } |
698 | ||
699 | /* | |
700 | * Do not use super clocks "skippers", since dividing using a clock skipper | |
701 | * does not allow the voltage to be scaled down. Instead adjust the rate of | |
702 | * the parent clock. This requires that the parent of a super clock have no | |
703 | * other children, otherwise the rate will change underneath the other | |
704 | * children. Special case: if fixed rate PLL is CPU super clock parent the | |
705 | * rate of this PLL can't be changed, and it has many other children. In | |
706 | * this case use 7.1 fractional divider to adjust the super clock rate. | |
707 | */ | |
92fe58f0 PG |
708 | static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
709 | unsigned long parent_rate) | |
d9cc6f76 | 710 | { |
92fe58f0 PG |
711 | struct clk_tegra *c = to_clk_tegra(hw); |
712 | struct clk *parent = __clk_get_parent(hw->clk); | |
713 | struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent)); | |
714 | ||
715 | if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) { | |
716 | int div = clk_div71_get_divider(parent_rate, | |
d9cc6f76 PDS |
717 | rate, c->flags, ROUND_DIVIDER_DOWN); |
718 | div = max(div, SUPER_CLOCK_DIV_U71_MIN); | |
719 | ||
720 | clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT, | |
721 | c->reg + SUPER_CLK_DIVIDER); | |
722 | c->div = div + 2; | |
723 | c->mul = 2; | |
724 | return 0; | |
725 | } | |
92fe58f0 PG |
726 | return 0; |
727 | } | |
728 | ||
729 | static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw, | |
730 | unsigned long parent_rate) | |
731 | { | |
732 | struct clk_tegra *c = to_clk_tegra(hw); | |
733 | u64 rate = parent_rate; | |
734 | ||
735 | if (c->mul != 0 && c->div != 0) { | |
736 | rate *= c->mul; | |
737 | rate += c->div - 1; /* round up */ | |
738 | do_div(rate, c->div); | |
739 | } | |
740 | ||
741 | return rate; | |
742 | } | |
743 | ||
744 | static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
745 | unsigned long *prate) | |
746 | { | |
747 | struct clk_tegra *c = to_clk_tegra(hw); | |
748 | struct clk *parent = __clk_get_parent(hw->clk); | |
749 | struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent)); | |
750 | int mul = 2; | |
751 | int div; | |
752 | ||
753 | if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) { | |
754 | div = clk_div71_get_divider(*prate, | |
755 | rate, c->flags, ROUND_DIVIDER_DOWN); | |
756 | div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2; | |
757 | rate = *prate * mul; | |
758 | rate += div - 1; /* round up */ | |
759 | do_div(rate, c->div); | |
760 | ||
761 | return rate; | |
762 | } | |
763 | return *prate; | |
d9cc6f76 PDS |
764 | } |
765 | ||
88e790a4 | 766 | struct clk_ops tegra30_super_ops = { |
92fe58f0 PG |
767 | .init = tegra30_super_clk_init, |
768 | .set_parent = tegra30_super_clk_set_parent, | |
769 | .get_parent = tegra30_super_clk_get_parent, | |
770 | .recalc_rate = tegra30_super_clk_recalc_rate, | |
771 | .round_rate = tegra30_super_clk_round_rate, | |
772 | .set_rate = tegra30_super_clk_set_rate, | |
d9cc6f76 PDS |
773 | }; |
774 | ||
92fe58f0 PG |
775 | static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw, |
776 | unsigned long parent_rate) | |
d9cc6f76 | 777 | { |
92fe58f0 PG |
778 | struct clk_tegra *c = to_clk_tegra(hw); |
779 | u64 rate = parent_rate; | |
780 | ||
781 | if (c->mul != 0 && c->div != 0) { | |
782 | rate *= c->mul; | |
783 | rate += c->div - 1; /* round up */ | |
784 | do_div(rate, c->div); | |
785 | } | |
786 | ||
787 | return rate; | |
d9cc6f76 PDS |
788 | } |
789 | ||
88e790a4 | 790 | struct clk_ops tegra30_twd_ops = { |
92fe58f0 | 791 | .recalc_rate = tegra30_twd_clk_recalc_rate, |
d9cc6f76 PDS |
792 | }; |
793 | ||
794 | /* Blink output functions */ | |
92fe58f0 | 795 | static int tegra30_blink_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 796 | { |
92fe58f0 | 797 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
798 | u32 val; |
799 | ||
800 | val = pmc_readl(PMC_CTRL); | |
801 | c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; | |
92fe58f0 | 802 | return c->state; |
d9cc6f76 PDS |
803 | } |
804 | ||
92fe58f0 | 805 | static int tegra30_blink_clk_enable(struct clk_hw *hw) |
d9cc6f76 PDS |
806 | { |
807 | u32 val; | |
808 | ||
809 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | |
810 | pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | |
811 | ||
812 | val = pmc_readl(PMC_CTRL); | |
813 | pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
92fe58f0 | 818 | static void tegra30_blink_clk_disable(struct clk_hw *hw) |
d9cc6f76 PDS |
819 | { |
820 | u32 val; | |
821 | ||
822 | val = pmc_readl(PMC_CTRL); | |
823 | pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); | |
824 | ||
825 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | |
826 | pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | |
827 | } | |
828 | ||
92fe58f0 PG |
829 | static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
830 | unsigned long parent_rate) | |
d9cc6f76 | 831 | { |
92fe58f0 PG |
832 | struct clk_tegra *c = to_clk_tegra(hw); |
833 | ||
d9cc6f76 PDS |
834 | if (rate >= parent_rate) { |
835 | c->div = 1; | |
836 | pmc_writel(0, c->reg); | |
837 | } else { | |
838 | unsigned int on_off; | |
839 | u32 val; | |
840 | ||
841 | on_off = DIV_ROUND_UP(parent_rate / 8, rate); | |
842 | c->div = on_off * 8; | |
843 | ||
844 | val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << | |
845 | PMC_BLINK_TIMER_DATA_ON_SHIFT; | |
846 | on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; | |
847 | on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | |
848 | val |= on_off; | |
849 | val |= PMC_BLINK_TIMER_ENB; | |
850 | pmc_writel(val, c->reg); | |
851 | } | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
92fe58f0 PG |
856 | static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw, |
857 | unsigned long parent_rate) | |
858 | { | |
859 | struct clk_tegra *c = to_clk_tegra(hw); | |
860 | u64 rate = parent_rate; | |
861 | u32 val; | |
862 | u32 mul; | |
863 | u32 div; | |
864 | u32 on_off; | |
d9cc6f76 | 865 | |
92fe58f0 PG |
866 | mul = 1; |
867 | val = pmc_readl(c->reg); | |
868 | ||
869 | if (val & PMC_BLINK_TIMER_ENB) { | |
870 | on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & | |
871 | PMC_BLINK_TIMER_DATA_ON_MASK; | |
872 | val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | |
873 | val &= PMC_BLINK_TIMER_DATA_OFF_MASK; | |
874 | on_off += val; | |
875 | /* each tick in the blink timer is 4 32KHz clocks */ | |
876 | div = on_off * 4; | |
877 | } else { | |
878 | div = 1; | |
879 | } | |
880 | ||
881 | if (mul != 0 && div != 0) { | |
882 | rate *= mul; | |
883 | rate += div - 1; /* round up */ | |
884 | do_div(rate, div); | |
885 | } | |
886 | return rate; | |
887 | } | |
888 | ||
889 | static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
890 | unsigned long *prate) | |
d9cc6f76 | 891 | { |
92fe58f0 PG |
892 | int div; |
893 | int mul; | |
894 | long round_rate = *prate; | |
895 | ||
896 | mul = 1; | |
897 | ||
898 | if (rate >= *prate) { | |
899 | div = 1; | |
900 | } else { | |
901 | div = DIV_ROUND_UP(*prate / 8, rate); | |
902 | div *= 8; | |
d9cc6f76 | 903 | } |
d9cc6f76 | 904 | |
92fe58f0 PG |
905 | round_rate *= mul; |
906 | round_rate += div - 1; | |
907 | do_div(round_rate, div); | |
908 | ||
909 | return round_rate; | |
d9cc6f76 PDS |
910 | } |
911 | ||
92fe58f0 PG |
912 | struct clk_ops tegra30_blink_clk_ops = { |
913 | .is_enabled = tegra30_blink_clk_is_enabled, | |
914 | .enable = tegra30_blink_clk_enable, | |
915 | .disable = tegra30_blink_clk_disable, | |
916 | .recalc_rate = tegra30_blink_clk_recalc_rate, | |
917 | .round_rate = tegra30_blink_clk_round_rate, | |
918 | .set_rate = tegra30_blink_clk_set_rate, | |
919 | }; | |
920 | ||
921 | static void tegra30_utmi_param_configure(struct clk_hw *hw) | |
d9cc6f76 | 922 | { |
92fe58f0 PG |
923 | unsigned long main_rate = |
924 | __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk))); | |
d9cc6f76 PDS |
925 | u32 reg; |
926 | int i; | |
d9cc6f76 PDS |
927 | |
928 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { | |
929 | if (main_rate == utmi_parameters[i].osc_frequency) | |
930 | break; | |
931 | } | |
932 | ||
933 | if (i >= ARRAY_SIZE(utmi_parameters)) { | |
934 | pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate); | |
935 | return; | |
936 | } | |
937 | ||
938 | reg = clk_readl(UTMIP_PLL_CFG2); | |
939 | ||
940 | /* Program UTMIP PLL stable and active counts */ | |
941 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ | |
942 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); | |
943 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT( | |
944 | utmi_parameters[i].stable_count); | |
945 | ||
946 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); | |
947 | ||
948 | reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( | |
949 | utmi_parameters[i].active_delay_count); | |
950 | ||
951 | /* Remove power downs from UTMIP PLL control bits */ | |
952 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; | |
953 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; | |
954 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; | |
955 | ||
956 | clk_writel(reg, UTMIP_PLL_CFG2); | |
957 | ||
958 | /* Program UTMIP PLL delay and oscillator frequency counts */ | |
959 | reg = clk_readl(UTMIP_PLL_CFG1); | |
960 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); | |
961 | ||
962 | reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( | |
963 | utmi_parameters[i].enable_delay_count); | |
964 | ||
965 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); | |
966 | reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( | |
967 | utmi_parameters[i].xtal_freq_count); | |
968 | ||
969 | /* Remove power downs from UTMIP PLL control bits */ | |
970 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
971 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; | |
972 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; | |
973 | ||
974 | clk_writel(reg, UTMIP_PLL_CFG1); | |
975 | } | |
976 | ||
92fe58f0 PG |
977 | /* PLL Functions */ |
978 | static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg, | |
979 | u32 lock_bit) | |
980 | { | |
981 | int ret = 0; | |
982 | ||
983 | #if USE_PLL_LOCK_BITS | |
984 | int i; | |
985 | for (i = 0; i < c->u.pll.lock_delay; i++) { | |
986 | if (clk_readl(lock_reg) & lock_bit) { | |
987 | udelay(PLL_POST_LOCK_DELAY); | |
988 | return 0; | |
989 | } | |
990 | udelay(2); /* timeout = 2 * lock time */ | |
991 | } | |
992 | pr_err("Timed out waiting for lock bit on pll %s", | |
993 | __clk_get_name(hw->clk)); | |
994 | ret = -1; | |
995 | #else | |
996 | udelay(c->u.pll.lock_delay); | |
997 | #endif | |
998 | return ret; | |
999 | } | |
1000 | ||
1001 | static int tegra30_pll_clk_is_enabled(struct clk_hw *hw) | |
d9cc6f76 | 1002 | { |
92fe58f0 | 1003 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1004 | u32 val = clk_readl(c->reg + PLL_BASE); |
1005 | ||
1006 | c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; | |
92fe58f0 PG |
1007 | return c->state; |
1008 | } | |
d9cc6f76 | 1009 | |
92fe58f0 PG |
1010 | static void tegra30_pll_clk_init(struct clk_hw *hw) |
1011 | { | |
1012 | struct clk_tegra *c = to_clk_tegra(hw); | |
d9cc6f76 PDS |
1013 | |
1014 | if (c->flags & PLLU) | |
92fe58f0 | 1015 | tegra30_utmi_param_configure(hw); |
d9cc6f76 PDS |
1016 | } |
1017 | ||
92fe58f0 | 1018 | static int tegra30_pll_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1019 | { |
92fe58f0 | 1020 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1021 | u32 val; |
92fe58f0 | 1022 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1023 | |
1024 | #if USE_PLL_LOCK_BITS | |
1025 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1026 | val |= PLL_MISC_LOCK_ENABLE(c); | |
1027 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1028 | #endif | |
1029 | val = clk_readl(c->reg + PLL_BASE); | |
1030 | val &= ~PLL_BASE_BYPASS; | |
1031 | val |= PLL_BASE_ENABLE; | |
1032 | clk_writel(val, c->reg + PLL_BASE); | |
1033 | ||
1034 | if (c->flags & PLLM) { | |
1035 | val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); | |
1036 | val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | |
1037 | pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); | |
1038 | } | |
1039 | ||
1040 | tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
92fe58f0 | 1045 | static void tegra30_pll_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 1046 | { |
92fe58f0 | 1047 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1048 | u32 val; |
92fe58f0 | 1049 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1050 | |
1051 | val = clk_readl(c->reg); | |
1052 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); | |
1053 | clk_writel(val, c->reg); | |
1054 | ||
1055 | if (c->flags & PLLM) { | |
1056 | val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); | |
1057 | val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | |
1058 | pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); | |
1059 | } | |
1060 | } | |
1061 | ||
92fe58f0 PG |
1062 | static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
1063 | unsigned long parent_rate) | |
d9cc6f76 | 1064 | { |
92fe58f0 | 1065 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1066 | u32 val, p_div, old_base; |
1067 | unsigned long input_rate; | |
1068 | const struct clk_pll_freq_table *sel; | |
1069 | struct clk_pll_freq_table cfg; | |
1070 | ||
d9cc6f76 PDS |
1071 | if (c->flags & PLL_FIXED) { |
1072 | int ret = 0; | |
1073 | if (rate != c->u.pll.fixed_rate) { | |
1074 | pr_err("%s: Can not change %s fixed rate %lu to %lu\n", | |
92fe58f0 PG |
1075 | __func__, __clk_get_name(hw->clk), |
1076 | c->u.pll.fixed_rate, rate); | |
d9cc6f76 PDS |
1077 | ret = -EINVAL; |
1078 | } | |
1079 | return ret; | |
1080 | } | |
1081 | ||
1082 | if (c->flags & PLLM) { | |
92fe58f0 | 1083 | if (rate != __clk_get_rate(hw->clk)) { |
d9cc6f76 | 1084 | pr_err("%s: Can not change memory %s rate in flight\n", |
92fe58f0 | 1085 | __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1086 | return -EINVAL; |
1087 | } | |
d9cc6f76 PDS |
1088 | } |
1089 | ||
1090 | p_div = 0; | |
92fe58f0 | 1091 | input_rate = parent_rate; |
d9cc6f76 PDS |
1092 | |
1093 | /* Check if the target rate is tabulated */ | |
1094 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1095 | if (sel->input_rate == input_rate && sel->output_rate == rate) { | |
1096 | if (c->flags & PLLU) { | |
1097 | BUG_ON(sel->p < 1 || sel->p > 2); | |
1098 | if (sel->p == 1) | |
1099 | p_div = PLLU_BASE_POST_DIV; | |
1100 | } else { | |
1101 | BUG_ON(sel->p < 1); | |
1102 | for (val = sel->p; val > 1; val >>= 1) | |
1103 | p_div++; | |
1104 | p_div <<= PLL_BASE_DIVP_SHIFT; | |
1105 | } | |
1106 | break; | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | /* Configure out-of-table rate */ | |
1111 | if (sel->input_rate == 0) { | |
1112 | unsigned long cfreq; | |
1113 | BUG_ON(c->flags & PLLU); | |
1114 | sel = &cfg; | |
1115 | ||
1116 | switch (input_rate) { | |
1117 | case 12000000: | |
1118 | case 26000000: | |
1119 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; | |
1120 | break; | |
1121 | case 13000000: | |
1122 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; | |
1123 | break; | |
1124 | case 16800000: | |
1125 | case 19200000: | |
1126 | cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; | |
1127 | break; | |
1128 | default: | |
1129 | pr_err("%s: Unexpected reference rate %lu\n", | |
1130 | __func__, input_rate); | |
1131 | BUG(); | |
1132 | } | |
1133 | ||
1134 | /* Raise VCO to guarantee 0.5% accuracy */ | |
1135 | for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; | |
1136 | cfg.output_rate <<= 1) | |
1137 | p_div++; | |
1138 | ||
1139 | cfg.p = 0x1 << p_div; | |
1140 | cfg.m = input_rate / cfreq; | |
1141 | cfg.n = cfg.output_rate / cfreq; | |
1142 | cfg.cpcon = OUT_OF_TABLE_CPCON; | |
1143 | ||
1144 | if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) || | |
1145 | (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || | |
1146 | (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || | |
1147 | (cfg.output_rate > c->u.pll.vco_max)) { | |
1148 | pr_err("%s: Failed to set %s out-of-table rate %lu\n", | |
92fe58f0 | 1149 | __func__, __clk_get_name(hw->clk), rate); |
d9cc6f76 PDS |
1150 | return -EINVAL; |
1151 | } | |
1152 | p_div <<= PLL_BASE_DIVP_SHIFT; | |
1153 | } | |
1154 | ||
1155 | c->mul = sel->n; | |
1156 | c->div = sel->m * sel->p; | |
1157 | ||
1158 | old_base = val = clk_readl(c->reg + PLL_BASE); | |
1159 | val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | | |
1160 | ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); | |
1161 | val |= (sel->m << PLL_BASE_DIVM_SHIFT) | | |
1162 | (sel->n << PLL_BASE_DIVN_SHIFT) | p_div; | |
1163 | if (val == old_base) | |
1164 | return 0; | |
1165 | ||
1166 | if (c->state == ON) { | |
92fe58f0 | 1167 | tegra30_pll_clk_disable(hw); |
d9cc6f76 PDS |
1168 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); |
1169 | } | |
1170 | clk_writel(val, c->reg + PLL_BASE); | |
1171 | ||
1172 | if (c->flags & PLL_HAS_CPCON) { | |
1173 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1174 | val &= ~PLL_MISC_CPCON_MASK; | |
1175 | val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; | |
1176 | if (c->flags & (PLLU | PLLD)) { | |
1177 | val &= ~PLL_MISC_LFCON_MASK; | |
1178 | if (sel->n >= PLLDU_LFCON_SET_DIVN) | |
1179 | val |= 0x1 << PLL_MISC_LFCON_SHIFT; | |
1180 | } else if (c->flags & (PLLX | PLLM)) { | |
1181 | val &= ~(0x1 << PLL_MISC_DCCON_SHIFT); | |
1182 | if (rate >= (c->u.pll.vco_max >> 1)) | |
1183 | val |= 0x1 << PLL_MISC_DCCON_SHIFT; | |
1184 | } | |
1185 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1186 | } | |
1187 | ||
1188 | if (c->state == ON) | |
92fe58f0 | 1189 | tegra30_pll_clk_enable(hw); |
d9cc6f76 | 1190 | |
92fe58f0 | 1191 | c->u.pll.fixed_rate = rate; |
d9cc6f76 | 1192 | |
d9cc6f76 PDS |
1193 | return 0; |
1194 | } | |
1195 | ||
92fe58f0 PG |
1196 | static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
1197 | unsigned long *prate) | |
d9cc6f76 | 1198 | { |
92fe58f0 PG |
1199 | struct clk_tegra *c = to_clk_tegra(hw); |
1200 | unsigned long input_rate = *prate; | |
78662130 | 1201 | u64 output_rate = *prate; |
92fe58f0 PG |
1202 | const struct clk_pll_freq_table *sel; |
1203 | struct clk_pll_freq_table cfg; | |
1204 | int mul; | |
1205 | int div; | |
1206 | u32 p_div; | |
d9cc6f76 PDS |
1207 | u32 val; |
1208 | ||
92fe58f0 PG |
1209 | if (c->flags & PLL_FIXED) |
1210 | return c->u.pll.fixed_rate; | |
d9cc6f76 | 1211 | |
92fe58f0 PG |
1212 | if (c->flags & PLLM) |
1213 | return __clk_get_rate(hw->clk); | |
d9cc6f76 | 1214 | |
92fe58f0 PG |
1215 | p_div = 0; |
1216 | /* Check if the target rate is tabulated */ | |
1217 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1218 | if (sel->input_rate == input_rate && sel->output_rate == rate) { | |
1219 | if (c->flags & PLLU) { | |
1220 | BUG_ON(sel->p < 1 || sel->p > 2); | |
1221 | if (sel->p == 1) | |
1222 | p_div = PLLU_BASE_POST_DIV; | |
1223 | } else { | |
1224 | BUG_ON(sel->p < 1); | |
1225 | for (val = sel->p; val > 1; val >>= 1) | |
1226 | p_div++; | |
1227 | p_div <<= PLL_BASE_DIVP_SHIFT; | |
1228 | } | |
1229 | break; | |
1230 | } | |
1231 | } | |
d9cc6f76 | 1232 | |
92fe58f0 PG |
1233 | if (sel->input_rate == 0) { |
1234 | unsigned long cfreq; | |
1235 | BUG_ON(c->flags & PLLU); | |
1236 | sel = &cfg; | |
1237 | ||
1238 | switch (input_rate) { | |
1239 | case 12000000: | |
1240 | case 26000000: | |
1241 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; | |
1242 | break; | |
1243 | case 13000000: | |
1244 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; | |
1245 | break; | |
1246 | case 16800000: | |
1247 | case 19200000: | |
1248 | cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; | |
1249 | break; | |
1250 | default: | |
1251 | pr_err("%s: Unexpected reference rate %lu\n", | |
1252 | __func__, input_rate); | |
1253 | BUG(); | |
1254 | } | |
1255 | ||
1256 | /* Raise VCO to guarantee 0.5% accuracy */ | |
1257 | for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; | |
1258 | cfg.output_rate <<= 1) | |
1259 | p_div++; | |
1260 | ||
1261 | cfg.p = 0x1 << p_div; | |
1262 | cfg.m = input_rate / cfreq; | |
1263 | cfg.n = cfg.output_rate / cfreq; | |
1264 | } | |
1265 | ||
1266 | mul = sel->n; | |
1267 | div = sel->m * sel->p; | |
1268 | ||
1269 | output_rate *= mul; | |
1270 | output_rate += div - 1; /* round up */ | |
1271 | do_div(output_rate, div); | |
1272 | ||
1273 | return output_rate; | |
1274 | } | |
1275 | ||
1276 | static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw, | |
1277 | unsigned long parent_rate) | |
1278 | { | |
1279 | struct clk_tegra *c = to_clk_tegra(hw); | |
1280 | u64 rate = parent_rate; | |
1281 | u32 val = clk_readl(c->reg + PLL_BASE); | |
1282 | ||
1283 | if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { | |
1284 | const struct clk_pll_freq_table *sel; | |
1285 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1286 | if (sel->input_rate == parent_rate && | |
1287 | sel->output_rate == c->u.pll.fixed_rate) { | |
1288 | c->mul = sel->n; | |
1289 | c->div = sel->m * sel->p; | |
1290 | break; | |
1291 | } | |
1292 | } | |
1293 | pr_err("Clock %s has unknown fixed frequency\n", | |
1294 | __clk_get_name(hw->clk)); | |
1295 | BUG(); | |
1296 | } else if (val & PLL_BASE_BYPASS) { | |
1297 | c->mul = 1; | |
1298 | c->div = 1; | |
1299 | } else { | |
1300 | c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; | |
1301 | c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; | |
1302 | if (c->flags & PLLU) | |
1303 | c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; | |
1304 | else | |
1305 | c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >> | |
1306 | PLL_BASE_DIVP_SHIFT)); | |
1307 | } | |
1308 | ||
1309 | if (c->mul != 0 && c->div != 0) { | |
1310 | rate *= c->mul; | |
1311 | rate += c->div - 1; /* round up */ | |
1312 | do_div(rate, c->div); | |
1313 | } | |
1314 | ||
1315 | return rate; | |
1316 | } | |
1317 | ||
1318 | struct clk_ops tegra30_pll_ops = { | |
1319 | .is_enabled = tegra30_pll_clk_is_enabled, | |
1320 | .init = tegra30_pll_clk_init, | |
1321 | .enable = tegra30_pll_clk_enable, | |
1322 | .disable = tegra30_pll_clk_disable, | |
1323 | .recalc_rate = tegra30_pll_recalc_rate, | |
1324 | .round_rate = tegra30_pll_round_rate, | |
1325 | .set_rate = tegra30_pll_clk_set_rate, | |
1326 | }; | |
1327 | ||
1328 | int tegra30_plld_clk_cfg_ex(struct clk_hw *hw, | |
1329 | enum tegra_clk_ex_param p, u32 setting) | |
1330 | { | |
1331 | struct clk_tegra *c = to_clk_tegra(hw); | |
1332 | u32 val, mask, reg; | |
1333 | ||
1334 | switch (p) { | |
1335 | case TEGRA_CLK_PLLD_CSI_OUT_ENB: | |
1336 | mask = PLLD_BASE_CSI_CLKENABLE; | |
1337 | reg = c->reg + PLL_BASE; | |
1338 | break; | |
1339 | case TEGRA_CLK_PLLD_DSI_OUT_ENB: | |
1340 | mask = PLLD_MISC_DSI_CLKENABLE; | |
1341 | reg = c->reg + PLL_MISC(c); | |
1342 | break; | |
1343 | case TEGRA_CLK_PLLD_MIPI_MUX_SEL: | |
1344 | if (!(c->flags & PLL_ALT_MISC_REG)) { | |
1345 | mask = PLLD_BASE_DSIB_MUX_MASK; | |
1346 | reg = c->reg + PLL_BASE; | |
1347 | break; | |
1348 | } | |
1349 | /* fall through - error since PLLD2 does not have MUX_SEL control */ | |
1350 | default: | |
1351 | return -EINVAL; | |
1352 | } | |
1353 | ||
1354 | val = clk_readl(reg); | |
1355 | if (setting) | |
1356 | val |= mask; | |
1357 | else | |
1358 | val &= ~mask; | |
1359 | clk_writel(val, reg); | |
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static int tegra30_plle_clk_is_enabled(struct clk_hw *hw) | |
1364 | { | |
1365 | struct clk_tegra *c = to_clk_tegra(hw); | |
1366 | u32 val; | |
1367 | ||
1368 | val = clk_readl(c->reg + PLL_BASE); | |
1369 | c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; | |
1370 | return c->state; | |
1371 | } | |
1372 | ||
1373 | static void tegra30_plle_clk_disable(struct clk_hw *hw) | |
1374 | { | |
1375 | struct clk_tegra *c = to_clk_tegra(hw); | |
1376 | u32 val; | |
1377 | ||
1378 | val = clk_readl(c->reg + PLL_BASE); | |
1379 | val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); | |
1380 | clk_writel(val, c->reg + PLL_BASE); | |
1381 | } | |
d9cc6f76 | 1382 | |
92fe58f0 | 1383 | static void tegra30_plle_training(struct clk_tegra *c) |
d9cc6f76 PDS |
1384 | { |
1385 | u32 val; | |
1386 | ||
1387 | /* PLLE is already disabled, and setup cleared; | |
1388 | * create falling edge on PLLE IDDQ input */ | |
1389 | val = pmc_readl(PMC_SATA_PWRGT); | |
1390 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | |
1391 | pmc_writel(val, PMC_SATA_PWRGT); | |
1392 | ||
1393 | val = pmc_readl(PMC_SATA_PWRGT); | |
1394 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; | |
1395 | pmc_writel(val, PMC_SATA_PWRGT); | |
1396 | ||
1397 | val = pmc_readl(PMC_SATA_PWRGT); | |
1398 | val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | |
1399 | pmc_writel(val, PMC_SATA_PWRGT); | |
1400 | ||
1401 | do { | |
1402 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1403 | } while (!(val & PLLE_MISC_READY)); | |
1404 | } | |
1405 | ||
92fe58f0 | 1406 | static int tegra30_plle_configure(struct clk_hw *hw, bool force_training) |
d9cc6f76 | 1407 | { |
92fe58f0 PG |
1408 | struct clk_tegra *c = to_clk_tegra(hw); |
1409 | struct clk *parent = __clk_get_parent(hw->clk); | |
d9cc6f76 | 1410 | const struct clk_pll_freq_table *sel; |
92fe58f0 PG |
1411 | u32 val; |
1412 | ||
d9cc6f76 | 1413 | unsigned long rate = c->u.pll.fixed_rate; |
92fe58f0 | 1414 | unsigned long input_rate = __clk_get_rate(parent); |
d9cc6f76 PDS |
1415 | |
1416 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1417 | if (sel->input_rate == input_rate && sel->output_rate == rate) | |
1418 | break; | |
1419 | } | |
1420 | ||
1421 | if (sel->input_rate == 0) | |
1422 | return -ENOSYS; | |
1423 | ||
1424 | /* disable PLLE, clear setup fiels */ | |
92fe58f0 | 1425 | tegra30_plle_clk_disable(hw); |
d9cc6f76 PDS |
1426 | |
1427 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1428 | val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); | |
1429 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1430 | ||
1431 | /* training */ | |
1432 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1433 | if (force_training || (!(val & PLLE_MISC_READY))) | |
1434 | tegra30_plle_training(c); | |
1435 | ||
1436 | /* configure dividers, setup, disable SS */ | |
1437 | val = clk_readl(c->reg + PLL_BASE); | |
1438 | val &= ~PLLE_BASE_DIV_MASK; | |
1439 | val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon); | |
1440 | clk_writel(val, c->reg + PLL_BASE); | |
1441 | c->mul = sel->n; | |
1442 | c->div = sel->m * sel->p; | |
1443 | ||
1444 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1445 | val |= PLLE_MISC_SETUP_VALUE; | |
1446 | val |= PLLE_MISC_LOCK_ENABLE; | |
1447 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1448 | ||
1449 | val = clk_readl(PLLE_SS_CTRL); | |
1450 | val |= PLLE_SS_DISABLE; | |
1451 | clk_writel(val, PLLE_SS_CTRL); | |
1452 | ||
1453 | /* enable and lock PLLE*/ | |
1454 | val = clk_readl(c->reg + PLL_BASE); | |
1455 | val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); | |
1456 | clk_writel(val, c->reg + PLL_BASE); | |
1457 | ||
1458 | tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK); | |
1459 | ||
1460 | return 0; | |
1461 | } | |
1462 | ||
92fe58f0 | 1463 | static int tegra30_plle_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1464 | { |
92fe58f0 PG |
1465 | struct clk_tegra *c = to_clk_tegra(hw); |
1466 | ||
1467 | return tegra30_plle_configure(hw, !c->set); | |
1468 | } | |
1469 | ||
1470 | static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw, | |
1471 | unsigned long parent_rate) | |
1472 | { | |
1473 | struct clk_tegra *c = to_clk_tegra(hw); | |
1474 | unsigned long rate = parent_rate; | |
1475 | u32 val; | |
1476 | ||
1477 | val = clk_readl(c->reg + PLL_BASE); | |
1478 | c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; | |
1479 | c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT; | |
1480 | c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT; | |
1481 | ||
1482 | if (c->mul != 0 && c->div != 0) { | |
1483 | rate *= c->mul; | |
1484 | rate += c->div - 1; /* round up */ | |
1485 | do_div(rate, c->div); | |
1486 | } | |
1487 | return rate; | |
d9cc6f76 PDS |
1488 | } |
1489 | ||
88e790a4 | 1490 | struct clk_ops tegra30_plle_ops = { |
92fe58f0 PG |
1491 | .is_enabled = tegra30_plle_clk_is_enabled, |
1492 | .enable = tegra30_plle_clk_enable, | |
1493 | .disable = tegra30_plle_clk_disable, | |
1494 | .recalc_rate = tegra30_plle_clk_recalc_rate, | |
d9cc6f76 PDS |
1495 | }; |
1496 | ||
1497 | /* Clock divider ops */ | |
92fe58f0 | 1498 | static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 1499 | { |
92fe58f0 PG |
1500 | struct clk_tegra *c = to_clk_tegra(hw); |
1501 | ||
d9cc6f76 | 1502 | if (c->flags & DIV_U71) { |
d9cc6f76 PDS |
1503 | u32 val = clk_readl(c->reg); |
1504 | val >>= c->reg_shift; | |
1505 | c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; | |
1506 | if (!(val & PLL_OUT_RESET_DISABLE)) | |
1507 | c->state = OFF; | |
d9cc6f76 PDS |
1508 | } else { |
1509 | c->state = ON; | |
d9cc6f76 | 1510 | } |
92fe58f0 | 1511 | return c->state; |
d9cc6f76 PDS |
1512 | } |
1513 | ||
92fe58f0 | 1514 | static int tegra30_pll_div_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1515 | { |
92fe58f0 | 1516 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1517 | u32 val; |
1518 | u32 new_val; | |
1519 | ||
92fe58f0 | 1520 | pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1521 | if (c->flags & DIV_U71) { |
1522 | val = clk_readl(c->reg); | |
1523 | new_val = val >> c->reg_shift; | |
1524 | new_val &= 0xFFFF; | |
1525 | ||
1526 | new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; | |
1527 | ||
1528 | val &= ~(0xFFFF << c->reg_shift); | |
1529 | val |= new_val << c->reg_shift; | |
1530 | clk_writel_delay(val, c->reg); | |
1531 | return 0; | |
1532 | } else if (c->flags & DIV_2) { | |
1533 | return 0; | |
1534 | } | |
1535 | return -EINVAL; | |
1536 | } | |
1537 | ||
92fe58f0 | 1538 | static void tegra30_pll_div_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 1539 | { |
92fe58f0 | 1540 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1541 | u32 val; |
1542 | u32 new_val; | |
1543 | ||
92fe58f0 | 1544 | pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1545 | if (c->flags & DIV_U71) { |
1546 | val = clk_readl(c->reg); | |
1547 | new_val = val >> c->reg_shift; | |
1548 | new_val &= 0xFFFF; | |
1549 | ||
1550 | new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); | |
1551 | ||
1552 | val &= ~(0xFFFF << c->reg_shift); | |
1553 | val |= new_val << c->reg_shift; | |
1554 | clk_writel_delay(val, c->reg); | |
1555 | } | |
1556 | } | |
1557 | ||
92fe58f0 PG |
1558 | static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
1559 | unsigned long parent_rate) | |
d9cc6f76 | 1560 | { |
92fe58f0 | 1561 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1562 | u32 val; |
1563 | u32 new_val; | |
1564 | int divider_u71; | |
d9cc6f76 | 1565 | |
d9cc6f76 PDS |
1566 | if (c->flags & DIV_U71) { |
1567 | divider_u71 = clk_div71_get_divider( | |
1568 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1569 | if (divider_u71 >= 0) { | |
1570 | val = clk_readl(c->reg); | |
1571 | new_val = val >> c->reg_shift; | |
1572 | new_val &= 0xFFFF; | |
1573 | if (c->flags & DIV_U71_FIXED) | |
1574 | new_val |= PLL_OUT_OVERRIDE; | |
1575 | new_val &= ~PLL_OUT_RATIO_MASK; | |
1576 | new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; | |
1577 | ||
1578 | val &= ~(0xFFFF << c->reg_shift); | |
1579 | val |= new_val << c->reg_shift; | |
1580 | clk_writel_delay(val, c->reg); | |
1581 | c->div = divider_u71 + 2; | |
1582 | c->mul = 2; | |
92fe58f0 | 1583 | c->fixed_rate = rate; |
d9cc6f76 PDS |
1584 | return 0; |
1585 | } | |
92fe58f0 PG |
1586 | } else if (c->flags & DIV_2) { |
1587 | c->fixed_rate = rate; | |
1588 | return 0; | |
1589 | } | |
d9cc6f76 PDS |
1590 | |
1591 | return -EINVAL; | |
1592 | } | |
1593 | ||
92fe58f0 PG |
1594 | static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw, |
1595 | unsigned long parent_rate) | |
1596 | { | |
1597 | struct clk_tegra *c = to_clk_tegra(hw); | |
1598 | u64 rate = parent_rate; | |
1599 | ||
1600 | if (c->flags & DIV_U71) { | |
1601 | u32 divu71; | |
1602 | u32 val = clk_readl(c->reg); | |
1603 | val >>= c->reg_shift; | |
1604 | ||
1605 | divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; | |
1606 | c->div = (divu71 + 2); | |
1607 | c->mul = 2; | |
1608 | } else if (c->flags & DIV_2) { | |
1609 | if (c->flags & (PLLD | PLLX)) { | |
1610 | c->div = 2; | |
1611 | c->mul = 1; | |
1612 | } else | |
1613 | BUG(); | |
1614 | } else { | |
1615 | c->div = 1; | |
1616 | c->mul = 1; | |
1617 | } | |
1618 | if (c->mul != 0 && c->div != 0) { | |
1619 | rate *= c->mul; | |
1620 | rate += c->div - 1; /* round up */ | |
1621 | do_div(rate, c->div); | |
1622 | } | |
1623 | ||
1624 | return rate; | |
1625 | } | |
1626 | ||
1627 | static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw, | |
1628 | unsigned long rate, unsigned long *prate) | |
d9cc6f76 | 1629 | { |
92fe58f0 PG |
1630 | struct clk_tegra *c = to_clk_tegra(hw); |
1631 | unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); | |
d9cc6f76 | 1632 | int divider; |
92fe58f0 PG |
1633 | |
1634 | if (prate) | |
1635 | parent_rate = *prate; | |
d9cc6f76 PDS |
1636 | |
1637 | if (c->flags & DIV_U71) { | |
1638 | divider = clk_div71_get_divider( | |
1639 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1640 | if (divider < 0) | |
1641 | return divider; | |
1642 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); | |
92fe58f0 PG |
1643 | } else if (c->flags & DIV_2) { |
1644 | *prate = rate * 2; | |
d9cc6f76 | 1645 | return rate; |
92fe58f0 | 1646 | } |
d9cc6f76 PDS |
1647 | |
1648 | return -EINVAL; | |
1649 | } | |
1650 | ||
88e790a4 | 1651 | struct clk_ops tegra30_pll_div_ops = { |
92fe58f0 PG |
1652 | .is_enabled = tegra30_pll_div_clk_is_enabled, |
1653 | .enable = tegra30_pll_div_clk_enable, | |
1654 | .disable = tegra30_pll_div_clk_disable, | |
1655 | .set_rate = tegra30_pll_div_clk_set_rate, | |
1656 | .recalc_rate = tegra30_pll_div_clk_recalc_rate, | |
1657 | .round_rate = tegra30_pll_div_clk_round_rate, | |
d9cc6f76 PDS |
1658 | }; |
1659 | ||
1660 | /* Periph clk ops */ | |
92fe58f0 | 1661 | static inline u32 periph_clk_source_mask(struct clk_tegra *c) |
d9cc6f76 PDS |
1662 | { |
1663 | if (c->flags & MUX8) | |
1664 | return 7 << 29; | |
1665 | else if (c->flags & MUX_PWM) | |
1666 | return 3 << 28; | |
1667 | else if (c->flags & MUX_CLK_OUT) | |
1668 | return 3 << (c->u.periph.clk_num + 4); | |
1669 | else if (c->flags & PLLD) | |
1670 | return PLLD_BASE_DSIB_MUX_MASK; | |
1671 | else | |
1672 | return 3 << 30; | |
1673 | } | |
1674 | ||
92fe58f0 | 1675 | static inline u32 periph_clk_source_shift(struct clk_tegra *c) |
d9cc6f76 PDS |
1676 | { |
1677 | if (c->flags & MUX8) | |
1678 | return 29; | |
1679 | else if (c->flags & MUX_PWM) | |
1680 | return 28; | |
1681 | else if (c->flags & MUX_CLK_OUT) | |
1682 | return c->u.periph.clk_num + 4; | |
1683 | else if (c->flags & PLLD) | |
1684 | return PLLD_BASE_DSIB_MUX_SHIFT; | |
1685 | else | |
1686 | return 30; | |
1687 | } | |
1688 | ||
92fe58f0 | 1689 | static int tegra30_periph_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 1690 | { |
92fe58f0 | 1691 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1692 | |
1693 | c->state = ON; | |
1694 | if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) | |
1695 | c->state = OFF; | |
1696 | if (!(c->flags & PERIPH_NO_RESET)) | |
1697 | if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) | |
1698 | c->state = OFF; | |
92fe58f0 | 1699 | return c->state; |
d9cc6f76 PDS |
1700 | } |
1701 | ||
92fe58f0 | 1702 | static int tegra30_periph_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1703 | { |
92fe58f0 | 1704 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1705 | |
1706 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; | |
1707 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) | |
1708 | return 0; | |
1709 | ||
1710 | clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c)); | |
1711 | if (!(c->flags & PERIPH_NO_RESET) && | |
1712 | !(c->flags & PERIPH_MANUAL_RESET)) { | |
1713 | if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & | |
1714 | PERIPH_CLK_TO_BIT(c)) { | |
1715 | udelay(5); /* reset propagation delay */ | |
1716 | clk_writel(PERIPH_CLK_TO_BIT(c), | |
1717 | PERIPH_CLK_TO_RST_CLR_REG(c)); | |
1718 | } | |
1719 | } | |
1720 | return 0; | |
1721 | } | |
1722 | ||
92fe58f0 | 1723 | static void tegra30_periph_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 1724 | { |
92fe58f0 | 1725 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1726 | unsigned long val; |
d9cc6f76 | 1727 | |
92fe58f0 | 1728 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; |
d9cc6f76 | 1729 | |
92fe58f0 PG |
1730 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0) |
1731 | return; | |
d9cc6f76 | 1732 | |
92fe58f0 PG |
1733 | /* If peripheral is in the APB bus then read the APB bus to |
1734 | * flush the write operation in apb bus. This will avoid the | |
1735 | * peripheral access after disabling clock*/ | |
1736 | if (c->flags & PERIPH_ON_APB) | |
1737 | val = chipid_readl(); | |
1738 | ||
1739 | clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); | |
d9cc6f76 PDS |
1740 | } |
1741 | ||
92fe58f0 | 1742 | void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert) |
d9cc6f76 | 1743 | { |
92fe58f0 | 1744 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1745 | unsigned long val; |
d9cc6f76 PDS |
1746 | |
1747 | if (!(c->flags & PERIPH_NO_RESET)) { | |
1748 | if (assert) { | |
1749 | /* If peripheral is in the APB bus then read the APB | |
1750 | * bus to flush the write operation in apb bus. This | |
1751 | * will avoid the peripheral access after disabling | |
1752 | * clock */ | |
1753 | if (c->flags & PERIPH_ON_APB) | |
1754 | val = chipid_readl(); | |
1755 | ||
1756 | clk_writel(PERIPH_CLK_TO_BIT(c), | |
1757 | PERIPH_CLK_TO_RST_SET_REG(c)); | |
1758 | } else | |
1759 | clk_writel(PERIPH_CLK_TO_BIT(c), | |
1760 | PERIPH_CLK_TO_RST_CLR_REG(c)); | |
1761 | } | |
1762 | } | |
1763 | ||
92fe58f0 | 1764 | static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 1765 | { |
92fe58f0 | 1766 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1767 | u32 val; |
d9cc6f76 PDS |
1768 | |
1769 | if (!(c->flags & MUX)) | |
92fe58f0 | 1770 | return (index == 0) ? 0 : (-EINVAL); |
d9cc6f76 | 1771 | |
92fe58f0 PG |
1772 | val = clk_readl(c->reg); |
1773 | val &= ~periph_clk_source_mask(c); | |
1774 | val |= (index << periph_clk_source_shift(c)); | |
1775 | clk_writel_delay(val, c->reg); | |
1776 | return 0; | |
1777 | } | |
d9cc6f76 | 1778 | |
92fe58f0 PG |
1779 | static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw) |
1780 | { | |
1781 | struct clk_tegra *c = to_clk_tegra(hw); | |
1782 | u32 val = clk_readl(c->reg); | |
1783 | int source = (val & periph_clk_source_mask(c)) >> | |
1784 | periph_clk_source_shift(c); | |
d9cc6f76 | 1785 | |
92fe58f0 PG |
1786 | if (!(c->flags & MUX)) |
1787 | return 0; | |
d9cc6f76 | 1788 | |
92fe58f0 | 1789 | return source; |
d9cc6f76 PDS |
1790 | } |
1791 | ||
92fe58f0 PG |
1792 | static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
1793 | unsigned long parent_rate) | |
d9cc6f76 | 1794 | { |
92fe58f0 | 1795 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1796 | u32 val; |
1797 | int divider; | |
d9cc6f76 PDS |
1798 | |
1799 | if (c->flags & DIV_U71) { | |
1800 | divider = clk_div71_get_divider( | |
1801 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1802 | if (divider >= 0) { | |
1803 | val = clk_readl(c->reg); | |
1804 | val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; | |
1805 | val |= divider; | |
1806 | if (c->flags & DIV_U71_UART) { | |
1807 | if (divider) | |
1808 | val |= PERIPH_CLK_UART_DIV_ENB; | |
1809 | else | |
1810 | val &= ~PERIPH_CLK_UART_DIV_ENB; | |
1811 | } | |
1812 | clk_writel_delay(val, c->reg); | |
1813 | c->div = divider + 2; | |
1814 | c->mul = 2; | |
1815 | return 0; | |
1816 | } | |
1817 | } else if (c->flags & DIV_U16) { | |
1818 | divider = clk_div16_get_divider(parent_rate, rate); | |
1819 | if (divider >= 0) { | |
1820 | val = clk_readl(c->reg); | |
1821 | val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; | |
1822 | val |= divider; | |
1823 | clk_writel_delay(val, c->reg); | |
1824 | c->div = divider + 1; | |
1825 | c->mul = 1; | |
1826 | return 0; | |
1827 | } | |
1828 | } else if (parent_rate <= rate) { | |
1829 | c->div = 1; | |
1830 | c->mul = 1; | |
1831 | return 0; | |
1832 | } | |
1833 | return -EINVAL; | |
1834 | } | |
1835 | ||
92fe58f0 PG |
1836 | static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
1837 | unsigned long *prate) | |
d9cc6f76 | 1838 | { |
92fe58f0 PG |
1839 | struct clk_tegra *c = to_clk_tegra(hw); |
1840 | unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); | |
d9cc6f76 | 1841 | int divider; |
92fe58f0 PG |
1842 | |
1843 | if (prate) | |
1844 | parent_rate = *prate; | |
d9cc6f76 PDS |
1845 | |
1846 | if (c->flags & DIV_U71) { | |
1847 | divider = clk_div71_get_divider( | |
1848 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1849 | if (divider < 0) | |
1850 | return divider; | |
1851 | ||
1852 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); | |
1853 | } else if (c->flags & DIV_U16) { | |
1854 | divider = clk_div16_get_divider(parent_rate, rate); | |
1855 | if (divider < 0) | |
1856 | return divider; | |
1857 | return DIV_ROUND_UP(parent_rate, divider + 1); | |
1858 | } | |
1859 | return -EINVAL; | |
1860 | } | |
1861 | ||
92fe58f0 PG |
1862 | static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw, |
1863 | unsigned long parent_rate) | |
1864 | { | |
1865 | struct clk_tegra *c = to_clk_tegra(hw); | |
1866 | u64 rate = parent_rate; | |
1867 | u32 val = clk_readl(c->reg); | |
1868 | ||
1869 | if (c->flags & DIV_U71) { | |
1870 | u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; | |
1871 | if ((c->flags & DIV_U71_UART) && | |
1872 | (!(val & PERIPH_CLK_UART_DIV_ENB))) { | |
1873 | divu71 = 0; | |
1874 | } | |
1875 | if (c->flags & DIV_U71_IDLE) { | |
1876 | val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK << | |
1877 | PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); | |
1878 | val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL << | |
1879 | PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); | |
1880 | clk_writel(val, c->reg); | |
1881 | } | |
1882 | c->div = divu71 + 2; | |
1883 | c->mul = 2; | |
1884 | } else if (c->flags & DIV_U16) { | |
1885 | u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; | |
1886 | c->div = divu16 + 1; | |
1887 | c->mul = 1; | |
1888 | } else { | |
1889 | c->div = 1; | |
1890 | c->mul = 1; | |
1891 | } | |
1892 | ||
1893 | if (c->mul != 0 && c->div != 0) { | |
1894 | rate *= c->mul; | |
1895 | rate += c->div - 1; /* round up */ | |
1896 | do_div(rate, c->div); | |
1897 | } | |
1898 | return rate; | |
1899 | } | |
1900 | ||
88e790a4 | 1901 | struct clk_ops tegra30_periph_clk_ops = { |
92fe58f0 PG |
1902 | .is_enabled = tegra30_periph_clk_is_enabled, |
1903 | .enable = tegra30_periph_clk_enable, | |
1904 | .disable = tegra30_periph_clk_disable, | |
1905 | .set_parent = tegra30_periph_clk_set_parent, | |
1906 | .get_parent = tegra30_periph_clk_get_parent, | |
1907 | .set_rate = tegra30_periph_clk_set_rate, | |
1908 | .round_rate = tegra30_periph_clk_round_rate, | |
1909 | .recalc_rate = tegra30_periph_clk_recalc_rate, | |
1910 | }; | |
1911 | ||
1912 | static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) | |
1913 | { | |
1914 | struct clk *d = clk_get_sys(NULL, "pll_d"); | |
1915 | /* The DSIB parent selection bit is in PLLD base | |
1916 | register - can not do direct r-m-w, must be | |
1917 | protected by PLLD lock */ | |
1918 | tegra_clk_cfg_ex( | |
1919 | d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); | |
1920 | ||
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | struct clk_ops tegra30_dsib_clk_ops = { | |
1925 | .is_enabled = tegra30_periph_clk_is_enabled, | |
d9cc6f76 PDS |
1926 | .enable = &tegra30_periph_clk_enable, |
1927 | .disable = &tegra30_periph_clk_disable, | |
92fe58f0 PG |
1928 | .set_parent = &tegra30_dsib_clk_set_parent, |
1929 | .get_parent = &tegra30_periph_clk_get_parent, | |
d9cc6f76 PDS |
1930 | .set_rate = &tegra30_periph_clk_set_rate, |
1931 | .round_rate = &tegra30_periph_clk_round_rate, | |
92fe58f0 | 1932 | .recalc_rate = &tegra30_periph_clk_recalc_rate, |
d9cc6f76 PDS |
1933 | }; |
1934 | ||
d9cc6f76 | 1935 | /* Periph extended clock configuration ops */ |
92fe58f0 PG |
1936 | int tegra30_vi_clk_cfg_ex(struct clk_hw *hw, |
1937 | enum tegra_clk_ex_param p, u32 setting) | |
d9cc6f76 | 1938 | { |
92fe58f0 PG |
1939 | struct clk_tegra *c = to_clk_tegra(hw); |
1940 | ||
d9cc6f76 PDS |
1941 | if (p == TEGRA_CLK_VI_INP_SEL) { |
1942 | u32 val = clk_readl(c->reg); | |
1943 | val &= ~PERIPH_CLK_VI_SEL_EX_MASK; | |
1944 | val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & | |
1945 | PERIPH_CLK_VI_SEL_EX_MASK; | |
1946 | clk_writel(val, c->reg); | |
1947 | return 0; | |
1948 | } | |
1949 | return -EINVAL; | |
1950 | } | |
1951 | ||
92fe58f0 PG |
1952 | int tegra30_nand_clk_cfg_ex(struct clk_hw *hw, |
1953 | enum tegra_clk_ex_param p, u32 setting) | |
d9cc6f76 | 1954 | { |
92fe58f0 PG |
1955 | struct clk_tegra *c = to_clk_tegra(hw); |
1956 | ||
d9cc6f76 PDS |
1957 | if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { |
1958 | u32 val = clk_readl(c->reg); | |
1959 | if (setting) | |
1960 | val |= PERIPH_CLK_NAND_DIV_EX_ENB; | |
1961 | else | |
1962 | val &= ~PERIPH_CLK_NAND_DIV_EX_ENB; | |
1963 | clk_writel(val, c->reg); | |
1964 | return 0; | |
1965 | } | |
1966 | return -EINVAL; | |
1967 | } | |
1968 | ||
92fe58f0 PG |
1969 | int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw, |
1970 | enum tegra_clk_ex_param p, u32 setting) | |
d9cc6f76 | 1971 | { |
92fe58f0 PG |
1972 | struct clk_tegra *c = to_clk_tegra(hw); |
1973 | ||
d9cc6f76 PDS |
1974 | if (p == TEGRA_CLK_DTV_INVERT) { |
1975 | u32 val = clk_readl(c->reg); | |
1976 | if (setting) | |
1977 | val |= PERIPH_CLK_DTV_POLARITY_INV; | |
1978 | else | |
1979 | val &= ~PERIPH_CLK_DTV_POLARITY_INV; | |
1980 | clk_writel(val, c->reg); | |
1981 | return 0; | |
1982 | } | |
1983 | return -EINVAL; | |
1984 | } | |
1985 | ||
d9cc6f76 PDS |
1986 | /* Output clock ops */ |
1987 | ||
1988 | static DEFINE_SPINLOCK(clk_out_lock); | |
1989 | ||
92fe58f0 | 1990 | static int tegra30_clk_out_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 1991 | { |
92fe58f0 | 1992 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1993 | u32 val = pmc_readl(c->reg); |
1994 | ||
1995 | c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; | |
1996 | c->mul = 1; | |
1997 | c->div = 1; | |
92fe58f0 | 1998 | return c->state; |
d9cc6f76 PDS |
1999 | } |
2000 | ||
92fe58f0 | 2001 | static int tegra30_clk_out_enable(struct clk_hw *hw) |
d9cc6f76 | 2002 | { |
92fe58f0 | 2003 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2004 | u32 val; |
2005 | unsigned long flags; | |
2006 | ||
d9cc6f76 PDS |
2007 | spin_lock_irqsave(&clk_out_lock, flags); |
2008 | val = pmc_readl(c->reg); | |
2009 | val |= (0x1 << c->u.periph.clk_num); | |
2010 | pmc_writel(val, c->reg); | |
2011 | spin_unlock_irqrestore(&clk_out_lock, flags); | |
2012 | ||
2013 | return 0; | |
2014 | } | |
2015 | ||
92fe58f0 | 2016 | static void tegra30_clk_out_disable(struct clk_hw *hw) |
d9cc6f76 | 2017 | { |
92fe58f0 | 2018 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2019 | u32 val; |
2020 | unsigned long flags; | |
2021 | ||
d9cc6f76 PDS |
2022 | spin_lock_irqsave(&clk_out_lock, flags); |
2023 | val = pmc_readl(c->reg); | |
2024 | val &= ~(0x1 << c->u.periph.clk_num); | |
2025 | pmc_writel(val, c->reg); | |
2026 | spin_unlock_irqrestore(&clk_out_lock, flags); | |
2027 | } | |
2028 | ||
92fe58f0 | 2029 | static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 2030 | { |
92fe58f0 | 2031 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2032 | u32 val; |
2033 | unsigned long flags; | |
d9cc6f76 | 2034 | |
92fe58f0 PG |
2035 | spin_lock_irqsave(&clk_out_lock, flags); |
2036 | val = pmc_readl(c->reg); | |
2037 | val &= ~periph_clk_source_mask(c); | |
2038 | val |= (index << periph_clk_source_shift(c)); | |
2039 | pmc_writel(val, c->reg); | |
2040 | spin_unlock_irqrestore(&clk_out_lock, flags); | |
d9cc6f76 | 2041 | |
92fe58f0 PG |
2042 | return 0; |
2043 | } | |
d9cc6f76 | 2044 | |
92fe58f0 PG |
2045 | static u8 tegra30_clk_out_get_parent(struct clk_hw *hw) |
2046 | { | |
2047 | struct clk_tegra *c = to_clk_tegra(hw); | |
2048 | u32 val = pmc_readl(c->reg); | |
2049 | int source; | |
d9cc6f76 | 2050 | |
92fe58f0 PG |
2051 | source = (val & periph_clk_source_mask(c)) >> |
2052 | periph_clk_source_shift(c); | |
2053 | return source; | |
d9cc6f76 PDS |
2054 | } |
2055 | ||
88e790a4 | 2056 | struct clk_ops tegra_clk_out_ops = { |
92fe58f0 PG |
2057 | .is_enabled = tegra30_clk_out_is_enabled, |
2058 | .enable = tegra30_clk_out_enable, | |
2059 | .disable = tegra30_clk_out_disable, | |
2060 | .set_parent = tegra30_clk_out_set_parent, | |
2061 | .get_parent = tegra30_clk_out_get_parent, | |
2062 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
d9cc6f76 PDS |
2063 | }; |
2064 | ||
d9cc6f76 | 2065 | /* Clock doubler ops */ |
92fe58f0 | 2066 | static int tegra30_clk_double_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 2067 | { |
92fe58f0 PG |
2068 | struct clk_tegra *c = to_clk_tegra(hw); |
2069 | ||
d9cc6f76 PDS |
2070 | c->state = ON; |
2071 | if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) | |
2072 | c->state = OFF; | |
92fe58f0 | 2073 | return c->state; |
d9cc6f76 PDS |
2074 | }; |
2075 | ||
92fe58f0 PG |
2076 | static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate, |
2077 | unsigned long parent_rate) | |
d9cc6f76 | 2078 | { |
92fe58f0 | 2079 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 2080 | u32 val; |
92fe58f0 | 2081 | |
d9cc6f76 PDS |
2082 | if (rate == parent_rate) { |
2083 | val = clk_readl(c->reg) | (0x1 << c->reg_shift); | |
2084 | clk_writel(val, c->reg); | |
2085 | c->mul = 1; | |
2086 | c->div = 1; | |
2087 | return 0; | |
2088 | } else if (rate == 2 * parent_rate) { | |
2089 | val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); | |
2090 | clk_writel(val, c->reg); | |
2091 | c->mul = 2; | |
2092 | c->div = 1; | |
2093 | return 0; | |
2094 | } | |
2095 | return -EINVAL; | |
2096 | } | |
2097 | ||
92fe58f0 PG |
2098 | static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw, |
2099 | unsigned long parent_rate) | |
2100 | { | |
2101 | struct clk_tegra *c = to_clk_tegra(hw); | |
2102 | u64 rate = parent_rate; | |
d9cc6f76 | 2103 | |
92fe58f0 PG |
2104 | u32 val = clk_readl(c->reg); |
2105 | c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; | |
2106 | c->div = 1; | |
2107 | ||
2108 | if (c->mul != 0 && c->div != 0) { | |
2109 | rate *= c->mul; | |
2110 | rate += c->div - 1; /* round up */ | |
2111 | do_div(rate, c->div); | |
2112 | } | |
2113 | ||
2114 | return rate; | |
2115 | } | |
2116 | ||
2117 | static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate, | |
2118 | unsigned long *prate) | |
d9cc6f76 | 2119 | { |
92fe58f0 PG |
2120 | unsigned long output_rate = *prate; |
2121 | ||
2122 | do_div(output_rate, 2); | |
2123 | return output_rate; | |
d9cc6f76 PDS |
2124 | } |
2125 | ||
92fe58f0 PG |
2126 | struct clk_ops tegra30_clk_double_ops = { |
2127 | .is_enabled = tegra30_clk_double_is_enabled, | |
2128 | .enable = tegra30_periph_clk_enable, | |
2129 | .disable = tegra30_periph_clk_disable, | |
2130 | .recalc_rate = tegra30_clk_double_recalc_rate, | |
2131 | .round_rate = tegra30_clk_double_round_rate, | |
2132 | .set_rate = tegra30_clk_double_set_rate, | |
2133 | }; | |
2134 | ||
2135 | /* Audio sync clock ops */ | |
88e790a4 | 2136 | struct clk_ops tegra_sync_source_ops = { |
92fe58f0 | 2137 | .recalc_rate = tegra30_clk_fixed_recalc_rate, |
d9cc6f76 PDS |
2138 | }; |
2139 | ||
92fe58f0 | 2140 | static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 2141 | { |
92fe58f0 | 2142 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2143 | u32 val = clk_readl(c->reg); |
2144 | c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; | |
92fe58f0 | 2145 | return c->state; |
d9cc6f76 PDS |
2146 | } |
2147 | ||
92fe58f0 | 2148 | static int tegra30_audio_sync_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 2149 | { |
92fe58f0 | 2150 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2151 | u32 val = clk_readl(c->reg); |
2152 | clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); | |
2153 | return 0; | |
2154 | } | |
2155 | ||
92fe58f0 | 2156 | static void tegra30_audio_sync_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 2157 | { |
92fe58f0 | 2158 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2159 | u32 val = clk_readl(c->reg); |
2160 | clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); | |
2161 | } | |
2162 | ||
92fe58f0 | 2163 | static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 2164 | { |
92fe58f0 | 2165 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 2166 | u32 val; |
d9cc6f76 | 2167 | |
92fe58f0 PG |
2168 | val = clk_readl(c->reg); |
2169 | val &= ~AUDIO_SYNC_SOURCE_MASK; | |
2170 | val |= index; | |
d9cc6f76 | 2171 | |
92fe58f0 PG |
2172 | clk_writel(val, c->reg); |
2173 | return 0; | |
2174 | } | |
d9cc6f76 | 2175 | |
92fe58f0 PG |
2176 | static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw) |
2177 | { | |
2178 | struct clk_tegra *c = to_clk_tegra(hw); | |
2179 | u32 val = clk_readl(c->reg); | |
2180 | int source; | |
d9cc6f76 | 2181 | |
92fe58f0 PG |
2182 | source = val & AUDIO_SYNC_SOURCE_MASK; |
2183 | return source; | |
d9cc6f76 PDS |
2184 | } |
2185 | ||
88e790a4 | 2186 | struct clk_ops tegra30_audio_sync_clk_ops = { |
92fe58f0 PG |
2187 | .is_enabled = tegra30_audio_sync_clk_is_enabled, |
2188 | .enable = tegra30_audio_sync_clk_enable, | |
2189 | .disable = tegra30_audio_sync_clk_disable, | |
d9cc6f76 | 2190 | .set_parent = tegra30_audio_sync_clk_set_parent, |
92fe58f0 PG |
2191 | .get_parent = tegra30_audio_sync_clk_get_parent, |
2192 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
d9cc6f76 PDS |
2193 | }; |
2194 | ||
2195 | /* cml0 (pcie), and cml1 (sata) clock ops */ | |
92fe58f0 | 2196 | static int tegra30_cml_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 2197 | { |
92fe58f0 | 2198 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2199 | u32 val = clk_readl(c->reg); |
2200 | c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; | |
92fe58f0 | 2201 | return c->state; |
d9cc6f76 PDS |
2202 | } |
2203 | ||
92fe58f0 | 2204 | static int tegra30_cml_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 2205 | { |
92fe58f0 PG |
2206 | struct clk_tegra *c = to_clk_tegra(hw); |
2207 | ||
d9cc6f76 PDS |
2208 | u32 val = clk_readl(c->reg); |
2209 | val |= (0x1 << c->u.periph.clk_num); | |
2210 | clk_writel(val, c->reg); | |
92fe58f0 | 2211 | |
d9cc6f76 PDS |
2212 | return 0; |
2213 | } | |
2214 | ||
92fe58f0 | 2215 | static void tegra30_cml_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 2216 | { |
92fe58f0 PG |
2217 | struct clk_tegra *c = to_clk_tegra(hw); |
2218 | ||
d9cc6f76 PDS |
2219 | u32 val = clk_readl(c->reg); |
2220 | val &= ~(0x1 << c->u.periph.clk_num); | |
2221 | clk_writel(val, c->reg); | |
2222 | } | |
2223 | ||
88e790a4 | 2224 | struct clk_ops tegra_cml_clk_ops = { |
92fe58f0 PG |
2225 | .is_enabled = tegra30_cml_clk_is_enabled, |
2226 | .enable = tegra30_cml_clk_enable, | |
2227 | .disable = tegra30_cml_clk_disable, | |
2228 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
2229 | }; | |
2230 | ||
2231 | struct clk_ops tegra_pciex_clk_ops = { | |
2232 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
d9cc6f76 | 2233 | }; |
dab403ef JL |
2234 | |
2235 | /* Tegra30 CPU clock and reset control functions */ | |
2236 | static void tegra30_wait_cpu_in_reset(u32 cpu) | |
2237 | { | |
2238 | unsigned int reg; | |
2239 | ||
2240 | do { | |
2241 | reg = readl(reg_clk_base + | |
2242 | TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); | |
2243 | cpu_relax(); | |
2244 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ | |
2245 | ||
2246 | return; | |
2247 | } | |
2248 | ||
2249 | static void tegra30_put_cpu_in_reset(u32 cpu) | |
2250 | { | |
2251 | writel(CPU_RESET(cpu), | |
2252 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); | |
2253 | dmb(); | |
2254 | } | |
2255 | ||
2256 | static void tegra30_cpu_out_of_reset(u32 cpu) | |
2257 | { | |
2258 | writel(CPU_RESET(cpu), | |
2259 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); | |
2260 | wmb(); | |
2261 | } | |
2262 | ||
2263 | static void tegra30_enable_cpu_clock(u32 cpu) | |
2264 | { | |
2265 | unsigned int reg; | |
2266 | ||
2267 | writel(CPU_CLOCK(cpu), | |
2268 | reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); | |
2269 | reg = readl(reg_clk_base + | |
2270 | TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); | |
2271 | } | |
2272 | ||
2273 | static void tegra30_disable_cpu_clock(u32 cpu) | |
2274 | { | |
2275 | ||
2276 | unsigned int reg; | |
2277 | ||
2278 | reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
2279 | writel(reg | CPU_CLOCK(cpu), | |
2280 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
2281 | } | |
2282 | ||
2283 | static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { | |
2284 | .wait_for_reset = tegra30_wait_cpu_in_reset, | |
2285 | .put_in_reset = tegra30_put_cpu_in_reset, | |
2286 | .out_of_reset = tegra30_cpu_out_of_reset, | |
2287 | .enable_clock = tegra30_enable_cpu_clock, | |
2288 | .disable_clock = tegra30_disable_cpu_clock, | |
2289 | }; | |
2290 | ||
2291 | void __init tegra30_cpu_car_ops_init(void) | |
2292 | { | |
2293 | tegra_cpu_car_ops = &tegra30_cpu_car_ops; | |
2294 | } |