Commit | Line | Data |
---|---|---|
88e790a4 | 1 | /* |
92fe58f0 | 2 | * arch/arm/mach-tegra/tegra30_clocks.c |
88e790a4 | 3 | * |
92fe58f0 | 4 | * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. |
88e790a4 PG |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
18 | * | |
19 | */ | |
20 | ||
92fe58f0 | 21 | #include <linux/clk-private.h> |
88e790a4 PG |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/list.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/cpufreq.h> | |
31 | ||
88e790a4 PG |
32 | #include "clock.h" |
33 | #include "fuse.h" | |
34 | #include "tegra30_clocks.h" | |
35 | ||
92fe58f0 PG |
36 | #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \ |
37 | _parent_names, _parents, _parent) \ | |
38 | static struct clk tegra_##_name = { \ | |
39 | .hw = &tegra_##_name##_hw.hw, \ | |
40 | .name = #_name, \ | |
41 | .rate = _rate, \ | |
42 | .ops = _ops, \ | |
43 | .flags = _flags, \ | |
44 | .parent_names = _parent_names, \ | |
45 | .parents = _parents, \ | |
46 | .num_parents = ARRAY_SIZE(_parent_names), \ | |
47 | .parent = _parent, \ | |
48 | }; | |
49 | ||
50 | static struct clk tegra_clk_32k; | |
51 | static struct clk_tegra tegra_clk_32k_hw = { | |
52 | .hw = { | |
53 | .clk = &tegra_clk_32k, | |
54 | }, | |
55 | .fixed_rate = 32768, | |
56 | }; | |
88e790a4 PG |
57 | static struct clk tegra_clk_32k = { |
58 | .name = "clk_32k", | |
92fe58f0 | 59 | .hw = &tegra_clk_32k_hw.hw, |
b78c030c | 60 | .ops = &tegra30_clk_32k_ops, |
92fe58f0 | 61 | .flags = CLK_IS_ROOT, |
88e790a4 PG |
62 | }; |
63 | ||
92fe58f0 PG |
64 | static struct clk tegra_clk_m; |
65 | static struct clk_tegra tegra_clk_m_hw = { | |
66 | .hw = { | |
67 | .clk = &tegra_clk_m, | |
68 | }, | |
69 | .flags = ENABLE_ON_INIT, | |
70 | .reg = 0x1fc, | |
88e790a4 | 71 | .reg_shift = 28, |
92fe58f0 PG |
72 | .max_rate = 48000000, |
73 | }; | |
74 | static struct clk tegra_clk_m = { | |
75 | .name = "clk_m", | |
76 | .hw = &tegra_clk_m_hw.hw, | |
77 | .ops = &tegra30_clk_m_ops, | |
78 | .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED, | |
88e790a4 PG |
79 | }; |
80 | ||
92fe58f0 PG |
81 | static const char *clk_m_div_parent_names[] = { |
82 | "clk_m", | |
88e790a4 PG |
83 | }; |
84 | ||
92fe58f0 PG |
85 | static struct clk *clk_m_div_parents[] = { |
86 | &tegra_clk_m, | |
88e790a4 PG |
87 | }; |
88 | ||
92fe58f0 PG |
89 | static struct clk tegra_clk_m_div2; |
90 | static struct clk_tegra tegra_clk_m_div2_hw = { | |
91 | .hw = { | |
92 | .clk = &tegra_clk_m_div2, | |
93 | }, | |
94 | .mul = 1, | |
95 | .div = 2, | |
96 | .max_rate = 24000000, | |
97 | }; | |
98 | DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0, | |
99 | clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m); | |
100 | ||
101 | static struct clk tegra_clk_m_div4; | |
102 | static struct clk_tegra tegra_clk_m_div4_hw = { | |
103 | .hw = { | |
104 | .clk = &tegra_clk_m_div4, | |
105 | }, | |
106 | .mul = 1, | |
107 | .div = 4, | |
108 | .max_rate = 12000000, | |
88e790a4 | 109 | }; |
92fe58f0 PG |
110 | DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0, |
111 | clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m); | |
112 | ||
113 | static struct clk tegra_pll_ref; | |
114 | static struct clk_tegra tegra_pll_ref_hw = { | |
115 | .hw = { | |
116 | .clk = &tegra_pll_ref, | |
117 | }, | |
118 | .flags = ENABLE_ON_INIT, | |
119 | .max_rate = 26000000, | |
120 | }; | |
121 | DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names, | |
122 | clk_m_div_parents, &tegra_clk_m); | |
123 | ||
124 | #define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \ | |
125 | _input_max, _cf_min, _cf_max, _vco_min, \ | |
126 | _vco_max, _freq_table, _lock_delay, _ops, \ | |
127 | _fixed_rate, _clk_cfg_ex, _parent) \ | |
128 | static struct clk tegra_##_name; \ | |
129 | static const char *_name##_parent_names[] = { \ | |
130 | #_parent, \ | |
131 | }; \ | |
132 | static struct clk *_name##_parents[] = { \ | |
133 | &tegra_##_parent, \ | |
134 | }; \ | |
135 | static struct clk_tegra tegra_##_name##_hw = { \ | |
136 | .hw = { \ | |
137 | .clk = &tegra_##_name, \ | |
138 | }, \ | |
139 | .flags = _flags, \ | |
140 | .reg = _reg, \ | |
141 | .max_rate = _max_rate, \ | |
142 | .u.pll = { \ | |
143 | .input_min = _input_min, \ | |
144 | .input_max = _input_max, \ | |
145 | .cf_min = _cf_min, \ | |
146 | .cf_max = _cf_max, \ | |
147 | .vco_min = _vco_min, \ | |
148 | .vco_max = _vco_max, \ | |
149 | .freq_table = _freq_table, \ | |
150 | .lock_delay = _lock_delay, \ | |
151 | .fixed_rate = _fixed_rate, \ | |
152 | }, \ | |
153 | .clk_cfg_ex = _clk_cfg_ex, \ | |
154 | }; \ | |
155 | DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \ | |
156 | _name##_parent_names, _name##_parents, \ | |
157 | &tegra_##_parent); | |
158 | ||
159 | #define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \ | |
160 | _max_rate, _ops, _parent, _clk_flags) \ | |
161 | static const char *_name##_parent_names[] = { \ | |
162 | #_parent, \ | |
163 | }; \ | |
164 | static struct clk *_name##_parents[] = { \ | |
165 | &tegra_##_parent, \ | |
166 | }; \ | |
167 | static struct clk tegra_##_name; \ | |
168 | static struct clk_tegra tegra_##_name##_hw = { \ | |
169 | .hw = { \ | |
170 | .clk = &tegra_##_name, \ | |
171 | }, \ | |
172 | .flags = _flags, \ | |
173 | .reg = _reg, \ | |
174 | .max_rate = _max_rate, \ | |
175 | .reg_shift = _reg_shift, \ | |
176 | }; \ | |
177 | DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \ | |
178 | _clk_flags, _name##_parent_names, \ | |
179 | _name##_parents, &tegra_##_parent); | |
88e790a4 PG |
180 | |
181 | static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { | |
182 | { 12000000, 1040000000, 520, 6, 1, 8}, | |
183 | { 13000000, 1040000000, 480, 6, 1, 8}, | |
92fe58f0 | 184 | { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ |
88e790a4 PG |
185 | { 19200000, 1040000000, 325, 6, 1, 6}, |
186 | { 26000000, 1040000000, 520, 13, 1, 8}, | |
187 | ||
188 | { 12000000, 832000000, 416, 6, 1, 8}, | |
189 | { 13000000, 832000000, 832, 13, 1, 8}, | |
92fe58f0 | 190 | { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ |
88e790a4 PG |
191 | { 19200000, 832000000, 260, 6, 1, 8}, |
192 | { 26000000, 832000000, 416, 13, 1, 8}, | |
193 | ||
194 | { 12000000, 624000000, 624, 12, 1, 8}, | |
195 | { 13000000, 624000000, 624, 13, 1, 8}, | |
196 | { 16800000, 600000000, 520, 14, 1, 8}, | |
197 | { 19200000, 624000000, 520, 16, 1, 8}, | |
198 | { 26000000, 624000000, 624, 26, 1, 8}, | |
199 | ||
200 | { 12000000, 600000000, 600, 12, 1, 8}, | |
201 | { 13000000, 600000000, 600, 13, 1, 8}, | |
202 | { 16800000, 600000000, 500, 14, 1, 8}, | |
203 | { 19200000, 600000000, 375, 12, 1, 6}, | |
204 | { 26000000, 600000000, 600, 26, 1, 8}, | |
205 | ||
206 | { 12000000, 520000000, 520, 12, 1, 8}, | |
207 | { 13000000, 520000000, 520, 13, 1, 8}, | |
92fe58f0 | 208 | { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ |
88e790a4 PG |
209 | { 19200000, 520000000, 325, 12, 1, 6}, |
210 | { 26000000, 520000000, 520, 26, 1, 8}, | |
211 | ||
212 | { 12000000, 416000000, 416, 12, 1, 8}, | |
213 | { 13000000, 416000000, 416, 13, 1, 8}, | |
92fe58f0 | 214 | { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ |
88e790a4 PG |
215 | { 19200000, 416000000, 260, 12, 1, 6}, |
216 | { 26000000, 416000000, 416, 26, 1, 8}, | |
217 | { 0, 0, 0, 0, 0, 0 }, | |
218 | }; | |
219 | ||
92fe58f0 PG |
220 | DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000, |
221 | 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300, | |
222 | tegra30_pll_ops, 0, NULL, pll_ref); | |
88e790a4 | 223 | |
92fe58f0 PG |
224 | DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000, |
225 | tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED); | |
88e790a4 PG |
226 | |
227 | static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { | |
228 | { 12000000, 666000000, 666, 12, 1, 8}, | |
229 | { 13000000, 666000000, 666, 13, 1, 8}, | |
230 | { 16800000, 666000000, 555, 14, 1, 8}, | |
231 | { 19200000, 666000000, 555, 16, 1, 8}, | |
232 | { 26000000, 666000000, 666, 26, 1, 8}, | |
233 | { 12000000, 600000000, 600, 12, 1, 8}, | |
234 | { 13000000, 600000000, 600, 13, 1, 8}, | |
235 | { 16800000, 600000000, 500, 14, 1, 8}, | |
236 | { 19200000, 600000000, 375, 12, 1, 6}, | |
237 | { 26000000, 600000000, 600, 26, 1, 8}, | |
238 | { 0, 0, 0, 0, 0, 0 }, | |
239 | }; | |
240 | ||
92fe58f0 PG |
241 | DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000, |
242 | 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, | |
243 | 300, tegra30_pll_ops, 0, NULL, pll_ref); | |
88e790a4 | 244 | |
92fe58f0 PG |
245 | DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000, |
246 | tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED); | |
88e790a4 PG |
247 | |
248 | static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { | |
249 | { 12000000, 216000000, 432, 12, 2, 8}, | |
250 | { 13000000, 216000000, 432, 13, 2, 8}, | |
251 | { 16800000, 216000000, 360, 14, 2, 8}, | |
252 | { 19200000, 216000000, 360, 16, 2, 8}, | |
253 | { 26000000, 216000000, 432, 26, 2, 8}, | |
254 | { 0, 0, 0, 0, 0, 0 }, | |
255 | }; | |
256 | ||
92fe58f0 PG |
257 | DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000, |
258 | 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, | |
259 | tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL, | |
260 | pll_ref); | |
88e790a4 | 261 | |
92fe58f0 PG |
262 | DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, |
263 | 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); | |
264 | DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, | |
265 | 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); | |
266 | DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, | |
267 | 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); | |
268 | DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, | |
269 | 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); | |
88e790a4 PG |
270 | |
271 | static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { | |
272 | { 9600000, 564480000, 294, 5, 1, 4}, | |
273 | { 9600000, 552960000, 288, 5, 1, 4}, | |
274 | { 9600000, 24000000, 5, 2, 1, 1}, | |
275 | ||
276 | { 28800000, 56448000, 49, 25, 1, 1}, | |
277 | { 28800000, 73728000, 64, 25, 1, 1}, | |
278 | { 28800000, 24000000, 5, 6, 1, 1}, | |
279 | { 0, 0, 0, 0, 0, 0 }, | |
280 | }; | |
281 | ||
92fe58f0 PG |
282 | DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000, |
283 | 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, | |
284 | 300, tegra30_pll_ops, 0, NULL, pll_p_out1); | |
88e790a4 | 285 | |
92fe58f0 PG |
286 | DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops, |
287 | pll_a, CLK_IGNORE_UNUSED); | |
88e790a4 PG |
288 | |
289 | static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { | |
290 | { 12000000, 216000000, 216, 12, 1, 4}, | |
291 | { 13000000, 216000000, 216, 13, 1, 4}, | |
292 | { 16800000, 216000000, 180, 14, 1, 4}, | |
293 | { 19200000, 216000000, 180, 16, 1, 4}, | |
294 | { 26000000, 216000000, 216, 26, 1, 4}, | |
295 | ||
296 | { 12000000, 594000000, 594, 12, 1, 8}, | |
297 | { 13000000, 594000000, 594, 13, 1, 8}, | |
298 | { 16800000, 594000000, 495, 14, 1, 8}, | |
299 | { 19200000, 594000000, 495, 16, 1, 8}, | |
300 | { 26000000, 594000000, 594, 26, 1, 8}, | |
301 | ||
302 | { 12000000, 1000000000, 1000, 12, 1, 12}, | |
303 | { 13000000, 1000000000, 1000, 13, 1, 12}, | |
304 | { 19200000, 1000000000, 625, 12, 1, 8}, | |
305 | { 26000000, 1000000000, 1000, 26, 1, 12}, | |
306 | ||
307 | { 0, 0, 0, 0, 0, 0 }, | |
308 | }; | |
309 | ||
92fe58f0 PG |
310 | DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000, |
311 | 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table, | |
312 | 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref); | |
88e790a4 | 313 | |
92fe58f0 PG |
314 | DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops, |
315 | pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED); | |
88e790a4 | 316 | |
92fe58f0 PG |
317 | DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000, |
318 | 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000, | |
319 | tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL, | |
320 | pll_ref); | |
321 | ||
322 | DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops, | |
323 | pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED); | |
88e790a4 PG |
324 | |
325 | static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { | |
326 | { 12000000, 480000000, 960, 12, 2, 12}, | |
327 | { 13000000, 480000000, 960, 13, 2, 12}, | |
328 | { 16800000, 480000000, 400, 7, 2, 5}, | |
329 | { 19200000, 480000000, 200, 4, 2, 3}, | |
330 | { 26000000, 480000000, 960, 26, 2, 12}, | |
331 | { 0, 0, 0, 0, 0, 0 }, | |
332 | }; | |
333 | ||
92fe58f0 PG |
334 | DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000, |
335 | 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table, | |
336 | 1000, tegra30_pll_ops, 0, NULL, pll_ref); | |
88e790a4 PG |
337 | |
338 | static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { | |
339 | /* 1.7 GHz */ | |
340 | { 12000000, 1700000000, 850, 6, 1, 8}, | |
341 | { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ | |
342 | { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ | |
343 | { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ | |
344 | { 26000000, 1700000000, 850, 13, 1, 8}, | |
345 | ||
346 | /* 1.6 GHz */ | |
347 | { 12000000, 1600000000, 800, 6, 1, 8}, | |
348 | { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ | |
349 | { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ | |
350 | { 19200000, 1600000000, 500, 6, 1, 8}, | |
351 | { 26000000, 1600000000, 800, 13, 1, 8}, | |
352 | ||
353 | /* 1.5 GHz */ | |
354 | { 12000000, 1500000000, 750, 6, 1, 8}, | |
355 | { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ | |
356 | { 16800000, 1500000000, 625, 7, 1, 8}, | |
357 | { 19200000, 1500000000, 625, 8, 1, 8}, | |
358 | { 26000000, 1500000000, 750, 13, 1, 8}, | |
359 | ||
360 | /* 1.4 GHz */ | |
361 | { 12000000, 1400000000, 700, 6, 1, 8}, | |
362 | { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ | |
363 | { 16800000, 1400000000, 1000, 12, 1, 8}, | |
364 | { 19200000, 1400000000, 875, 12, 1, 8}, | |
365 | { 26000000, 1400000000, 700, 13, 1, 8}, | |
366 | ||
367 | /* 1.3 GHz */ | |
368 | { 12000000, 1300000000, 975, 9, 1, 8}, | |
369 | { 13000000, 1300000000, 1000, 10, 1, 8}, | |
370 | { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ | |
371 | { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ | |
372 | { 26000000, 1300000000, 650, 13, 1, 8}, | |
373 | ||
374 | /* 1.2 GHz */ | |
375 | { 12000000, 1200000000, 1000, 10, 1, 8}, | |
376 | { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ | |
377 | { 16800000, 1200000000, 1000, 14, 1, 8}, | |
378 | { 19200000, 1200000000, 1000, 16, 1, 8}, | |
379 | { 26000000, 1200000000, 600, 13, 1, 8}, | |
380 | ||
381 | /* 1.1 GHz */ | |
382 | { 12000000, 1100000000, 825, 9, 1, 8}, | |
383 | { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ | |
384 | { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ | |
385 | { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ | |
386 | { 26000000, 1100000000, 550, 13, 1, 8}, | |
387 | ||
388 | /* 1 GHz */ | |
389 | { 12000000, 1000000000, 1000, 12, 1, 8}, | |
390 | { 13000000, 1000000000, 1000, 13, 1, 8}, | |
391 | { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ | |
392 | { 19200000, 1000000000, 625, 12, 1, 8}, | |
393 | { 26000000, 1000000000, 1000, 26, 1, 8}, | |
394 | ||
395 | { 0, 0, 0, 0, 0, 0 }, | |
396 | }; | |
397 | ||
92fe58f0 PG |
398 | DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000, |
399 | 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000, | |
400 | tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref); | |
88e790a4 | 401 | |
92fe58f0 PG |
402 | DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops, |
403 | pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED); | |
88e790a4 PG |
404 | |
405 | static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { | |
406 | /* PLLE special case: use cpcon field to store cml divider value */ | |
407 | { 12000000, 100000000, 150, 1, 18, 11}, | |
408 | { 216000000, 100000000, 200, 18, 24, 13}, | |
409 | { 0, 0, 0, 0, 0, 0 }, | |
410 | }; | |
411 | ||
92fe58f0 PG |
412 | DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000, |
413 | 12000000, 12000000, 1200000000, 2400000000U, | |
414 | tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL, | |
415 | pll_ref); | |
416 | ||
417 | static const char *mux_plle[] = { | |
418 | "pll_e", | |
419 | }; | |
420 | ||
421 | static struct clk *mux_plle_p[] = { | |
422 | &tegra_pll_e, | |
88e790a4 PG |
423 | }; |
424 | ||
92fe58f0 PG |
425 | static struct clk tegra_cml0; |
426 | static struct clk_tegra tegra_cml0_hw = { | |
427 | .hw = { | |
428 | .clk = &tegra_cml0, | |
429 | }, | |
430 | .reg = 0x48c, | |
431 | .fixed_rate = 100000000, | |
432 | .u.periph = { | |
88e790a4 PG |
433 | .clk_num = 0, |
434 | }, | |
435 | }; | |
92fe58f0 PG |
436 | DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle, |
437 | mux_plle_p, &tegra_pll_e); | |
88e790a4 | 438 | |
92fe58f0 PG |
439 | static struct clk tegra_cml1; |
440 | static struct clk_tegra tegra_cml1_hw = { | |
441 | .hw = { | |
442 | .clk = &tegra_cml1, | |
443 | }, | |
444 | .reg = 0x48c, | |
445 | .fixed_rate = 100000000, | |
446 | .u.periph = { | |
447 | .clk_num = 1, | |
88e790a4 PG |
448 | }, |
449 | }; | |
92fe58f0 PG |
450 | DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle, |
451 | mux_plle_p, &tegra_pll_e); | |
88e790a4 | 452 | |
92fe58f0 PG |
453 | static struct clk tegra_pciex; |
454 | static struct clk_tegra tegra_pciex_hw = { | |
455 | .hw = { | |
456 | .clk = &tegra_pciex, | |
457 | }, | |
458 | .reg = 0x48c, | |
459 | .fixed_rate = 100000000, | |
460 | .reset = tegra30_periph_clk_reset, | |
461 | .u.periph = { | |
462 | .clk_num = 74, | |
88e790a4 PG |
463 | }, |
464 | }; | |
92fe58f0 PG |
465 | DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle, |
466 | mux_plle_p, &tegra_pll_e); | |
88e790a4 | 467 | |
92fe58f0 PG |
468 | #define SYNC_SOURCE(_name) \ |
469 | static struct clk tegra_##_name##_sync; \ | |
470 | static struct clk_tegra tegra_##_name##_sync_hw = { \ | |
471 | .hw = { \ | |
472 | .clk = &tegra_##_name##_sync, \ | |
473 | }, \ | |
474 | .max_rate = 24000000, \ | |
475 | .fixed_rate = 24000000, \ | |
476 | }; \ | |
477 | static struct clk tegra_##_name##_sync = { \ | |
478 | .name = #_name "_sync", \ | |
479 | .hw = &tegra_##_name##_sync_hw.hw, \ | |
480 | .ops = &tegra_sync_source_ops, \ | |
481 | .flags = CLK_IS_ROOT, \ | |
482 | }; | |
483 | ||
484 | SYNC_SOURCE(spdif_in); | |
485 | SYNC_SOURCE(i2s0); | |
486 | SYNC_SOURCE(i2s1); | |
487 | SYNC_SOURCE(i2s2); | |
488 | SYNC_SOURCE(i2s3); | |
489 | SYNC_SOURCE(i2s4); | |
490 | SYNC_SOURCE(vimclk); | |
491 | ||
492 | static struct clk *tegra_sync_source_list[] = { | |
493 | &tegra_spdif_in_sync, | |
494 | &tegra_i2s0_sync, | |
495 | &tegra_i2s1_sync, | |
496 | &tegra_i2s2_sync, | |
497 | &tegra_i2s3_sync, | |
498 | &tegra_i2s4_sync, | |
499 | &tegra_vimclk_sync, | |
500 | }; | |
501 | ||
502 | static const char *mux_audio_sync_clk[] = { | |
503 | "spdif_in_sync", | |
504 | "i2s0_sync", | |
505 | "i2s1_sync", | |
506 | "i2s2_sync", | |
507 | "i2s3_sync", | |
508 | "i2s4_sync", | |
509 | "vimclk_sync", | |
510 | }; | |
511 | ||
512 | #define AUDIO_SYNC_CLK(_name, _index) \ | |
513 | static struct clk tegra_##_name; \ | |
514 | static struct clk_tegra tegra_##_name##_hw = { \ | |
515 | .hw = { \ | |
516 | .clk = &tegra_##_name, \ | |
517 | }, \ | |
518 | .max_rate = 24000000, \ | |
519 | .reg = 0x4A0 + (_index) * 4, \ | |
520 | }; \ | |
521 | static struct clk tegra_##_name = { \ | |
522 | .name = #_name, \ | |
9c54db6d | 523 | .ops = &tegra30_audio_sync_clk_ops, \ |
92fe58f0 PG |
524 | .hw = &tegra_##_name##_hw.hw, \ |
525 | .parent_names = mux_audio_sync_clk, \ | |
526 | .parents = tegra_sync_source_list, \ | |
527 | .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \ | |
528 | }; | |
529 | ||
530 | AUDIO_SYNC_CLK(audio0, 0); | |
531 | AUDIO_SYNC_CLK(audio1, 1); | |
532 | AUDIO_SYNC_CLK(audio2, 2); | |
533 | AUDIO_SYNC_CLK(audio3, 3); | |
534 | AUDIO_SYNC_CLK(audio4, 4); | |
535 | AUDIO_SYNC_CLK(audio5, 5); | |
536 | ||
537 | static struct clk *tegra_clk_audio_list[] = { | |
538 | &tegra_audio0, | |
539 | &tegra_audio1, | |
540 | &tegra_audio2, | |
541 | &tegra_audio3, | |
542 | &tegra_audio4, | |
543 | &tegra_audio5, /* SPDIF */ | |
544 | }; | |
545 | ||
546 | #define AUDIO_SYNC_2X_CLK(_name, _index) \ | |
547 | static const char *_name##_parent_names[] = { \ | |
548 | "tegra_" #_name, \ | |
549 | }; \ | |
550 | static struct clk *_name##_parents[] = { \ | |
551 | &tegra_##_name, \ | |
552 | }; \ | |
553 | static struct clk tegra_##_name##_2x; \ | |
554 | static struct clk_tegra tegra_##_name##_2x_hw = { \ | |
555 | .hw = { \ | |
556 | .clk = &tegra_##_name##_2x, \ | |
557 | }, \ | |
558 | .flags = PERIPH_NO_RESET, \ | |
559 | .max_rate = 48000000, \ | |
560 | .reg = 0x49C, \ | |
88e790a4 | 561 | .reg_shift = 24 + (_index), \ |
88e790a4 PG |
562 | .u.periph = { \ |
563 | .clk_num = 113 + (_index), \ | |
564 | }, \ | |
92fe58f0 PG |
565 | }; \ |
566 | static struct clk tegra_##_name##_2x = { \ | |
567 | .name = #_name "_2x", \ | |
568 | .ops = &tegra30_clk_double_ops, \ | |
569 | .hw = &tegra_##_name##_2x_hw.hw, \ | |
570 | .parent_names = _name##_parent_names, \ | |
571 | .parents = _name##_parents, \ | |
572 | .parent = &tegra_##_name, \ | |
573 | .num_parents = 1, \ | |
574 | }; | |
575 | ||
576 | AUDIO_SYNC_2X_CLK(audio0, 0); | |
577 | AUDIO_SYNC_2X_CLK(audio1, 1); | |
578 | AUDIO_SYNC_2X_CLK(audio2, 2); | |
579 | AUDIO_SYNC_2X_CLK(audio3, 3); | |
580 | AUDIO_SYNC_2X_CLK(audio4, 4); | |
581 | AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */ | |
582 | ||
583 | static struct clk *tegra_clk_audio_2x_list[] = { | |
584 | &tegra_audio0_2x, | |
585 | &tegra_audio1_2x, | |
586 | &tegra_audio2_2x, | |
587 | &tegra_audio3_2x, | |
588 | &tegra_audio4_2x, | |
589 | &tegra_audio5_2x, /* SPDIF */ | |
590 | }; | |
591 | ||
592 | #define MUX_I2S_SPDIF(_id) \ | |
593 | static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ | |
594 | "pll_a_out0", \ | |
595 | #_id "_2x", \ | |
596 | "pll_p", \ | |
597 | "clk_m", \ | |
598 | }; \ | |
599 | static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \ | |
600 | &tegra_pll_a_out0, \ | |
601 | &tegra_##_id##_2x, \ | |
602 | &tegra_pll_p, \ | |
603 | &tegra_clk_m, \ | |
604 | }; | |
605 | ||
606 | MUX_I2S_SPDIF(audio0); | |
607 | MUX_I2S_SPDIF(audio1); | |
608 | MUX_I2S_SPDIF(audio2); | |
609 | MUX_I2S_SPDIF(audio3); | |
610 | MUX_I2S_SPDIF(audio4); | |
611 | MUX_I2S_SPDIF(audio5); /* SPDIF */ | |
612 | ||
613 | static struct clk tegra_extern1; | |
614 | static struct clk tegra_extern2; | |
615 | static struct clk tegra_extern3; | |
88e790a4 PG |
616 | |
617 | /* External clock outputs (through PMC) */ | |
92fe58f0 PG |
618 | #define MUX_EXTERN_OUT(_id) \ |
619 | static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \ | |
620 | "clk_m", \ | |
621 | "clk_m_div2", \ | |
622 | "clk_m_div4", \ | |
623 | "extern" #_id, \ | |
624 | }; \ | |
625 | static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \ | |
626 | &tegra_clk_m, \ | |
627 | &tegra_clk_m_div2, \ | |
628 | &tegra_clk_m_div4, \ | |
629 | &tegra_extern##_id, \ | |
630 | }; | |
631 | ||
88e790a4 PG |
632 | MUX_EXTERN_OUT(1); |
633 | MUX_EXTERN_OUT(2); | |
634 | MUX_EXTERN_OUT(3); | |
635 | ||
92fe58f0 PG |
636 | #define CLK_OUT_CLK(_name, _index) \ |
637 | static struct clk tegra_##_name; \ | |
638 | static struct clk_tegra tegra_##_name##_hw = { \ | |
639 | .hw = { \ | |
640 | .clk = &tegra_##_name, \ | |
641 | }, \ | |
642 | .lookup = { \ | |
643 | .dev_id = #_name, \ | |
644 | .con_id = "extern" #_index, \ | |
645 | }, \ | |
646 | .flags = MUX_CLK_OUT, \ | |
647 | .fixed_rate = 216000000, \ | |
648 | .reg = 0x1a8, \ | |
649 | .u.periph = { \ | |
650 | .clk_num = (_index - 1) * 8 + 2, \ | |
651 | }, \ | |
652 | }; \ | |
653 | static struct clk tegra_##_name = { \ | |
654 | .name = #_name, \ | |
655 | .ops = &tegra_clk_out_ops, \ | |
656 | .hw = &tegra_##_name##_hw.hw, \ | |
657 | .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \ | |
658 | .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \ | |
659 | .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\ | |
660 | }; | |
661 | ||
662 | CLK_OUT_CLK(clk_out_1, 1); | |
663 | CLK_OUT_CLK(clk_out_2, 2); | |
664 | CLK_OUT_CLK(clk_out_3, 3); | |
665 | ||
666 | static struct clk *tegra_clk_out_list[] = { | |
667 | &tegra_clk_out_1, | |
668 | &tegra_clk_out_2, | |
669 | &tegra_clk_out_3, | |
670 | }; | |
671 | ||
672 | static const char *mux_sclk[] = { | |
673 | "clk_m", | |
674 | "pll_c_out1", | |
675 | "pll_p_out4", | |
676 | "pll_p_out3", | |
677 | "pll_p_out2", | |
678 | "dummy", | |
679 | "clk_32k", | |
680 | "pll_m_out1", | |
681 | }; | |
682 | ||
683 | static struct clk *mux_sclk_p[] = { | |
684 | &tegra_clk_m, | |
685 | &tegra_pll_c_out1, | |
686 | &tegra_pll_p_out4, | |
687 | &tegra_pll_p_out3, | |
688 | &tegra_pll_p_out2, | |
689 | NULL, | |
690 | &tegra_clk_32k, | |
691 | &tegra_pll_m_out1, | |
88e790a4 PG |
692 | }; |
693 | ||
92fe58f0 PG |
694 | static struct clk tegra_clk_sclk; |
695 | static struct clk_tegra tegra_clk_sclk_hw = { | |
696 | .hw = { | |
697 | .clk = &tegra_clk_sclk, | |
698 | }, | |
699 | .reg = 0x28, | |
700 | .max_rate = 334000000, | |
701 | .min_rate = 40000000, | |
88e790a4 PG |
702 | }; |
703 | ||
92fe58f0 PG |
704 | static struct clk tegra_clk_sclk = { |
705 | .name = "sclk", | |
706 | .ops = &tegra30_super_ops, | |
707 | .hw = &tegra_clk_sclk_hw.hw, | |
708 | .parent_names = mux_sclk, | |
709 | .parents = mux_sclk_p, | |
710 | .num_parents = ARRAY_SIZE(mux_sclk), | |
711 | }; | |
88e790a4 | 712 | |
92fe58f0 PG |
713 | static const char *mux_blink[] = { |
714 | "clk_32k", | |
88e790a4 PG |
715 | }; |
716 | ||
92fe58f0 PG |
717 | static struct clk *mux_blink_p[] = { |
718 | &tegra_clk_32k, | |
88e790a4 PG |
719 | }; |
720 | ||
92fe58f0 PG |
721 | static struct clk tegra_clk_blink; |
722 | static struct clk_tegra tegra_clk_blink_hw = { | |
723 | .hw = { | |
724 | .clk = &tegra_clk_blink, | |
725 | }, | |
726 | .reg = 0x40, | |
727 | .max_rate = 32768, | |
728 | }; | |
88e790a4 | 729 | static struct clk tegra_clk_blink = { |
92fe58f0 PG |
730 | .name = "blink", |
731 | .ops = &tegra30_blink_clk_ops, | |
732 | .hw = &tegra_clk_blink_hw.hw, | |
733 | .parent = &tegra_clk_32k, | |
734 | .parent_names = mux_blink, | |
735 | .parents = mux_blink_p, | |
736 | .num_parents = ARRAY_SIZE(mux_blink), | |
88e790a4 PG |
737 | }; |
738 | ||
92fe58f0 PG |
739 | static const char *mux_pllm_pllc_pllp_plla[] = { |
740 | "pll_m", | |
741 | "pll_c", | |
742 | "pll_p", | |
743 | "pll_a_out0", | |
88e790a4 PG |
744 | }; |
745 | ||
92fe58f0 PG |
746 | static const char *mux_pllp_pllc_pllm_clkm[] = { |
747 | "pll_p", | |
748 | "pll_c", | |
749 | "pll_m", | |
750 | "clk_m", | |
88e790a4 PG |
751 | }; |
752 | ||
92fe58f0 PG |
753 | static const char *mux_pllp_clkm[] = { |
754 | "pll_p", | |
755 | "dummy", | |
756 | "dummy", | |
757 | "clk_m", | |
88e790a4 PG |
758 | }; |
759 | ||
92fe58f0 PG |
760 | static const char *mux_pllp_plld_pllc_clkm[] = { |
761 | "pll_p", | |
762 | "pll_d_out0", | |
763 | "pll_c", | |
764 | "clk_m", | |
88e790a4 PG |
765 | }; |
766 | ||
92fe58f0 PG |
767 | static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { |
768 | "pll_p", | |
769 | "pll_m", | |
770 | "pll_d_out0", | |
771 | "pll_a_out0", | |
772 | "pll_c", | |
773 | "pll_d2_out0", | |
774 | "clk_m", | |
88e790a4 PG |
775 | }; |
776 | ||
92fe58f0 PG |
777 | static const char *mux_plla_pllc_pllp_clkm[] = { |
778 | "pll_a_out0", | |
779 | "dummy", | |
780 | "pll_p", | |
781 | "clk_m" | |
88e790a4 PG |
782 | }; |
783 | ||
92fe58f0 PG |
784 | static const char *mux_pllp_pllc_clk32_clkm[] = { |
785 | "pll_p", | |
786 | "pll_c", | |
787 | "clk_32k", | |
788 | "clk_m", | |
88e790a4 PG |
789 | }; |
790 | ||
92fe58f0 PG |
791 | static const char *mux_pllp_pllc_clkm_clk32[] = { |
792 | "pll_p", | |
793 | "pll_c", | |
794 | "clk_m", | |
795 | "clk_32k", | |
88e790a4 PG |
796 | }; |
797 | ||
92fe58f0 PG |
798 | static const char *mux_pllp_pllc_pllm[] = { |
799 | "pll_p", | |
800 | "pll_c", | |
801 | "pll_m", | |
88e790a4 PG |
802 | }; |
803 | ||
92fe58f0 PG |
804 | static const char *mux_clk_m[] = { |
805 | "clk_m", | |
88e790a4 PG |
806 | }; |
807 | ||
92fe58f0 PG |
808 | static const char *mux_pllp_out3[] = { |
809 | "pll_p_out3", | |
88e790a4 PG |
810 | }; |
811 | ||
92fe58f0 PG |
812 | static const char *mux_plld_out0[] = { |
813 | "pll_d_out0", | |
88e790a4 PG |
814 | }; |
815 | ||
92fe58f0 PG |
816 | static const char *mux_plld_out0_plld2_out0[] = { |
817 | "pll_d_out0", | |
818 | "pll_d2_out0", | |
88e790a4 PG |
819 | }; |
820 | ||
92fe58f0 PG |
821 | static const char *mux_clk_32k[] = { |
822 | "clk_32k", | |
88e790a4 PG |
823 | }; |
824 | ||
92fe58f0 PG |
825 | static const char *mux_plla_clk32_pllp_clkm_plle[] = { |
826 | "pll_a_out0", | |
827 | "clk_32k", | |
828 | "pll_p", | |
829 | "clk_m", | |
830 | "pll_e", | |
88e790a4 PG |
831 | }; |
832 | ||
92fe58f0 PG |
833 | static const char *mux_cclk_g[] = { |
834 | "clk_m", | |
835 | "pll_c", | |
836 | "clk_32k", | |
837 | "pll_m", | |
838 | "pll_p", | |
839 | "pll_p_out4", | |
840 | "pll_p_out3", | |
841 | "dummy", | |
842 | "pll_x", | |
88e790a4 PG |
843 | }; |
844 | ||
92fe58f0 PG |
845 | static struct clk *mux_pllm_pllc_pllp_plla_p[] = { |
846 | &tegra_pll_m, | |
847 | &tegra_pll_c, | |
848 | &tegra_pll_p, | |
849 | &tegra_pll_a_out0, | |
850 | }; | |
851 | ||
852 | static struct clk *mux_pllp_pllc_pllm_clkm_p[] = { | |
853 | &tegra_pll_p, | |
854 | &tegra_pll_c, | |
855 | &tegra_pll_m, | |
856 | &tegra_clk_m, | |
857 | }; | |
858 | ||
859 | static struct clk *mux_pllp_clkm_p[] = { | |
860 | &tegra_pll_p, | |
861 | NULL, | |
862 | NULL, | |
863 | &tegra_clk_m, | |
864 | }; | |
865 | ||
866 | static struct clk *mux_pllp_plld_pllc_clkm_p[] = { | |
867 | &tegra_pll_p, | |
868 | &tegra_pll_d_out0, | |
869 | &tegra_pll_c, | |
870 | &tegra_clk_m, | |
871 | }; | |
872 | ||
873 | static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = { | |
874 | &tegra_pll_p, | |
875 | &tegra_pll_m, | |
876 | &tegra_pll_d_out0, | |
877 | &tegra_pll_a_out0, | |
878 | &tegra_pll_c, | |
879 | &tegra_pll_d2_out0, | |
880 | &tegra_clk_m, | |
881 | }; | |
882 | ||
883 | static struct clk *mux_plla_pllc_pllp_clkm_p[] = { | |
884 | &tegra_pll_a_out0, | |
885 | NULL, | |
886 | &tegra_pll_p, | |
887 | &tegra_clk_m, | |
888 | }; | |
889 | ||
890 | static struct clk *mux_pllp_pllc_clk32_clkm_p[] = { | |
891 | &tegra_pll_p, | |
892 | &tegra_pll_c, | |
893 | &tegra_clk_32k, | |
894 | &tegra_clk_m, | |
895 | }; | |
896 | ||
897 | static struct clk *mux_pllp_pllc_clkm_clk32_p[] = { | |
898 | &tegra_pll_p, | |
899 | &tegra_pll_c, | |
900 | &tegra_clk_m, | |
901 | &tegra_clk_32k, | |
902 | }; | |
903 | ||
904 | static struct clk *mux_pllp_pllc_pllm_p[] = { | |
905 | &tegra_pll_p, | |
906 | &tegra_pll_c, | |
907 | &tegra_pll_m, | |
908 | }; | |
909 | ||
910 | static struct clk *mux_clk_m_p[] = { | |
911 | &tegra_clk_m, | |
912 | }; | |
913 | ||
914 | static struct clk *mux_pllp_out3_p[] = { | |
915 | &tegra_pll_p_out3, | |
916 | }; | |
917 | ||
918 | static struct clk *mux_plld_out0_p[] = { | |
919 | &tegra_pll_d_out0, | |
920 | }; | |
921 | ||
922 | static struct clk *mux_plld_out0_plld2_out0_p[] = { | |
923 | &tegra_pll_d_out0, | |
924 | &tegra_pll_d2_out0, | |
925 | }; | |
926 | ||
927 | static struct clk *mux_clk_32k_p[] = { | |
928 | &tegra_clk_32k, | |
929 | }; | |
930 | ||
931 | static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = { | |
932 | &tegra_pll_a_out0, | |
933 | &tegra_clk_32k, | |
934 | &tegra_pll_p, | |
935 | &tegra_clk_m, | |
936 | &tegra_pll_e, | |
937 | }; | |
938 | ||
939 | static struct clk *mux_cclk_g_p[] = { | |
940 | &tegra_clk_m, | |
941 | &tegra_pll_c, | |
942 | &tegra_clk_32k, | |
943 | &tegra_pll_m, | |
944 | &tegra_pll_p, | |
945 | &tegra_pll_p_out4, | |
946 | &tegra_pll_p_out3, | |
947 | NULL, | |
948 | &tegra_pll_x, | |
949 | }; | |
950 | ||
951 | static struct clk tegra_clk_cclk_g; | |
952 | static struct clk_tegra tegra_clk_cclk_g_hw = { | |
953 | .hw = { | |
954 | .clk = &tegra_clk_cclk_g, | |
955 | }, | |
956 | .flags = DIV_U71 | DIV_U71_INT, | |
957 | .reg = 0x368, | |
88e790a4 PG |
958 | .max_rate = 1700000000, |
959 | }; | |
92fe58f0 PG |
960 | static struct clk tegra_clk_cclk_g = { |
961 | .name = "cclk_g", | |
962 | .ops = &tegra30_super_ops, | |
963 | .hw = &tegra_clk_cclk_g_hw.hw, | |
964 | .parent_names = mux_cclk_g, | |
965 | .parents = mux_cclk_g_p, | |
966 | .num_parents = ARRAY_SIZE(mux_cclk_g), | |
967 | }; | |
88e790a4 | 968 | |
92fe58f0 PG |
969 | static const char *mux_twd[] = { |
970 | "cclk_g", | |
971 | }; | |
88e790a4 | 972 | |
92fe58f0 PG |
973 | static struct clk *mux_twd_p[] = { |
974 | &tegra_clk_cclk_g, | |
975 | }; | |
88e790a4 | 976 | |
92fe58f0 PG |
977 | static struct clk tegra30_clk_twd; |
978 | static struct clk_tegra tegra30_clk_twd_hw = { | |
979 | .hw = { | |
980 | .clk = &tegra30_clk_twd, | |
981 | }, | |
982 | .max_rate = 1400000000, | |
983 | .mul = 1, | |
984 | .div = 2, | |
985 | }; | |
986 | ||
987 | static struct clk tegra30_clk_twd = { | |
988 | .name = "twd", | |
989 | .ops = &tegra30_twd_ops, | |
990 | .hw = &tegra30_clk_twd_hw.hw, | |
991 | .parent = &tegra_clk_cclk_g, | |
992 | .parent_names = mux_twd, | |
993 | .parents = mux_twd_p, | |
994 | .num_parents = ARRAY_SIZE(mux_twd), | |
995 | }; | |
996 | ||
997 | #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \ | |
998 | _max, _inputs, _flags) \ | |
999 | static struct clk tegra_##_name; \ | |
1000 | static struct clk_tegra tegra_##_name##_hw = { \ | |
1001 | .hw = { \ | |
1002 | .clk = &tegra_##_name, \ | |
88e790a4 | 1003 | }, \ |
92fe58f0 | 1004 | .lookup = { \ |
88e790a4 | 1005 | .dev_id = _dev, \ |
92fe58f0 | 1006 | .con_id = _con, \ |
88e790a4 | 1007 | }, \ |
92fe58f0 PG |
1008 | .reg = _reg, \ |
1009 | .flags = _flags, \ | |
1010 | .max_rate = _max, \ | |
1011 | .u.periph = { \ | |
1012 | .clk_num = _clk_num, \ | |
1013 | }, \ | |
1014 | .reset = &tegra30_periph_clk_reset, \ | |
1015 | }; \ | |
1016 | static struct clk tegra_##_name = { \ | |
1017 | .name = #_name, \ | |
1018 | .ops = &tegra30_periph_clk_ops, \ | |
1019 | .hw = &tegra_##_name##_hw.hw, \ | |
1020 | .parent_names = _inputs, \ | |
1021 | .parents = _inputs##_p, \ | |
1022 | .num_parents = ARRAY_SIZE(_inputs), \ | |
1023 | }; | |
1024 | ||
1025 | PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0); | |
1026 | PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB); | |
1027 | PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB); | |
1028 | PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0); | |
1029 | PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0); | |
1030 | PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB); | |
1031 | PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB); | |
1032 | PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0); | |
1033 | PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1034 | PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1035 | PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1036 | PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1037 | PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1038 | PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1039 | PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1040 | PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB); | |
1041 | PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); | |
1042 | PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); | |
1043 | PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); | |
1044 | PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); | |
1045 | PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); | |
1046 | PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); | |
1047 | PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0); | |
1048 | PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1049 | PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1050 | PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1051 | PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1052 | PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1053 | PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1054 | PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); | |
1055 | PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); | |
1056 | PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0); | |
1057 | PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); | |
1058 | PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); | |
1059 | PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1060 | PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ | |
1061 | PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ | |
1062 | PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ | |
1063 | PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ | |
1064 | PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0); | |
1065 | PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0); | |
1066 | PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0); | |
1067 | PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT); | |
1068 | PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */ | |
1069 | PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); | |
1070 | PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1071 | PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */ | |
1072 | PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */ | |
1073 | PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); | |
1074 | PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); | |
1075 | PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); | |
1076 | PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); | |
1077 | PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); | |
1078 | PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); | |
1079 | PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); | |
1080 | PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); | |
1081 | PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); | |
1082 | PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); | |
1083 | PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); | |
1084 | PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET); | |
1085 | PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET); | |
1086 | PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE); | |
1087 | PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); | |
1088 | PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); | |
1089 | PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); | |
1090 | PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); | |
1091 | PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ | |
1092 | PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ | |
1093 | PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0); | |
1094 | PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71); | |
1095 | PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ | |
1096 | PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8); | |
1097 | PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8); | |
1098 | PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ | |
1099 | PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ | |
1100 | PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ | |
1101 | PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0); | |
1102 | PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0); | |
1103 | PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */ | |
1104 | PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET); | |
1105 | PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71); | |
1106 | PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71); | |
1107 | PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71); | |
1108 | PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71); | |
1109 | PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71); | |
1110 | PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB); | |
1111 | PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0); | |
1112 | PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0); | |
1113 | PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT); | |
1114 | ||
1115 | static struct clk tegra_dsib; | |
1116 | static struct clk_tegra tegra_dsib_hw = { | |
1117 | .hw = { | |
1118 | .clk = &tegra_dsib, | |
1119 | }, | |
1120 | .lookup = { | |
1121 | .dev_id = "tegradc.1", | |
1122 | .con_id = "dsib", | |
1123 | }, | |
1124 | .reg = 0xd0, | |
1125 | .flags = MUX | PLLD, | |
1126 | .max_rate = 500000000, | |
1127 | .u.periph = { | |
1128 | .clk_num = 82, | |
1129 | }, | |
1130 | .reset = &tegra30_periph_clk_reset, | |
1131 | }; | |
1132 | static struct clk tegra_dsib = { | |
1133 | .name = "dsib", | |
1134 | .ops = &tegra30_dsib_clk_ops, | |
1135 | .hw = &tegra_dsib_hw.hw, | |
1136 | .parent_names = mux_plld_out0_plld2_out0, | |
1137 | .parents = mux_plld_out0_plld2_out0_p, | |
1138 | .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0), | |
1139 | }; | |
1140 | ||
1141 | struct clk *tegra_list_clks[] = { | |
1142 | &tegra_apbdma, | |
1143 | &tegra_rtc, | |
1144 | &tegra_kbc, | |
92fe58f0 PG |
1145 | &tegra_kfuse, |
1146 | &tegra_fuse, | |
1147 | &tegra_fuse_burn, | |
1148 | &tegra_apbif, | |
1149 | &tegra_i2s0, | |
1150 | &tegra_i2s1, | |
1151 | &tegra_i2s2, | |
1152 | &tegra_i2s3, | |
1153 | &tegra_i2s4, | |
1154 | &tegra_spdif_out, | |
1155 | &tegra_spdif_in, | |
1156 | &tegra_pwm, | |
1157 | &tegra_d_audio, | |
1158 | &tegra_dam0, | |
1159 | &tegra_dam1, | |
1160 | &tegra_dam2, | |
1161 | &tegra_hda, | |
1162 | &tegra_hda2codec_2x, | |
1163 | &tegra_hda2hdmi, | |
1164 | &tegra_sbc1, | |
1165 | &tegra_sbc2, | |
1166 | &tegra_sbc3, | |
1167 | &tegra_sbc4, | |
1168 | &tegra_sbc5, | |
1169 | &tegra_sbc6, | |
1170 | &tegra_sata_oob, | |
1171 | &tegra_sata, | |
1172 | &tegra_sata_cold, | |
1173 | &tegra_ndflash, | |
1174 | &tegra_ndspeed, | |
1175 | &tegra_vfir, | |
1176 | &tegra_sdmmc1, | |
1177 | &tegra_sdmmc2, | |
1178 | &tegra_sdmmc3, | |
1179 | &tegra_sdmmc4, | |
1180 | &tegra_vcp, | |
1181 | &tegra_bsea, | |
1182 | &tegra_bsev, | |
1183 | &tegra_vde, | |
1184 | &tegra_csite, | |
1185 | &tegra_la, | |
1186 | &tegra_owr, | |
1187 | &tegra_nor, | |
1188 | &tegra_mipi, | |
1189 | &tegra_i2c1, | |
1190 | &tegra_i2c2, | |
1191 | &tegra_i2c3, | |
1192 | &tegra_i2c4, | |
1193 | &tegra_i2c5, | |
1194 | &tegra_uarta, | |
1195 | &tegra_uartb, | |
1196 | &tegra_uartc, | |
1197 | &tegra_uartd, | |
1198 | &tegra_uarte, | |
1199 | &tegra_vi, | |
1200 | &tegra_3d, | |
1201 | &tegra_3d2, | |
1202 | &tegra_2d, | |
1203 | &tegra_vi_sensor, | |
1204 | &tegra_epp, | |
1205 | &tegra_mpe, | |
1206 | &tegra_host1x, | |
1207 | &tegra_cve, | |
1208 | &tegra_tvo, | |
1209 | &tegra_dtv, | |
1210 | &tegra_hdmi, | |
1211 | &tegra_tvdac, | |
1212 | &tegra_disp1, | |
1213 | &tegra_disp2, | |
1214 | &tegra_usbd, | |
1215 | &tegra_usb2, | |
1216 | &tegra_usb3, | |
1217 | &tegra_dsia, | |
1218 | &tegra_dsib, | |
1219 | &tegra_csi, | |
1220 | &tegra_isp, | |
1221 | &tegra_csus, | |
1222 | &tegra_tsensor, | |
1223 | &tegra_actmon, | |
1224 | &tegra_extern1, | |
1225 | &tegra_extern2, | |
1226 | &tegra_extern3, | |
1227 | &tegra_i2cslow, | |
1228 | &tegra_pcie, | |
1229 | &tegra_afi, | |
1230 | &tegra_se, | |
1231 | }; | |
1232 | ||
1233 | #define CLK_DUPLICATE(_name, _dev, _con) \ | |
1234 | { \ | |
1235 | .name = _name, \ | |
1236 | .lookup = { \ | |
1237 | .dev_id = _dev, \ | |
1238 | .con_id = _con, \ | |
1239 | }, \ | |
88e790a4 PG |
1240 | } |
1241 | ||
1242 | /* Some clocks may be used by different drivers depending on the board | |
1243 | * configuration. List those here to register them twice in the clock lookup | |
1244 | * table under two names. | |
1245 | */ | |
1246 | struct clk_duplicate tegra_clk_duplicates[] = { | |
1247 | CLK_DUPLICATE("uarta", "serial8250.0", NULL), | |
1248 | CLK_DUPLICATE("uartb", "serial8250.1", NULL), | |
1249 | CLK_DUPLICATE("uartc", "serial8250.2", NULL), | |
1250 | CLK_DUPLICATE("uartd", "serial8250.3", NULL), | |
1251 | CLK_DUPLICATE("uarte", "serial8250.4", NULL), | |
1252 | CLK_DUPLICATE("usbd", "utmip-pad", NULL), | |
1253 | CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), | |
1254 | CLK_DUPLICATE("usbd", "tegra-otg", NULL), | |
1255 | CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), | |
1256 | CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), | |
1257 | CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), | |
1258 | CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), | |
1259 | CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), | |
1260 | CLK_DUPLICATE("bsev", "nvavp", "bsev"), | |
1261 | CLK_DUPLICATE("vde", "tegra-aes", "vde"), | |
1262 | CLK_DUPLICATE("bsea", "tegra-aes", "bsea"), | |
1263 | CLK_DUPLICATE("bsea", "nvavp", "bsea"), | |
1264 | CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL), | |
1265 | CLK_DUPLICATE("cml0", "tegra_pcie", "cml"), | |
1266 | CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"), | |
1267 | CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL), | |
1268 | CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL), | |
1269 | CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL), | |
1270 | CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL), | |
1271 | CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL), | |
1272 | CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL), | |
1273 | CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL), | |
1274 | CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL), | |
1275 | CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL), | |
1276 | CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL), | |
1277 | CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL), | |
1278 | CLK_DUPLICATE("twd", "smp_twd", NULL), | |
1279 | CLK_DUPLICATE("vcp", "nvavp", "vcp"), | |
1280 | CLK_DUPLICATE("i2s0", NULL, "i2s0"), | |
1281 | CLK_DUPLICATE("i2s1", NULL, "i2s1"), | |
1282 | CLK_DUPLICATE("i2s2", NULL, "i2s2"), | |
1283 | CLK_DUPLICATE("i2s3", NULL, "i2s3"), | |
1284 | CLK_DUPLICATE("i2s4", NULL, "i2s4"), | |
1285 | CLK_DUPLICATE("dam0", NULL, "dam0"), | |
1286 | CLK_DUPLICATE("dam1", NULL, "dam1"), | |
1287 | CLK_DUPLICATE("dam2", NULL, "dam2"), | |
1288 | CLK_DUPLICATE("spdif_in", NULL, "spdif_in"), | |
e54848d9 LD |
1289 | CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"), |
1290 | CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"), | |
1291 | CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"), | |
1292 | CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"), | |
1293 | CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"), | |
88e790a4 PG |
1294 | }; |
1295 | ||
1296 | struct clk *tegra_ptr_clks[] = { | |
1297 | &tegra_clk_32k, | |
1298 | &tegra_clk_m, | |
1299 | &tegra_clk_m_div2, | |
1300 | &tegra_clk_m_div4, | |
1301 | &tegra_pll_ref, | |
1302 | &tegra_pll_m, | |
1303 | &tegra_pll_m_out1, | |
1304 | &tegra_pll_c, | |
1305 | &tegra_pll_c_out1, | |
1306 | &tegra_pll_p, | |
1307 | &tegra_pll_p_out1, | |
1308 | &tegra_pll_p_out2, | |
1309 | &tegra_pll_p_out3, | |
1310 | &tegra_pll_p_out4, | |
1311 | &tegra_pll_a, | |
1312 | &tegra_pll_a_out0, | |
1313 | &tegra_pll_d, | |
1314 | &tegra_pll_d_out0, | |
1315 | &tegra_pll_d2, | |
1316 | &tegra_pll_d2_out0, | |
1317 | &tegra_pll_u, | |
1318 | &tegra_pll_x, | |
1319 | &tegra_pll_x_out0, | |
1320 | &tegra_pll_e, | |
1321 | &tegra_clk_cclk_g, | |
92fe58f0 PG |
1322 | &tegra_cml0, |
1323 | &tegra_cml1, | |
1324 | &tegra_pciex, | |
88e790a4 PG |
1325 | &tegra_clk_sclk, |
1326 | &tegra_clk_blink, | |
1327 | &tegra30_clk_twd, | |
1328 | }; | |
1329 | ||
88e790a4 PG |
1330 | static void tegra30_init_one_clock(struct clk *c) |
1331 | { | |
92fe58f0 PG |
1332 | struct clk_tegra *clk = to_clk_tegra(c->hw); |
1333 | __clk_init(NULL, c); | |
1334 | INIT_LIST_HEAD(&clk->shared_bus_list); | |
1335 | if (!clk->lookup.dev_id && !clk->lookup.con_id) | |
1336 | clk->lookup.con_id = c->name; | |
1337 | clk->lookup.clk = c; | |
1338 | clkdev_add(&clk->lookup); | |
1339 | tegra_clk_add(c); | |
88e790a4 PG |
1340 | } |
1341 | ||
1342 | void __init tegra30_init_clocks(void) | |
1343 | { | |
1344 | int i; | |
1345 | struct clk *c; | |
1346 | ||
1347 | for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) | |
1348 | tegra30_init_one_clock(tegra_ptr_clks[i]); | |
1349 | ||
1350 | for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) | |
92fe58f0 | 1351 | tegra30_init_one_clock(tegra_list_clks[i]); |
88e790a4 PG |
1352 | |
1353 | for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { | |
1354 | c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); | |
1355 | if (!c) { | |
1356 | pr_err("%s: Unknown duplicate clock %s\n", __func__, | |
1357 | tegra_clk_duplicates[i].name); | |
1358 | continue; | |
1359 | } | |
1360 | ||
1361 | tegra_clk_duplicates[i].lookup.clk = c; | |
1362 | clkdev_add(&tegra_clk_duplicates[i].lookup); | |
1363 | } | |
1364 | ||
1365 | for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) | |
92fe58f0 | 1366 | tegra30_init_one_clock(tegra_sync_source_list[i]); |
88e790a4 | 1367 | for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) |
92fe58f0 | 1368 | tegra30_init_one_clock(tegra_clk_audio_list[i]); |
88e790a4 | 1369 | for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++) |
92fe58f0 | 1370 | tegra30_init_one_clock(tegra_clk_audio_2x_list[i]); |
88e790a4 | 1371 | |
88e790a4 | 1372 | for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) |
92fe58f0 | 1373 | tegra30_init_one_clock(tegra_clk_out_list[i]); |
88e790a4 | 1374 | } |