[deliverable/linux.git] / arch / arm / mach-tegra / timer.c

/*
 * arch/arch/mach-tegra/timer.c
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/err.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach/time.h>
#include <asm/smp_twd.h>
#include <asm/sched_clock.h>

#include <mach/irqs.h>

#include "board.h"
#include "clock.h"
#include "iomap.h"

#define RTC_SECONDS            0x08
#define RTC_SHADOW_SECONDS     0x0c
#define RTC_MILLISECONDS       0x10

#define TIMERUS_CNTR_1US 0x10
#define TIMERUS_USEC_CFG 0x14
#define TIMERUS_CNTR_FREEZE 0x4c

#define TIMER1_BASE 0x0
#define TIMER2_BASE 0x8
#define TIMER3_BASE 0x50
#define TIMER4_BASE 0x58

#define TIMER_PTV 0x0
#define TIMER_PCR 0x4

static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);

static struct timespec persistent_ts;
static u64 persistent_ms, last_persistent_ms;

#define timer_writel(value, reg) \
	__raw_writel(value, timer_reg_base + (reg))
#define timer_readl(reg) \
	__raw_readl(timer_reg_base + (reg))

static int tegra_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	u32 reg;

	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
	timer_writel(reg, TIMER3_BASE + TIMER_PTV);

	return 0;
}

static void tegra_timer_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 reg;

	timer_writel(0, TIMER3_BASE + TIMER_PTV);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		reg = 0xC0000000 | ((1000000/HZ)-1);
		timer_writel(reg, TIMER3_BASE + TIMER_PTV);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device tegra_clockevent = {
	.name		= "timer0",
	.rating		= 300,
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.set_next_event	= tegra_timer_set_next_event,
	.set_mode	= tegra_timer_set_mode,
};

static u32 notrace tegra_read_sched_clock(void)
{
	return timer_readl(TIMERUS_CNTR_1US);
}

/*
 * tegra_rtc_read - Reads the Tegra RTC registers
 * Care must be taken that this funciton is not called while the
 * tegra_rtc driver could be executing to avoid race conditions
 * on the RTC shadow register
 */
static u64 tegra_rtc_read_ms(void)
{
	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
	return (u64)s * MSEC_PER_SEC + ms;
}

/*
 * tegra_read_persistent_clock -  Return time from a persistent clock.
 *
 * Reads the time from a source which isn't disabled during PM, the
 * 32k sync timer.  Convert the cycles elapsed since last read into
 * nsecs and adds to a monotonically increasing timespec.
 * Care must be taken that this funciton is not called while the
 * tegra_rtc driver could be executing to avoid race conditions
 * on the RTC shadow register
 */
static void tegra_read_persistent_clock(struct timespec *ts)
{
	u64 delta;
	struct timespec *tsp = &persistent_ts;

	last_persistent_ms = persistent_ms;
	persistent_ms = tegra_rtc_read_ms();
	delta = persistent_ms - last_persistent_ms;

	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
	*ts = *tsp;
}

static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction tegra_timer_irq = {
	.name		= "timer0",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
	.handler	= tegra_timer_interrupt,
	.dev_id		= &tegra_clockevent,
	.irq		= INT_TMR3,
};

#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
			      TEGRA_ARM_PERIF_BASE + 0x600,
			      IRQ_LOCALTIMER);

static void __init tegra_twd_init(void)
{
	int err = twd_local_timer_register(&twd_local_timer);
	if (err)
		pr_err("twd_local_timer_register failed %d\n", err);
}
#else
#define tegra_twd_init()	do {} while(0)
#endif

static void __init tegra_init_timer(void)
{
	struct clk *clk;
	unsigned long rate;
	int ret;

	clk = clk_get_sys("timer", NULL);
	if (IS_ERR(clk)) {
		pr_warn("Unable to get timer clock."
			" Assuming 12Mhz input clock.\n");
		rate = 12000000;
	} else {
		clk_prepare_enable(clk);
		rate = clk_get_rate(clk);
	}

	/*
	 * rtc registers are used by read_persistent_clock, keep the rtc clock
	 * enabled
	 */
	clk = clk_get_sys("rtc-tegra", NULL);
	if (IS_ERR(clk))
		pr_warn("Unable to get rtc-tegra clock\n");
	else
		clk_prepare_enable(clk);

	switch (rate) {
	case 12000000:
		timer_writel(0x000b, TIMERUS_USEC_CFG);
		break;
	case 13000000:
		timer_writel(0x000c, TIMERUS_USEC_CFG);
		break;
	case 19200000:
		timer_writel(0x045f, TIMERUS_USEC_CFG);
		break;
	case 26000000:
		timer_writel(0x0019, TIMERUS_USEC_CFG);
		break;
	default:
		WARN(1, "Unknown clock rate");
	}

	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);

	if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
		"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
		printk(KERN_ERR "Failed to register clocksource\n");
		BUG();
	}

	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
	if (ret) {
		printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
		BUG();
	}

	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
	tegra_clockevent.max_delta_ns =
		clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
	tegra_clockevent.min_delta_ns =
		clockevent_delta2ns(0x1, &tegra_clockevent);
	tegra_clockevent.cpumask = cpu_all_mask;
	tegra_clockevent.irq = tegra_timer_irq.irq;
	clockevents_register_device(&tegra_clockevent);
	tegra_twd_init();
	register_persistent_clock(NULL, tegra_read_persistent_clock);
}

struct sys_timer tegra_sys_timer = {
	.init = tegra_init_timer,
};

#ifdef CONFIG_PM
static u32 usec_config;

void tegra_timer_suspend(void)
{
	usec_config = timer_readl(TIMERUS_USEC_CFG);
}

void tegra_timer_resume(void)
{
	timer_writel(usec_config, TIMERUS_USEC_CFG);
}
#endif
Commit	Line	Data
2d5cd9a3 CC	1	/*
	2	* arch/arch/mach-tegra/timer.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Colin Cross <ccross@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
62248ae8	21	#include <linux/err.h>
2d5cd9a3 CC	22	#include <linux/time.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
	25	#include <linux/clockchips.h>
	26	#include <linux/clocksource.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
2d5cd9a3	29
2d5cd9a3	30	#include <asm/mach/time.h>
1fcf3a6e	31	#include <asm/smp_twd.h>
e3f4c0ab	32	#include <asm/sched_clock.h>
2d5cd9a3	33
2d5cd9a3 CC	34	#include <mach/irqs.h>
	35
	36	#include "board.h"
	37	#include "clock.h"
2be39c07	38	#include "iomap.h"
2d5cd9a3	39
09361785 CC	40	#define RTC_SECONDS 0x08
	41	#define RTC_SHADOW_SECONDS 0x0c
	42	#define RTC_MILLISECONDS 0x10
	43
2d5cd9a3 CC	44	#define TIMERUS_CNTR_1US 0x10
	45	#define TIMERUS_USEC_CFG 0x14
	46	#define TIMERUS_CNTR_FREEZE 0x4c
	47
	48	#define TIMER1_BASE 0x0
	49	#define TIMER2_BASE 0x8
	50	#define TIMER3_BASE 0x50
	51	#define TIMER4_BASE 0x58
	52
	53	#define TIMER_PTV 0x0
	54	#define TIMER_PCR 0x4
	55
2d5cd9a3	56	static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
09361785 CC	57	static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
	58
	59	static struct timespec persistent_ts;
	60	static u64 persistent_ms, last_persistent_ms;
2d5cd9a3 CC	61
2d5cd9a3 CC	62	#define timer_writel(value, reg) \
75d71166	63	__raw_writel(value, timer_reg_base + (reg))
2d5cd9a3	64	#define timer_readl(reg) \
75d71166	65	__raw_readl(timer_reg_base + (reg))
2d5cd9a3 CC	66
	67	static int tegra_timer_set_next_event(unsigned long cycles,
	68	struct clock_event_device *evt)
	69	{
	70	u32 reg;
	71
	72	reg = 0x80000000 \| ((cycles > 1) ? (cycles-1) : 0);
	73	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
	74
	75	return 0;
	76	}
	77
	78	static void tegra_timer_set_mode(enum clock_event_mode mode,
	79	struct clock_event_device *evt)
	80	{
	81	u32 reg;
	82
	83	timer_writel(0, TIMER3_BASE + TIMER_PTV);
	84
	85	switch (mode) {
	86	case CLOCK_EVT_MODE_PERIODIC:
	87	reg = 0xC0000000 \| ((1000000/HZ)-1);
	88	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
	89	break;
	90	case CLOCK_EVT_MODE_ONESHOT:
	91	break;
	92	case CLOCK_EVT_MODE_UNUSED:
	93	case CLOCK_EVT_MODE_SHUTDOWN:
	94	case CLOCK_EVT_MODE_RESUME:
	95	break;
	96	}
	97	}
	98
2d5cd9a3 CC	99	static struct clock_event_device tegra_clockevent = {
	100	.name = "timer0",
	101	.rating = 300,
	102	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
	103	.set_next_event = tegra_timer_set_next_event,
	104	.set_mode = tegra_timer_set_mode,
	105	};
	106
2f0778af	107	static u32 notrace tegra_read_sched_clock(void)
e3f4c0ab	108	{
2f0778af	109	return timer_readl(TIMERUS_CNTR_1US);
2d5cd9a3 CC	110	}
2d5cd9a3 CC	111
09361785 CC	112	/*
	113	* tegra_rtc_read - Reads the Tegra RTC registers
	114	* Care must be taken that this funciton is not called while the
	115	* tegra_rtc driver could be executing to avoid race conditions
	116	* on the RTC shadow register
	117	*/
b28fba2a	118	static u64 tegra_rtc_read_ms(void)
09361785 CC	119	{
	120	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
	121	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
	122	return (u64)s * MSEC_PER_SEC + ms;
	123	}
	124
	125	/*
bd0493ea	126	* tegra_read_persistent_clock - Return time from a persistent clock.
09361785 CC	127	*
	128	* Reads the time from a source which isn't disabled during PM, the
	129	* 32k sync timer. Convert the cycles elapsed since last read into
	130	* nsecs and adds to a monotonically increasing timespec.
	131	* Care must be taken that this funciton is not called while the
	132	* tegra_rtc driver could be executing to avoid race conditions
	133	* on the RTC shadow register
	134	*/
bd0493ea	135	static void tegra_read_persistent_clock(struct timespec *ts)
09361785 CC	136	{
	137	u64 delta;
	138	struct timespec *tsp = &persistent_ts;
	139
	140	last_persistent_ms = persistent_ms;
	141	persistent_ms = tegra_rtc_read_ms();
	142	delta = persistent_ms - last_persistent_ms;
	143
	144	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
	145	ts = tsp;
	146	}
	147
2d5cd9a3 CC	148	static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
	149	{
	150	struct clock_event_device evt = (struct clock_event_device )dev_id;
	151	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
	152	evt->event_handler(evt);
	153	return IRQ_HANDLED;
	154	}
	155
	156	static struct irqaction tegra_timer_irq = {
	157	.name = "timer0",
	158	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_TRIGGER_HIGH,
	159	.handler = tegra_timer_interrupt,
	160	.dev_id = &tegra_clockevent,
	161	.irq = INT_TMR3,
	162	};
	163
1fcf3a6e MZ	164	#ifdef CONFIG_HAVE_ARM_TWD
	165	static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
	166	TEGRA_ARM_PERIF_BASE + 0x600,
	167	IRQ_LOCALTIMER);
	168
	169	static void __init tegra_twd_init(void)
	170	{
	171	int err = twd_local_timer_register(&twd_local_timer);
	172	if (err)
	173	pr_err("twd_local_timer_register failed %d\n", err);
	174	}
	175	#else
	176	#define tegra_twd_init() do {} while(0)
	177	#endif
	178
2d5cd9a3 CC	179	static void __init tegra_init_timer(void)
2d5cd9a3 CC	180	{
62248ae8	181	struct clk *clk;
8e4fab2c	182	unsigned long rate;
2d5cd9a3 CC	183	int ret;
2d5cd9a3 CC	184
62248ae8	185	clk = clk_get_sys("timer", NULL);
8e4fab2c PDS	186	if (IS_ERR(clk)) {
	187	pr_warn("Unable to get timer clock."
	188	" Assuming 12Mhz input clock.\n");
	189	rate = 12000000;
	190	} else {
6a5278d0	191	clk_prepare_enable(clk);
8e4fab2c PDS	192	rate = clk_get_rate(clk);
8e4fab2c PDS	193	}
62248ae8 CC	194
	195	/*
	196	* rtc registers are used by read_persistent_clock, keep the rtc clock
	197	* enabled
	198	*/
	199	clk = clk_get_sys("rtc-tegra", NULL);
2d85b5d8 PDS	200	if (IS_ERR(clk))
	201	pr_warn("Unable to get rtc-tegra clock\n");
	202	else
6a5278d0	203	clk_prepare_enable(clk);
62248ae8	204
2d5cd9a3 CC	205	switch (rate) {
	206	case 12000000:
	207	timer_writel(0x000b, TIMERUS_USEC_CFG);
	208	break;
	209	case 13000000:
	210	timer_writel(0x000c, TIMERUS_USEC_CFG);
	211	break;
	212	case 19200000:
	213	timer_writel(0x045f, TIMERUS_USEC_CFG);
	214	break;
	215	case 26000000:
	216	timer_writel(0x0019, TIMERUS_USEC_CFG);
	217	break;
	218	default:
	219	WARN(1, "Unknown clock rate");
	220	}
	221
2f0778af	222	setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
e3f4c0ab	223
234b6ced RK	224	if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
234b6ced RK	225	"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
2d5cd9a3 CC	226	printk(KERN_ERR "Failed to register clocksource\n");
	227	BUG();
	228	}
	229
	230	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
	231	if (ret) {
	232	printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
	233	BUG();
	234	}
	235
	236	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
	237	tegra_clockevent.max_delta_ns =
	238	clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
	239	tegra_clockevent.min_delta_ns =
	240	clockevent_delta2ns(0x1, &tegra_clockevent);
	241	tegra_clockevent.cpumask = cpu_all_mask;
	242	tegra_clockevent.irq = tegra_timer_irq.irq;
	243	clockevents_register_device(&tegra_clockevent);
1fcf3a6e	244	tegra_twd_init();
bd0493ea	245	register_persistent_clock(NULL, tegra_read_persistent_clock);
2d5cd9a3 CC	246	}
2d5cd9a3 CC	247
f2ef412d	248	struct sys_timer tegra_sys_timer = {
2d5cd9a3 CC	249	.init = tegra_init_timer,
2d5cd9a3 CC	250	};
09361785 CC	251
	252	#ifdef CONFIG_PM
	253	static u32 usec_config;
	254
	255	void tegra_timer_suspend(void)
	256	{
	257	usec_config = timer_readl(TIMERUS_USEC_CFG);
	258	}
	259
	260	void tegra_timer_resume(void)
	261	{
	262	timer_writel(usec_config, TIMERUS_USEC_CFG);
	263	}
	264	#endif