[deliverable/linux.git] / arch / arm / mach-u300 / timer.c

/*
 *
 * arch/arm/mach-u300/timer.c
 *
 *
 * Copyright (C) 2007-2009 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * Timer COH 901 328, runs the OS timer interrupt.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
 */
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

/* Generic stuff */
#include <asm/mach/map.h>
#include <asm/mach/time.h>

/*
 * APP side special timer registers
 * This timer contains four timers which can fire an interrupt each.
 * OS (operating system) timer @ 32768 Hz
 * DD (device driver) timer @ 1 kHz
 * GP1 (general purpose 1) timer @ 1MHz
 * GP2 (general purpose 2) timer @ 1MHz
 */

/* Reset OS Timer 32bit (-/W) */
#define U300_TIMER_APP_ROST					(0x0000)
#define U300_TIMER_APP_ROST_TIMER_RESET				(0x00000000)
/* Enable OS Timer 32bit (-/W) */
#define U300_TIMER_APP_EOST					(0x0004)
#define U300_TIMER_APP_EOST_TIMER_ENABLE			(0x00000000)
/* Disable OS Timer 32bit (-/W) */
#define U300_TIMER_APP_DOST					(0x0008)
#define U300_TIMER_APP_DOST_TIMER_DISABLE			(0x00000000)
/* OS Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SOSTM					(0x000c)
#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT			(0x00000001)
/* OS Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_OSTS					(0x0010)
#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_OSTS_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_OSTS_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND			(0x00000080)
/* OS Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_OSTCC					(0x0014)
/* OS Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_OSTTC					(0x0018)
/* OS Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_OSTIE					(0x001c)
#define U300_TIMER_APP_OSTIE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_OSTIE_IRQ_ENABLE				(0x00000001)
/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_OSTIA					(0x0020)
#define U300_TIMER_APP_OSTIA_IRQ_ACK				(0x00000080)

/* Reset DD Timer 32bit (-/W) */
#define U300_TIMER_APP_RDDT					(0x0040)
#define U300_TIMER_APP_RDDT_TIMER_RESET				(0x00000000)
/* Enable DD Timer 32bit (-/W) */
#define U300_TIMER_APP_EDDT					(0x0044)
#define U300_TIMER_APP_EDDT_TIMER_ENABLE			(0x00000000)
/* Disable DD Timer 32bit (-/W) */
#define U300_TIMER_APP_DDDT					(0x0048)
#define U300_TIMER_APP_DDDT_TIMER_DISABLE			(0x00000000)
/* DD Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SDDTM					(0x004c)
#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT			(0x00000001)
/* DD Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_DDTS					(0x0050)
#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_DDTS_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_DDTS_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND			(0x00000080)
/* DD Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_DDTCC					(0x0054)
/* DD Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_DDTTC					(0x0058)
/* DD Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_DDTIE					(0x005c)
#define U300_TIMER_APP_DDTIE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_DDTIE_IRQ_ENABLE				(0x00000001)
/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_DDTIA					(0x0060)
#define U300_TIMER_APP_DDTIA_IRQ_ACK				(0x00000080)

/* Reset GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_RGPT1					(0x0080)
#define U300_TIMER_APP_RGPT1_TIMER_RESET			(0x00000000)
/* Enable GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_EGPT1					(0x0084)
#define U300_TIMER_APP_EGPT1_TIMER_ENABLE			(0x00000000)
/* Disable GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_DGPT1					(0x0088)
#define U300_TIMER_APP_DGPT1_TIMER_DISABLE			(0x00000000)
/* GP1 Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SGPT1M					(0x008c)
#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT			(0x00000001)
/* GP1 Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_GPT1S					(0x0090)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_GPT1S_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_GPT1S_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND			(0x00000080)
/* GP1 Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_GPT1CC					(0x0094)
/* GP1 Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_GPT1TC					(0x0098)
/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_GPT1IE					(0x009c)
#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE			(0x00000001)
/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_GPT1IA					(0x00a0)
#define U300_TIMER_APP_GPT1IA_IRQ_ACK				(0x00000080)

/* Reset GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_RGPT2					(0x00c0)
#define U300_TIMER_APP_RGPT2_TIMER_RESET			(0x00000000)
/* Enable GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_EGPT2					(0x00c4)
#define U300_TIMER_APP_EGPT2_TIMER_ENABLE			(0x00000000)
/* Disable GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_DGPT2					(0x00c8)
#define U300_TIMER_APP_DGPT2_TIMER_DISABLE			(0x00000000)
/* GP2 Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SGPT2M					(0x00cc)
#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT			(0x00000001)
/* GP2 Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_GPT2S					(0x00d0)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK			(0x0000000F)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE			(0x00000001)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE			(0x00000002)
#define U300_TIMER_APP_GPT2S_ENABLE_IND				(0x00000010)
#define U300_TIMER_APP_GPT2S_MODE_MASK				(0x00000020)
#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS			(0x00000000)
#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT			(0x00000020)
#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND			(0x00000040)
#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND			(0x00000080)
/* GP2 Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_GPT2CC					(0x00d4)
/* GP2 Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_GPT2TC					(0x00d8)
/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_GPT2IE					(0x00dc)
#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE			(0x00000000)
#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE			(0x00000001)
/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_GPT2IA					(0x00e0)
#define U300_TIMER_APP_GPT2IA_IRQ_ACK				(0x00000080)

/* Clock request control register - all four timers */
#define U300_TIMER_APP_CRC					(0x100)
#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE			(0x00000001)

static void __iomem *u300_timer_base;

struct u300_clockevent_data {
	struct clock_event_device cevd;
	unsigned ticks_per_jiffy;
};

/*
 * The u300_set_mode() function is always called first, if we
 * have oneshot timer active, the oneshot scheduling function
 * u300_set_next_event() is called immediately after.
 */
static void u300_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt)
{
	struct u300_clockevent_data *cevdata =
		container_of(evt, struct u300_clockevent_data, cevd);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* Disable interrupts on GPT1 */
		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Disable GP1 while we're reprogramming it. */
		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
		       u300_timer_base + U300_TIMER_APP_DGPT1);
		/*
		 * Set the periodic mode to a certain number of ticks per
		 * jiffy.
		 */
		writel(cevdata->ticks_per_jiffy,
		       u300_timer_base + U300_TIMER_APP_GPT1TC);
		/*
		 * Set continuous mode, so the timer keeps triggering
		 * interrupts.
		 */
		writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
		       u300_timer_base + U300_TIMER_APP_SGPT1M);
		/* Enable timer interrupts */
		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Then enable the OS timer again */
		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
		       u300_timer_base + U300_TIMER_APP_EGPT1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* Just break; here? */
		/*
		 * The actual event will be programmed by the next event hook,
		 * so we just set a dummy value somewhere at the end of the
		 * universe here.
		 */
		/* Disable interrupts on GPT1 */
		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Disable GP1 while we're reprogramming it. */
		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
		       u300_timer_base + U300_TIMER_APP_DGPT1);
		/*
		 * Expire far in the future, u300_set_next_event() will be
		 * called soon...
		 */
		writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
		/* We run one shot per tick here! */
		writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
		       u300_timer_base + U300_TIMER_APP_SGPT1M);
		/* Enable interrupts for this timer */
		writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Enable timer */
		writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
		       u300_timer_base + U300_TIMER_APP_EGPT1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		/* Disable interrupts on GP1 */
		writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
		       u300_timer_base + U300_TIMER_APP_GPT1IE);
		/* Disable GP1 */
		writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
		       u300_timer_base + U300_TIMER_APP_DGPT1);
		break;
	case CLOCK_EVT_MODE_RESUME:
		/* Ignore this call */
		break;
	}
}

/*
 * The app timer in one shot mode obviously has to be reprogrammed
 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 * the interrupt disable + timer disable commands with a reset command,
 * it will fail miserably. Apparently (and I found this the hard way)
 * the timer is very sensitive to the instruction order, though you don't
 * get that impression from the data sheet.
 */
static int u300_set_next_event(unsigned long cycles,
			       struct clock_event_device *evt)

{
	/* Disable interrupts on GPT1 */
	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
	       u300_timer_base + U300_TIMER_APP_GPT1IE);
	/* Disable GP1 while we're reprogramming it. */
	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
	       u300_timer_base + U300_TIMER_APP_DGPT1);
	/* Reset the General Purpose timer 1. */
	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
	       u300_timer_base + U300_TIMER_APP_RGPT1);
	/* IRQ in n * cycles */
	writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
	/*
	 * We run one shot per tick here! (This is necessary to reconfigure,
	 * the timer will tilt if you don't!)
	 */
	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
	       u300_timer_base + U300_TIMER_APP_SGPT1M);
	/* Enable timer interrupts */
	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
	       u300_timer_base + U300_TIMER_APP_GPT1IE);
	/* Then enable the OS timer again */
	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
	       u300_timer_base + U300_TIMER_APP_EGPT1);
	return 0;
}

static struct u300_clockevent_data u300_clockevent_data = {
	/* Use general purpose timer 1 as clock event */
	.cevd = {
		.name		= "GPT1",
		/* Reasonably fast and accurate clock event */
		.rating		= 300,
		.features	= CLOCK_EVT_FEAT_PERIODIC |
			CLOCK_EVT_FEAT_ONESHOT,
		.set_next_event	= u300_set_next_event,
		.set_mode	= u300_set_mode,
	},
};

/* Clock event timer interrupt handler */
static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &u300_clockevent_data.cevd;
	/* ACK/Clear timer IRQ for the APP GPT1 Timer */

	writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
		u300_timer_base + U300_TIMER_APP_GPT1IA);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction u300_timer_irq = {
	.name		= "U300 Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= u300_timer_interrupt,
};

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by OMAP implementation.)
 */

static u64 notrace u300_read_sched_clock(void)
{
	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
}

static unsigned long u300_read_current_timer(void)
{
	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
}

static struct delay_timer u300_delay_timer;

/*
 * This sets up the system timers, clock source and clock event.
 */
static void __init u300_timer_init_of(struct device_node *np)
{
	unsigned int irq;
	struct clk *clk;
	unsigned long rate;

	u300_timer_base = of_iomap(np, 0);
	if (!u300_timer_base)
		panic("could not ioremap system timer\n");

	/* Get the IRQ for the GP1 timer */
	irq = irq_of_parse_and_map(np, 2);
	if (!irq)
		panic("no IRQ for system timer\n");

	pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);

	/* Clock the interrupt controller */
	clk = of_clk_get(np, 0);
	BUG_ON(IS_ERR(clk));
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);

	sched_clock_register(u300_read_sched_clock, 32, rate);

	u300_delay_timer.read_current_timer = &u300_read_current_timer;
	u300_delay_timer.freq = rate;
	register_current_timer_delay(&u300_delay_timer);

	/*
	 * Disable the "OS" and "DD" timers - these are designed for Symbian!
	 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
	 */
	writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
		u300_timer_base + U300_TIMER_APP_CRC);
	writel(U300_TIMER_APP_ROST_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_ROST);
	writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
		u300_timer_base + U300_TIMER_APP_DOST);
	writel(U300_TIMER_APP_RDDT_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_RDDT);
	writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
		u300_timer_base + U300_TIMER_APP_DDDT);

	/* Reset the General Purpose timer 1. */
	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_RGPT1);

	/* Set up the IRQ handler */
	setup_irq(irq, &u300_timer_irq);

	/* Reset the General Purpose timer 2 */
	writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
		u300_timer_base + U300_TIMER_APP_RGPT2);
	/* Set this timer to run around forever */
	writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
	/* Set continuous mode so it wraps around */
	writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
	       u300_timer_base + U300_TIMER_APP_SGPT2M);
	/* Disable timer interrupts */
	writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
		u300_timer_base + U300_TIMER_APP_GPT2IE);
	/* Then enable the GP2 timer to use as a free running us counter */
	writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
		u300_timer_base + U300_TIMER_APP_EGPT2);

	/* Use general purpose timer 2 as clock source */
	if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
			"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
		pr_err("timer: failed to initialize U300 clock source\n");

	/* Configure and register the clockevent */
	clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
					1, 0xffffffff);

	/*
	 * TODO: init and register the rest of the timers too, they can be
	 * used by hrtimers!
	 */
}

CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
		       u300_timer_init_of);
Commit	Line	Data
bb3cee2b LW	1	/*
	2	*
	3	* arch/arm/mach-u300/timer.c
	4	*
	5	*
	6	* Copyright (C) 2007-2009 ST-Ericsson AB
	7	* License terms: GNU General Public License (GPL) version 2
	8	* Timer COH 901 328, runs the OS timer interrupt.
	9	* Author: Linus Walleij <linus.walleij@stericsson.com>
	10	*/
	11	#include <linux/interrupt.h>
	12	#include <linux/time.h>
	13	#include <linux/timex.h>
	14	#include <linux/clockchips.h>
	15	#include <linux/clocksource.h>
	16	#include <linux/types.h>
	17	#include <linux/io.h>
b7276b23 LW	18	#include <linux/clk.h>
b7276b23 LW	19	#include <linux/err.h>
a4fe292f	20	#include <linux/irq.h>
3c96d8ea	21	#include <linux/delay.h>
5a5056cc LW	22	#include <linux/of_address.h>
5a5056cc LW	23	#include <linux/of_irq.h>
38ff87f7	24	#include <linux/sched_clock.h>
bb3cee2b	25
bb3cee2b LW	26	/* Generic stuff */
	27	#include <asm/mach/map.h>
	28	#include <asm/mach/time.h>
bb3cee2b	29
bb3cee2b LW	30	/*
	31	* APP side special timer registers
	32	* This timer contains four timers which can fire an interrupt each.
	33	* OS (operating system) timer @ 32768 Hz
	34	* DD (device driver) timer @ 1 kHz
	35	* GP1 (general purpose 1) timer @ 1MHz
	36	* GP2 (general purpose 2) timer @ 1MHz
	37	*/
	38
	39	/* Reset OS Timer 32bit (-/W) */
	40	#define U300_TIMER_APP_ROST (0x0000)
	41	#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
	42	/* Enable OS Timer 32bit (-/W) */
	43	#define U300_TIMER_APP_EOST (0x0004)
	44	#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
	45	/* Disable OS Timer 32bit (-/W) */
	46	#define U300_TIMER_APP_DOST (0x0008)
	47	#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
	48	/* OS Timer Mode Register 32bit (-/W) */
	49	#define U300_TIMER_APP_SOSTM (0x000c)
	50	#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
	51	#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
	52	/* OS Timer Status Register 32bit (R/-) */
	53	#define U300_TIMER_APP_OSTS (0x0010)
	54	#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
	55	#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
	56	#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
	57	#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
	58	#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
	59	#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
	60	#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
	61	#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
	62	#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
	63	/* OS Timer Current Count Register 32bit (R/-) */
	64	#define U300_TIMER_APP_OSTCC (0x0014)
	65	/* OS Timer Terminal Count Register 32bit (R/W) */
	66	#define U300_TIMER_APP_OSTTC (0x0018)
	67	/* OS Timer Interrupt Enable Register 32bit (-/W) */
	68	#define U300_TIMER_APP_OSTIE (0x001c)
	69	#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
	70	#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
	71	/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
	72	#define U300_TIMER_APP_OSTIA (0x0020)
	73	#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
	74
	75	/* Reset DD Timer 32bit (-/W) */
	76	#define U300_TIMER_APP_RDDT (0x0040)
	77	#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
	78	/* Enable DD Timer 32bit (-/W) */
	79	#define U300_TIMER_APP_EDDT (0x0044)
	80	#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
	81	/* Disable DD Timer 32bit (-/W) */
	82	#define U300_TIMER_APP_DDDT (0x0048)
	83	#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
	84	/* DD Timer Mode Register 32bit (-/W) */
	85	#define U300_TIMER_APP_SDDTM (0x004c)
	86	#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
	87	#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
	88	/* DD Timer Status Register 32bit (R/-) */
	89	#define U300_TIMER_APP_DDTS (0x0050)
	90	#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
	91	#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
	92	#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
	93	#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
94	#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
95	#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
96	#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
97	#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
98	#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
99	/* DD Timer Current Count Register 32bit (R/-) */
100	#define U300_TIMER_APP_DDTCC (0x0054)
101	/* DD Timer Terminal Count Register 32bit (R/W) */
102	#define U300_TIMER_APP_DDTTC (0x0058)
103	/* DD Timer Interrupt Enable Register 32bit (-/W) */
104	#define U300_TIMER_APP_DDTIE (0x005c)
105	#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
106	#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
107	/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
108	#define U300_TIMER_APP_DDTIA (0x0060)
109	#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
110
111	/* Reset GP1 Timer 32bit (-/W) */
112	#define U300_TIMER_APP_RGPT1 (0x0080)
113	#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
114	/* Enable GP1 Timer 32bit (-/W) */
115	#define U300_TIMER_APP_EGPT1 (0x0084)
116	#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
117	/* Disable GP1 Timer 32bit (-/W) */
118	#define U300_TIMER_APP_DGPT1 (0x0088)
119	#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
120	/* GP1 Timer Mode Register 32bit (-/W) */
121	#define U300_TIMER_APP_SGPT1M (0x008c)
122	#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
123	#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
124	/* GP1 Timer Status Register 32bit (R/-) */
125	#define U300_TIMER_APP_GPT1S (0x0090)
126	#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
127	#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
128	#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
129	#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
130	#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
131	#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
132	#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
133	#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
134	#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
135	/* GP1 Timer Current Count Register 32bit (R/-) */
136	#define U300_TIMER_APP_GPT1CC (0x0094)
137	/* GP1 Timer Terminal Count Register 32bit (R/W) */
138	#define U300_TIMER_APP_GPT1TC (0x0098)
139	/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
140	#define U300_TIMER_APP_GPT1IE (0x009c)
141	#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
142	#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
143	/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
144	#define U300_TIMER_APP_GPT1IA (0x00a0)
145	#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
146
147	/* Reset GP2 Timer 32bit (-/W) */
148	#define U300_TIMER_APP_RGPT2 (0x00c0)
149	#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
150	/* Enable GP2 Timer 32bit (-/W) */
151	#define U300_TIMER_APP_EGPT2 (0x00c4)
152	#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
153	/* Disable GP2 Timer 32bit (-/W) */
154	#define U300_TIMER_APP_DGPT2 (0x00c8)
155	#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
156	/* GP2 Timer Mode Register 32bit (-/W) */
157	#define U300_TIMER_APP_SGPT2M (0x00cc)
158	#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
159	#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
160	/* GP2 Timer Status Register 32bit (R/-) */
161	#define U300_TIMER_APP_GPT2S (0x00d0)
162	#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
163	#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
164	#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
165	#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
166	#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
167	#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
168	#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
169	#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
170	#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
171	/* GP2 Timer Current Count Register 32bit (R/-) */
172	#define U300_TIMER_APP_GPT2CC (0x00d4)
173	/* GP2 Timer Terminal Count Register 32bit (R/W) */
174	#define U300_TIMER_APP_GPT2TC (0x00d8)
175	/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
176	#define U300_TIMER_APP_GPT2IE (0x00dc)
177	#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
178	#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
179	/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
180	#define U300_TIMER_APP_GPT2IA (0x00e0)
181	#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
182
183	/* Clock request control register - all four timers */
184	#define U300_TIMER_APP_CRC (0x100)
185	#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
186
5a5056cc LW	187	static void __iomem *u300_timer_base;
5a5056cc LW	188
6a79799d UKK	189	struct u300_clockevent_data {
	190	struct clock_event_device cevd;
	191	unsigned ticks_per_jiffy;
	192	};
	193
bb3cee2b LW	194	/*
	195	* The u300_set_mode() function is always called first, if we
	196	* have oneshot timer active, the oneshot scheduling function
	197	* u300_set_next_event() is called immediately after.
	198	*/
	199	static void u300_set_mode(enum clock_event_mode mode,
	200	struct clock_event_device *evt)
	201	{
6a79799d UKK	202	struct u300_clockevent_data *cevdata =
	203	container_of(evt, struct u300_clockevent_data, cevd);
	204
bb3cee2b LW	205	switch (mode) {
	206	case CLOCK_EVT_MODE_PERIODIC:
	207	/* Disable interrupts on GPT1 */
	208	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	209	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	210	/* Disable GP1 while we're reprogramming it. */
bb3cee2b LW	211	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	212	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	213	/*
	214	* Set the periodic mode to a certain number of ticks per
	215	* jiffy.
	216	*/
6a79799d	217	writel(cevdata->ticks_per_jiffy,
5a5056cc	218	u300_timer_base + U300_TIMER_APP_GPT1TC);
bb3cee2b LW	219	/*
	220	* Set continuous mode, so the timer keeps triggering
	221	* interrupts.
	222	*/
	223	writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
5a5056cc	224	u300_timer_base + U300_TIMER_APP_SGPT1M);
bb3cee2b LW	225	/* Enable timer interrupts */
bb3cee2b LW	226	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
5a5056cc	227	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	228	/* Then enable the OS timer again */
bb3cee2b LW	229	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
5a5056cc	230	u300_timer_base + U300_TIMER_APP_EGPT1);
bb3cee2b LW	231	break;
	232	case CLOCK_EVT_MODE_ONESHOT:
	233	/* Just break; here? */
	234	/*
	235	* The actual event will be programmed by the next event hook,
	236	* so we just set a dummy value somewhere at the end of the
	237	* universe here.
	238	*/
	239	/* Disable interrupts on GPT1 */
	240	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	241	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	242	/* Disable GP1 while we're reprogramming it. */
bb3cee2b LW	243	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	244	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	245	/*
	246	* Expire far in the future, u300_set_next_event() will be
	247	* called soon...
	248	*/
5a5056cc	249	writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
bb3cee2b LW	250	/* We run one shot per tick here! */
bb3cee2b LW	251	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
5a5056cc	252	u300_timer_base + U300_TIMER_APP_SGPT1M);
bb3cee2b LW	253	/* Enable interrupts for this timer */
bb3cee2b LW	254	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
5a5056cc	255	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	256	/* Enable timer */
bb3cee2b LW	257	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
5a5056cc	258	u300_timer_base + U300_TIMER_APP_EGPT1);
bb3cee2b LW	259	break;
	260	case CLOCK_EVT_MODE_UNUSED:
	261	case CLOCK_EVT_MODE_SHUTDOWN:
	262	/* Disable interrupts on GP1 */
	263	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	264	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	265	/* Disable GP1 */
bb3cee2b LW	266	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	267	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	268	break;
	269	case CLOCK_EVT_MODE_RESUME:
	270	/* Ignore this call */
	271	break;
	272	}
	273	}
	274
	275	/*
	276	* The app timer in one shot mode obviously has to be reprogrammed
	277	* in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
	278	* the interrupt disable + timer disable commands with a reset command,
	279	* it will fail miserably. Apparently (and I found this the hard way)
	280	* the timer is very sensitive to the instruction order, though you don't
	281	* get that impression from the data sheet.
	282	*/
	283	static int u300_set_next_event(unsigned long cycles,
	284	struct clock_event_device *evt)
	285
	286	{
	287	/* Disable interrupts on GPT1 */
	288	writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
5a5056cc	289	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	290	/* Disable GP1 while we're reprogramming it. */
bb3cee2b LW	291	writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
5a5056cc	292	u300_timer_base + U300_TIMER_APP_DGPT1);
bb3cee2b LW	293	/* Reset the General Purpose timer 1. */
bb3cee2b LW	294	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
5a5056cc	295	u300_timer_base + U300_TIMER_APP_RGPT1);
bb3cee2b	296	/* IRQ in n * cycles */
5a5056cc	297	writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
bb3cee2b LW	298	/*
	299	* We run one shot per tick here! (This is necessary to reconfigure,
	300	* the timer will tilt if you don't!)
	301	*/
	302	writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
5a5056cc	303	u300_timer_base + U300_TIMER_APP_SGPT1M);
bb3cee2b LW	304	/* Enable timer interrupts */
bb3cee2b LW	305	writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
5a5056cc	306	u300_timer_base + U300_TIMER_APP_GPT1IE);
bb3cee2b LW	307	/* Then enable the OS timer again */
bb3cee2b LW	308	writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
5a5056cc	309	u300_timer_base + U300_TIMER_APP_EGPT1);
bb3cee2b LW	310	return 0;
	311	}
	312
6a79799d UKK	313	static struct u300_clockevent_data u300_clockevent_data = {
	314	/* Use general purpose timer 1 as clock event */
	315	.cevd = {
	316	.name = "GPT1",
	317	/* Reasonably fast and accurate clock event */
	318	.rating = 300,
	319	.features = CLOCK_EVT_FEAT_PERIODIC \|
	320	CLOCK_EVT_FEAT_ONESHOT,
	321	.set_next_event = u300_set_next_event,
	322	.set_mode = u300_set_mode,
	323	},
bb3cee2b LW	324	};
	325
	326	/* Clock event timer interrupt handler */
	327	static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
	328	{
6a79799d	329	struct clock_event_device *evt = &u300_clockevent_data.cevd;
bb3cee2b	330	/* ACK/Clear timer IRQ for the APP GPT1 Timer */
5a5056cc	331
bb3cee2b	332	writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
5a5056cc	333	u300_timer_base + U300_TIMER_APP_GPT1IA);
bb3cee2b LW	334	evt->event_handler(evt);
	335	return IRQ_HANDLED;
	336	}
	337
	338	static struct irqaction u300_timer_irq = {
cde21de1 LW	339	.name = "U300 Timer Tick",
	340	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	341	.handler = u300_timer_interrupt,
bb3cee2b LW	342	};
bb3cee2b LW	343
a2ca00ea LW	344	/*
	345	* Override the global weak sched_clock symbol with this
	346	* local implementation which uses the clocksource to get some
	347	* better resolution when scheduling the kernel. We accept that
	348	* this wraps around for now, since it is just a relative time
	349	* stamp. (Inspired by OMAP implementation.)
	350	*/
5c21b7ca	351
5994d01f	352	static u64 notrace u300_read_sched_clock(void)
a2ca00ea	353	{
5a5056cc	354	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
a2ca00ea LW	355	}
a2ca00ea LW	356
3c96d8ea LW	357	static unsigned long u300_read_current_timer(void)
3c96d8ea LW	358	{
5a5056cc	359	return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
3c96d8ea LW	360	}
	361
	362	static struct delay_timer u300_delay_timer;
bb3cee2b LW	363
	364	/*
	365	* This sets up the system timers, clock source and clock event.
	366	*/
75a7f3f1	367	static void __init u300_timer_init_of(struct device_node *np)
bb3cee2b	368	{
f7578496	369	unsigned int irq;
b7276b23	370	struct clk *clk;
3af8a8da	371	unsigned long rate;
b7276b23	372
75a7f3f1 LW	373	u300_timer_base = of_iomap(np, 0);
	374	if (!u300_timer_base)
	375	panic("could not ioremap system timer\n");
	376
	377	/* Get the IRQ for the GP1 timer */
f7578496 TR	378	irq = irq_of_parse_and_map(np, 2);
f7578496 TR	379	if (!irq)
75a7f3f1 LW	380	panic("no IRQ for system timer\n");
75a7f3f1 LW	381
f7578496	382	pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);
5a5056cc	383
b7276b23	384	/* Clock the interrupt controller */
bba5f2cc	385	clk = of_clk_get(np, 0);
b7276b23	386	BUG_ON(IS_ERR(clk));
50667d63	387	clk_prepare_enable(clk);
3af8a8da	388	rate = clk_get_rate(clk);
b7276b23	389
6a79799d UKK	390	u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
6a79799d UKK	391
5994d01f	392	sched_clock_register(u300_read_sched_clock, 32, rate);
5c21b7ca	393
3c96d8ea LW	394	u300_delay_timer.read_current_timer = &u300_read_current_timer;
	395	u300_delay_timer.freq = rate;
	396	register_current_timer_delay(&u300_delay_timer);
	397
bb3cee2b LW	398	/*
	399	* Disable the "OS" and "DD" timers - these are designed for Symbian!
	400	* Example usage in cnh1601578 cpu subsystem pd_timer_app.c
	401	*/
	402	writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
5a5056cc	403	u300_timer_base + U300_TIMER_APP_CRC);
bb3cee2b	404	writel(U300_TIMER_APP_ROST_TIMER_RESET,
5a5056cc	405	u300_timer_base + U300_TIMER_APP_ROST);
bb3cee2b	406	writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
5a5056cc	407	u300_timer_base + U300_TIMER_APP_DOST);
bb3cee2b	408	writel(U300_TIMER_APP_RDDT_TIMER_RESET,
5a5056cc	409	u300_timer_base + U300_TIMER_APP_RDDT);
bb3cee2b	410	writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
5a5056cc	411	u300_timer_base + U300_TIMER_APP_DDDT);
bb3cee2b LW	412
	413	/* Reset the General Purpose timer 1. */
	414	writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
5a5056cc	415	u300_timer_base + U300_TIMER_APP_RGPT1);
bb3cee2b LW	416
bb3cee2b LW	417	/* Set up the IRQ handler */
5a5056cc	418	setup_irq(irq, &u300_timer_irq);
bb3cee2b LW	419
	420	/* Reset the General Purpose timer 2 */
	421	writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
5a5056cc	422	u300_timer_base + U300_TIMER_APP_RGPT2);
bb3cee2b	423	/* Set this timer to run around forever */
5a5056cc	424	writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
bb3cee2b LW	425	/* Set continuous mode so it wraps around */
bb3cee2b LW	426	writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
5a5056cc	427	u300_timer_base + U300_TIMER_APP_SGPT2M);
bb3cee2b LW	428	/* Disable timer interrupts */
bb3cee2b LW	429	writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
5a5056cc	430	u300_timer_base + U300_TIMER_APP_GPT2IE);
bb3cee2b LW	431	/* Then enable the GP2 timer to use as a free running us counter */
bb3cee2b LW	432	writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
5a5056cc	433	u300_timer_base + U300_TIMER_APP_EGPT2);
bb3cee2b	434
234b6ced	435	/* Use general purpose timer 2 as clock source */
5a5056cc	436	if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
234b6ced	437	"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
9425032b	438	pr_err("timer: failed to initialize U300 clock source\n");
bb3cee2b	439
cde21de1	440	/* Configure and register the clockevent */
6a79799d	441	clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
cde21de1 LW	442	1, 0xffffffff);
cde21de1 LW	443
bb3cee2b LW	444	/*
	445	* TODO: init and register the rest of the timers too, they can be
	446	* used by hrtimers!
	447	*/
	448	}
5a5056cc	449
5a5056cc LW	450	CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
5a5056cc LW	451	u300_timer_init_of);