Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target...
[deliverable/linux.git] / arch / arm / mach-ux500 / cache-l2x0.c
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1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#include <linux/io.h>
f1949ea0 8#include <linux/of.h>
583ecab9 9#include <linux/of_address.h>
f1949ea0 10
458eef2f 11#include <asm/hardware/cache-l2x0.h>
7a4f2609 12
174e7796 13#include "db8500-regs.h"
7a4f2609 14#include "id.h"
458eef2f 15
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16static int __init ux500_l2x0_unlock(void)
17{
18 int i;
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19 struct device_node *np;
20 void __iomem *l2x0_base;
21
22 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
23 l2x0_base = of_iomap(np, 0);
24 of_node_put(np);
25 if (!l2x0_base)
26 return -ENODEV;
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27
28 /*
29 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
30 * apparently locks both caches before jumping to the kernel. The
31 * l2x0 core will not touch the unlock registers if the l2x0 is
32 * already enabled, so we do it right here instead. The PL310 has
33 * 8 sets of registers, one per possible CPU.
34 */
35 for (i = 0; i < 8; i++) {
36 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
37 i * L2X0_LOCKDOWN_STRIDE);
38 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
39 i * L2X0_LOCKDOWN_STRIDE);
40 }
583ecab9 41 iounmap(l2x0_base);
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42 return 0;
43}
44
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45static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
46{
47 /*
48 * We can't write to secure registers as we are in non-secure
49 * mode, until we have some SMI service available.
50 */
51}
52
a3849a4c 53static int __init ux500_l2x0_init(void)
458eef2f 54{
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55 /* Multiplatform guard */
56 if (!((cpu_is_u8500_family() || cpu_is_ux540_family())))
31c72abb 57 return -ENODEV;
458eef2f 58
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59 /* Unlock before init */
60 ux500_l2x0_unlock();
67161733 61 outer_cache.write_sec = ux500_l2c310_write_sec;
823e7546 62 l2x0_of_init(0, ~0);
458eef2f 63
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64 return 0;
65}
458eef2f 66early_initcall(ux500_l2x0_init);
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