Merge tag 'perf-urgent-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / mach-ux500 / cache-l2x0.c
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1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#include <linux/io.h>
f1949ea0 8#include <linux/of.h>
583ecab9 9#include <linux/of_address.h>
f1949ea0 10
f8130906 11#include <asm/outercache.h>
458eef2f 12#include <asm/hardware/cache-l2x0.h>
7a4f2609 13
174e7796 14#include "db8500-regs.h"
7a4f2609 15#include "id.h"
458eef2f 16
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17static int __init ux500_l2x0_unlock(void)
18{
19 int i;
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20 struct device_node *np;
21 void __iomem *l2x0_base;
22
23 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
24 l2x0_base = of_iomap(np, 0);
25 of_node_put(np);
26 if (!l2x0_base)
27 return -ENODEV;
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28
29 /*
30 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
31 * apparently locks both caches before jumping to the kernel. The
32 * l2x0 core will not touch the unlock registers if the l2x0 is
33 * already enabled, so we do it right here instead. The PL310 has
34 * 8 sets of registers, one per possible CPU.
35 */
36 for (i = 0; i < 8; i++) {
37 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
38 i * L2X0_LOCKDOWN_STRIDE);
39 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
40 i * L2X0_LOCKDOWN_STRIDE);
41 }
583ecab9 42 iounmap(l2x0_base);
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43 return 0;
44}
45
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46static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
47{
48 /*
49 * We can't write to secure registers as we are in non-secure
50 * mode, until we have some SMI service available.
51 */
52}
53
a3849a4c 54static int __init ux500_l2x0_init(void)
458eef2f 55{
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56 /* Multiplatform guard */
57 if (!((cpu_is_u8500_family() || cpu_is_ux540_family())))
31c72abb 58 return -ENODEV;
458eef2f 59
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60 /* Unlock before init */
61 ux500_l2x0_unlock();
67161733 62 outer_cache.write_sec = ux500_l2c310_write_sec;
823e7546 63 l2x0_of_init(0, ~0);
458eef2f 64
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65 return 0;
66}
458eef2f 67early_initcall(ux500_l2x0_init);
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