[deliverable/linux.git] / arch / arm / mach-ux500 / cpu.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */

#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
#include <asm/localtimer.h>

#include <plat/mtu.h>
#include <mach/hardware.h>
#include <mach/setup.h>
#include <mach/devices.h>
#include <mach/prcmu.h>

#include "clock.h"

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2x0_base;
#endif

void __init ux500_map_io(void)
{
}

void __init ux500_init_irq(void)
{
	void __iomem *dist_base;
	void __iomem *cpu_base;

	if (cpu_is_u5500()) {
		dist_base = __io_address(U5500_GIC_DIST_BASE);
		cpu_base = __io_address(U5500_GIC_CPU_BASE);
	} else if (cpu_is_u8500()) {
		dist_base = __io_address(U8500_GIC_DIST_BASE);
		cpu_base = __io_address(U8500_GIC_CPU_BASE);
	} else
		ux500_unknown_soc();

	gic_init(0, 29, dist_base, cpu_base);

	/*
	 * Init clocks here so that they are available for system timer
	 * initialization.
	 */
	if (cpu_is_u8500())
		prcmu_early_init();
	clk_init();
}

#ifdef CONFIG_CACHE_L2X0
static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
{
	/* wait for the operation to complete */
	while (readl_relaxed(reg) & mask)
		;
}

static inline void ux500_cache_sync(void)
{
	void __iomem *base = l2x0_base;

	writel_relaxed(0, base + L2X0_CACHE_SYNC);
	ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
}

/*
 * The L2 cache cannot be turned off in the non-secure world.
 * Dummy until a secure service is in place.
 */
static void ux500_l2x0_disable(void)
{
}

/*
 * This is only called when doing a kexec, just after turning off the L2
 * and L1 cache, and it is surrounded by a spinlock in the generic version.
 * However, we're not really turning off the L2 cache right now and the
 * PL310 does not support exclusive accesses (used to implement the spinlock).
 * So, the invalidation needs to be done without the spinlock.
 */
static void ux500_l2x0_inv_all(void)
{
	void __iomem *base = l2x0_base;
	uint32_t l2x0_way_mask = (1<<16) - 1;	/* Bitmask of active ways */

	/* invalidate all ways */
	writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
	ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
	ux500_cache_sync();
}

static int ux500_l2x0_init(void)
{
	if (cpu_is_u5500())
		l2x0_base = __io_address(U5500_L2CC_BASE);
	else if (cpu_is_u8500())
		l2x0_base = __io_address(U8500_L2CC_BASE);
	else
		ux500_unknown_soc();

	/* 64KB way size, 8 way associativity, force WA */
	l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);

	/* Override invalidate function */
	outer_cache.disable = ux500_l2x0_disable;
	outer_cache.inv_all = ux500_l2x0_inv_all;

	return 0;
}
early_initcall(ux500_l2x0_init);
#endif

static void __init ux500_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
	/* Setup the local timer base */
	if (cpu_is_u5500())
		twd_base = __io_address(U5500_TWD_BASE);
	else if (cpu_is_u8500())
		twd_base = __io_address(U8500_TWD_BASE);
	else
		ux500_unknown_soc();
#endif
	if (cpu_is_u5500())
		mtu_base = __io_address(U5500_MTU0_BASE);
	else if (cpu_is_u8500ed())
		mtu_base = __io_address(U8500_MTU0_BASE_ED);
	else if (cpu_is_u8500())
		mtu_base = __io_address(U8500_MTU0_BASE);
	else
		ux500_unknown_soc();

	nmdk_timer_init();
}

struct sys_timer ux500_timer = {
	.init	= ux500_timer_init,
};
Commit	Line	Data
178980f9 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	5	* License terms: GNU General Public License (GPL) version 2
	6	*/
	7
	8	#include <linux/platform_device.h>
178980f9 RV	9	#include <linux/io.h>
	10	#include <linux/clk.h>
	11
ae694804	12	#include <asm/cacheflush.h>
178980f9 RV	13	#include <asm/hardware/cache-l2x0.h>
	14	#include <asm/hardware/gic.h>
	15	#include <asm/mach/map.h>
41ac329f	16	#include <asm/localtimer.h>
178980f9	17
41ac329f	18	#include <plat/mtu.h>
178980f9 RV	19	#include <mach/hardware.h>
178980f9 RV	20	#include <mach/setup.h>
d48fd006	21	#include <mach/devices.h>
fcbd458e	22	#include <mach/prcmu.h>
178980f9 RV	23
	24	#include "clock.h"
	25
92389ca8 RV	26	#ifdef CONFIG_CACHE_L2X0
	27	static void __iomem *l2x0_base;
	28	#endif
178980f9 RV	29
	30	void __init ux500_map_io(void)
	31	{
178980f9 RV	32	}
	33
	34	void __init ux500_init_irq(void)
	35	{
92389ca8 RV	36	void __iomem *dist_base;
	37	void __iomem *cpu_base;
	38
	39	if (cpu_is_u5500()) {
	40	dist_base = __io_address(U5500_GIC_DIST_BASE);
	41	cpu_base = __io_address(U5500_GIC_CPU_BASE);
	42	} else if (cpu_is_u8500()) {
	43	dist_base = __io_address(U8500_GIC_DIST_BASE);
	44	cpu_base = __io_address(U8500_GIC_CPU_BASE);
	45	} else
	46	ux500_unknown_soc();
	47
	48	gic_init(0, 29, dist_base, cpu_base);
ba327b1e LW	49
	50	/*
	51	* Init clocks here so that they are available for system timer
	52	* initialization.
	53	*/
9b04f8b9 PF	54	if (cpu_is_u8500())
9b04f8b9 PF	55	prcmu_early_init();
ba327b1e	56	clk_init();
178980f9 RV	57	}
	58
	59	#ifdef CONFIG_CACHE_L2X0
ae694804 PF	60	static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
	61	{
	62	/* wait for the operation to complete */
ffc43ef3	63	while (readl_relaxed(reg) & mask)
ae694804 PF	64	;
	65	}
	66
	67	static inline void ux500_cache_sync(void)
	68	{
92389ca8 RV	69	void __iomem *base = l2x0_base;
92389ca8 RV	70
ffc43ef3	71	writel_relaxed(0, base + L2X0_CACHE_SYNC);
ae694804 PF	72	ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
	73	}
	74
	75	/*
	76	* The L2 cache cannot be turned off in the non-secure world.
	77	* Dummy until a secure service is in place.
	78	*/
	79	static void ux500_l2x0_disable(void)
	80	{
	81	}
	82
	83	/*
	84	* This is only called when doing a kexec, just after turning off the L2
	85	* and L1 cache, and it is surrounded by a spinlock in the generic version.
	86	* However, we're not really turning off the L2 cache right now and the
	87	* PL310 does not support exclusive accesses (used to implement the spinlock).
	88	* So, the invalidation needs to be done without the spinlock.
	89	*/
	90	static void ux500_l2x0_inv_all(void)
	91	{
92389ca8	92	void __iomem *base = l2x0_base;
ae694804 PF	93	uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
	94
	95	/* invalidate all ways */
92389ca8 RV	96	writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
92389ca8 RV	97	ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
ae694804 PF	98	ux500_cache_sync();
	99	}
	100
178980f9 RV	101	static int ux500_l2x0_init(void)
178980f9 RV	102	{
92389ca8 RV	103	if (cpu_is_u5500())
	104	l2x0_base = __io_address(U5500_L2CC_BASE);
	105	else if (cpu_is_u8500())
	106	l2x0_base = __io_address(U8500_L2CC_BASE);
	107	else
	108	ux500_unknown_soc();
178980f9 RV	109
	110	/* 64KB way size, 8 way associativity, force WA */
	111	l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
	112
ae694804 PF	113	/* Override invalidate function */
	114	outer_cache.disable = ux500_l2x0_disable;
	115	outer_cache.inv_all = ux500_l2x0_inv_all;
	116
178980f9 RV	117	return 0;
	118	}
	119	early_initcall(ux500_l2x0_init);
	120	#endif
41ac329f RV	121
	122	static void __init ux500_timer_init(void)
	123	{
	124	#ifdef CONFIG_LOCAL_TIMERS
	125	/* Setup the local timer base */
92389ca8 RV	126	if (cpu_is_u5500())
	127	twd_base = __io_address(U5500_TWD_BASE);
	128	else if (cpu_is_u8500())
	129	twd_base = __io_address(U8500_TWD_BASE);
	130	else
	131	ux500_unknown_soc();
41ac329f	132	#endif
92389ca8 RV	133	if (cpu_is_u5500())
	134	mtu_base = __io_address(U5500_MTU0_BASE);
	135	else if (cpu_is_u8500ed())
41ac329f	136	mtu_base = __io_address(U8500_MTU0_BASE_ED);
92389ca8 RV	137	else if (cpu_is_u8500())
92389ca8 RV	138	mtu_base = __io_address(U8500_MTU0_BASE);
41ac329f	139	else
92389ca8	140	ux500_unknown_soc();
41ac329f RV	141
	142	nmdk_timer_init();
	143	}
	144
	145	struct sys_timer ux500_timer = {
	146	.init = ux500_timer_init,
	147	};