projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c9c09572 RV |
1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | * | |
| 4 | * License terms: GNU General Public License (GPL) version 2 | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __MACH_DB8500_REGS_H | |
| 8 | #define __MACH_DB8500_REGS_H | |
| 9 | ||
| 7b8ddb06 LW |
10 | /* Base address and bank offsets for ESRAM */ |
| 11 | #define U8500_ESRAM_BASE 0x40000000 | |
| 12 | #define U8500_ESRAM_BANK_SIZE 0x00020000 | |
| 13 | #define U8500_ESRAM_BANK0 U8500_ESRAM_BASE | |
| 14 | #define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) | |
| 15 | #define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) | |
| 16 | #define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) | |
| 17 | #define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) | |
| 32647406 LW |
18 | /* |
| 19 | * on V1 DMA uses 4KB for logical parameters position is right after the 64KB | |
| 20 | * reserved for security | |
| 21 | */ | |
| 22 | #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 | |
| 23 | ||
| 24 | #define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) | |
| 7b8ddb06 | 25 | |
| ca2ea4e8 LW |
26 | /* This address fulfills the 256k alignment requirement of the lcla base */ |
| 27 | #define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 | |
| 28 | ||
| c9c09572 RV |
29 | #define U8500_PER3_BASE 0x80000000 |
| 30 | #define U8500_STM_BASE 0x80100000 | |
| 31 | #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) | |
| 32 | #define U8500_PER2_BASE 0x80110000 | |
| 33 | #define U8500_PER1_BASE 0x80120000 | |
| 34 | #define U8500_B2R2_BASE 0x80130000 | |
| 35 | #define U8500_HSEM_BASE 0x80140000 | |
| 36 | #define U8500_PER4_BASE 0x80150000 | |
| 32647406 | 37 | #define U8500_TPIU_BASE 0x80190000 |
| c9c09572 RV |
38 | #define U8500_ICN_BASE 0x81000000 |
| 39 | ||
| 40 | #define U8500_BOOT_ROM_BASE 0x90000000 | |
| 32647406 LW |
41 | /* ASIC ID is at 0xbf4 offset within this region */ |
| 42 | #define U8500_ASIC_ID_BASE 0x9001D000 | |
| c9c09572 | 43 | |
| bc71c096 LW |
44 | #define U9540_BOOT_ROM_BASE 0xFFFE0000 |
| 45 | /* ASIC ID is at 0xbf4 offset within this region */ | |
| 46 | #define U9540_ASIC_ID_BASE 0xFFFFD000 | |
| 47 | ||
| c9c09572 | 48 | #define U8500_PER6_BASE 0xa03c0000 |
| ca2ea4e8 | 49 | #define U8500_PER7_BASE 0xa03d0000 |
| c9c09572 | 50 | #define U8500_PER5_BASE 0xa03e0000 |
| c9c09572 RV |
51 | |
| 52 | #define U8500_SVA_BASE 0xa0100000 | |
| 53 | #define U8500_SIA_BASE 0xa0200000 | |
| 54 | ||
| 55 | #define U8500_SGA_BASE 0xa0300000 | |
| 56 | #define U8500_MCDE_BASE 0xa0350000 | |
| c9c09572 RV |
57 | #define U8500_DMA_BASE 0x801C0000 /* v1 */ |
| 58 | ||
| 59 | #define U8500_SBAG_BASE 0xa0390000 | |
| 60 | ||
| 61 | #define U8500_SCU_BASE 0xa0410000 | |
| 62 | #define U8500_GIC_CPU_BASE 0xa0410100 | |
| 63 | #define U8500_TWD_BASE 0xa0410600 | |
| 64 | #define U8500_GIC_DIST_BASE 0xa0411000 | |
| 65 | #define U8500_L2CC_BASE 0xa0412000 | |
| 66 | ||
| 67 | #define U8500_MODEM_I2C 0xb7e02000 | |
| 68 | ||
| 69 | #define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) | |
| 70 | #define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) | |
| 71 | #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) | |
| 72 | #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) | |
| 73 | ||
| c9c09572 RV |
74 | #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) |
| 75 | #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) | |
| 76 | ||
| 25985edc | 77 | /* per6 base addresses */ |
| c9c09572 | 78 | #define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) |
| 32647406 LW |
79 | #define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000) |
| 80 | #define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000) | |
| 81 | #define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000) | |
| 82 | #define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100) | |
| c9c09572 RV |
83 | #define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ |
| 84 | #define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ | |
| 85 | #define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ | |
| 32647406 LW |
86 | #define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000) |
| 87 | #define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000) | |
| c9c09572 RV |
88 | #define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) |
| 89 | ||
| 25985edc | 90 | /* per5 base addresses */ |
| c9c09572 RV |
91 | #define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) |
| 92 | #define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) | |
| 93 | ||
| 25985edc | 94 | /* per4 base addresses */ |
| c9c09572 RV |
95 | #define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) |
| 96 | #define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) | |
| 97 | #define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) | |
| 98 | #define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) | |
| 99 | #define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) | |
| 100 | #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) | |
| 101 | #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) | |
| 102 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) | |
| bc71c096 | 103 | #define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000) |
| 32647406 LW |
104 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) |
| 105 | #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) | |
| c15def1c LW |
106 | #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) |
| 107 | #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) | |
| 7ed00af7 | 108 | |
| c9c09572 RV |
109 | /* per3 base addresses */ |
| 110 | #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) | |
| 111 | #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) | |
| 112 | #define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) | |
| 113 | #define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) | |
| 114 | #define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) | |
| 115 | #define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) | |
| 116 | #define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) | |
| 117 | #define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) | |
| 118 | #define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) | |
| 119 | ||
| 25985edc | 120 | /* per2 base addresses */ |
| c9c09572 RV |
121 | #define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) |
| 122 | #define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) | |
| 123 | #define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) | |
| 124 | #define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) | |
| 125 | #define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) | |
| 126 | #define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) | |
| 127 | #define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) | |
| 128 | #define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) | |
| 129 | #define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) | |
| 130 | #define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) | |
| 131 | #define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) | |
| 132 | #define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) | |
| 133 | ||
| 134 | /* per1 base addresses */ | |
| 135 | #define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) | |
| 136 | #define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) | |
| 137 | #define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) | |
| 32647406 | 138 | #define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000) |
| c9c09572 RV |
139 | #define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) |
| 140 | #define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) | |
| 141 | #define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) | |
| 142 | #define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) | |
| 143 | #define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) | |
| 144 | #define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) | |
| 145 | ||
| 146 | #define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 | |
| 147 | ||
| 148 | #define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE | |
| 149 | #define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) | |
| 150 | #define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE | |
| 151 | #define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) | |
| 152 | #define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) | |
| 153 | #define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) | |
| 154 | #define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE | |
| 155 | #define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) | |
| 156 | #define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE | |
| 157 | ||
| 32647406 LW |
158 | #define U8500_MCDE_SIZE 0x1000 |
| 159 | #define U8500_DSI_LINK_SIZE 0x1000 | |
| 160 | #define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE) | |
| 161 | #define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) | |
| 162 | #define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) | |
| 163 | #define U8500_DSI_LINK_COUNT 0x3 | |
| 164 | ||
| 165 | /* Modem and APE physical addresses */ | |
| 166 | #define U8500_MODEM_BASE 0xe000000 | |
| 167 | #define U8500_APE_BASE 0x6000000 | |
| 168 | ||
| eda413c2 LJ |
169 | /* SoC identification number information */ |
| 170 | #define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0) | |
| 171 | ||
| 174e7796 LW |
172 | /* Offsets to specific addresses in some IP blocks for DMA */ |
| 173 | #define MSP_TX_RX_REG_OFFSET 0 | |
| 174 | #define CRYP1_RX_REG_OFFSET 0x10 | |
| 175 | #define CRYP1_TX_REG_OFFSET 0x8 | |
| 176 | #define HASH1_TX_REG_OFFSET 0x4 | |
| 177 | ||
| 178 | /* | |
| 179 | * Macros to get at IO space when running virtually | |
| 180 | * We dont map all the peripherals, let ioremap do | |
| 181 | * this for us. We map only very basic peripherals here. | |
| 182 | */ | |
| 183 | #define U8500_IO_VIRTUAL 0xf0000000 | |
| 184 | #define U8500_IO_PHYSICAL 0xa0000000 | |
| 185 | /* This is where we map in the ROM to check ASIC IDs */ | |
| 080e0435 | 186 | #define UX500_VIRT_ROM IOMEM(0xf0000000) |
| 174e7796 LW |
187 | |
| 188 | /* This macro is used in assembly, so no cast */ | |
| 189 | #define IO_ADDRESS(x) \ | |
| 190 | (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) | |
| 191 | ||
| 192 | /* typesafe io address */ | |
| 193 | #define __io_address(n) IOMEM(IO_ADDRESS(n)) | |
| 194 | ||
| 195 | /* Used by some plat-nomadik code */ | |
| 196 | #define io_p2v(n) __io_address(n) | |
| 197 | ||
| 198 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | |
| 199 | ||
| c9c09572 | 200 | #endif |