projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c9c09572 RV |
1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | * | |
| 4 | * License terms: GNU General Public License (GPL) version 2 | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __MACH_DB8500_REGS_H | |
| 8 | #define __MACH_DB8500_REGS_H | |
| 9 | ||
| 7b8ddb06 LW |
10 | /* Base address and bank offsets for ESRAM */ |
| 11 | #define U8500_ESRAM_BASE 0x40000000 | |
| 12 | #define U8500_ESRAM_BANK_SIZE 0x00020000 | |
| 13 | #define U8500_ESRAM_BANK0 U8500_ESRAM_BASE | |
| 14 | #define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE) | |
| 15 | #define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE) | |
| 16 | #define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE) | |
| 17 | #define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE) | |
| 32647406 LW |
18 | /* |
| 19 | * on V1 DMA uses 4KB for logical parameters position is right after the 64KB | |
| 20 | * reserved for security | |
| 21 | */ | |
| 22 | #define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000 | |
| 23 | ||
| 24 | #define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET) | |
| f4185592 | 25 | #define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000) |
| 7b8ddb06 | 26 | |
| ca2ea4e8 LW |
27 | /* This address fulfills the 256k alignment requirement of the lcla base */ |
| 28 | #define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4 | |
| 29 | ||
| c9c09572 RV |
30 | #define U8500_PER3_BASE 0x80000000 |
| 31 | #define U8500_STM_BASE 0x80100000 | |
| 32 | #define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) | |
| 33 | #define U8500_PER2_BASE 0x80110000 | |
| 34 | #define U8500_PER1_BASE 0x80120000 | |
| 35 | #define U8500_B2R2_BASE 0x80130000 | |
| 36 | #define U8500_HSEM_BASE 0x80140000 | |
| 37 | #define U8500_PER4_BASE 0x80150000 | |
| 32647406 | 38 | #define U8500_TPIU_BASE 0x80190000 |
| c9c09572 RV |
39 | #define U8500_ICN_BASE 0x81000000 |
| 40 | ||
| 41 | #define U8500_BOOT_ROM_BASE 0x90000000 | |
| 32647406 LW |
42 | /* ASIC ID is at 0xbf4 offset within this region */ |
| 43 | #define U8500_ASIC_ID_BASE 0x9001D000 | |
| c9c09572 RV |
44 | |
| 45 | #define U8500_PER6_BASE 0xa03c0000 | |
| ca2ea4e8 | 46 | #define U8500_PER7_BASE 0xa03d0000 |
| c9c09572 RV |
47 | #define U8500_PER5_BASE 0xa03e0000 |
| 48 | #define U8500_PER7_BASE_ED 0xa03d0000 | |
| 49 | ||
| 50 | #define U8500_SVA_BASE 0xa0100000 | |
| 51 | #define U8500_SIA_BASE 0xa0200000 | |
| 52 | ||
| 53 | #define U8500_SGA_BASE 0xa0300000 | |
| 54 | #define U8500_MCDE_BASE 0xa0350000 | |
| 55 | #define U8500_DMA_BASE_ED 0xa0362000 | |
| 56 | #define U8500_DMA_BASE 0x801C0000 /* v1 */ | |
| 57 | ||
| 58 | #define U8500_SBAG_BASE 0xa0390000 | |
| 59 | ||
| 60 | #define U8500_SCU_BASE 0xa0410000 | |
| 61 | #define U8500_GIC_CPU_BASE 0xa0410100 | |
| 62 | #define U8500_TWD_BASE 0xa0410600 | |
| 63 | #define U8500_GIC_DIST_BASE 0xa0411000 | |
| 64 | #define U8500_L2CC_BASE 0xa0412000 | |
| 65 | ||
| 66 | #define U8500_MODEM_I2C 0xb7e02000 | |
| 67 | ||
| 68 | #define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) | |
| 69 | #define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) | |
| 70 | #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) | |
| 71 | #define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) | |
| 72 | ||
| 25985edc | 73 | /* per7 base addresses */ |
| c9c09572 RV |
74 | #define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) |
| 75 | #define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) | |
| 76 | #define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) | |
| 77 | #define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) | |
| 78 | #define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) | |
| 79 | ||
| 80 | #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) | |
| 81 | #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) | |
| 82 | ||
| 25985edc | 83 | /* per6 base addresses */ |
| c9c09572 | 84 | #define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) |
| 32647406 LW |
85 | #define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000) |
| 86 | #define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000) | |
| 87 | #define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000) | |
| 88 | #define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100) | |
| c9c09572 RV |
89 | #define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ |
| 90 | #define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ | |
| 91 | #define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ | |
| 32647406 LW |
92 | #define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000) |
| 93 | #define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000) | |
| c9c09572 RV |
94 | #define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) |
| 95 | ||
| 25985edc | 96 | /* per5 base addresses */ |
| c9c09572 RV |
97 | #define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) |
| 98 | #define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) | |
| 99 | ||
| 25985edc | 100 | /* per4 base addresses */ |
| c9c09572 RV |
101 | #define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) |
| 102 | #define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) | |
| 103 | #define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) | |
| 104 | #define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) | |
| 105 | #define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) | |
| 106 | #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) | |
| 107 | #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) | |
| 108 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) | |
| 7ed00af7 MW |
109 | #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) |
| 110 | #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) | |
| fcbd458e | 111 | #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) |
| 32647406 LW |
112 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) |
| 113 | #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) | |
| c9c09572 | 114 | |
| 7ed00af7 | 115 | |
| c9c09572 RV |
116 | /* per3 base addresses */ |
| 117 | #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) | |
| 118 | #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) | |
| 119 | #define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) | |
| 120 | #define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) | |
| 121 | #define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) | |
| 122 | #define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) | |
| 123 | #define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) | |
| 124 | #define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) | |
| 125 | #define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) | |
| 126 | ||
| 25985edc | 127 | /* per2 base addresses */ |
| c9c09572 RV |
128 | #define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) |
| 129 | #define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) | |
| 130 | #define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) | |
| 131 | #define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) | |
| 132 | #define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) | |
| 133 | #define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) | |
| 134 | #define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) | |
| 135 | #define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) | |
| 136 | #define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) | |
| 137 | #define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) | |
| 138 | #define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) | |
| 139 | #define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) | |
| 140 | ||
| 141 | /* per1 base addresses */ | |
| 142 | #define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) | |
| 143 | #define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) | |
| 144 | #define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) | |
| 32647406 | 145 | #define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000) |
| c9c09572 RV |
146 | #define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) |
| 147 | #define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) | |
| 148 | #define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) | |
| 149 | #define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) | |
| 150 | #define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) | |
| 151 | #define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) | |
| 152 | ||
| 153 | #define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 | |
| 154 | ||
| 155 | #define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE | |
| 156 | #define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) | |
| 157 | #define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE | |
| 158 | #define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) | |
| 159 | #define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) | |
| 160 | #define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) | |
| 161 | #define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE | |
| 162 | #define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) | |
| 163 | #define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE | |
| 164 | ||
| 32647406 LW |
165 | #define U8500_MCDE_SIZE 0x1000 |
| 166 | #define U8500_DSI_LINK_SIZE 0x1000 | |
| 167 | #define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE) | |
| 168 | #define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) | |
| 169 | #define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) | |
| 170 | #define U8500_DSI_LINK_COUNT 0x3 | |
| 171 | ||
| 172 | /* Modem and APE physical addresses */ | |
| 173 | #define U8500_MODEM_BASE 0xe000000 | |
| 174 | #define U8500_APE_BASE 0x6000000 | |
| 175 | ||
| c9c09572 | 176 | #endif |