projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| aa44ef4d SK |
1 | /* |
| 2 | * Copyright (C) 2002 ARM Ltd. | |
| 3 | * Copyright (C) 2008 STMicroelctronics. | |
| 4 | * Copyright (C) 2009 ST-Ericsson. | |
| 5 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
| 6 | * | |
| 7 | * This file is based on arm realview platform | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | */ | |
| 13 | #include <linux/init.h> | |
| 14 | #include <linux/errno.h> | |
| 15 | #include <linux/delay.h> | |
| 16 | #include <linux/device.h> | |
| 17 | #include <linux/smp.h> | |
| 18 | #include <linux/io.h> | |
| 58202033 LW |
19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> | |
| aa44ef4d SK |
21 | |
| 22 | #include <asm/cacheflush.h> | |
| eb50439b | 23 | #include <asm/smp_plat.h> |
| aa44ef4d | 24 | #include <asm/smp_scu.h> |
| 7a4f2609 | 25 | |
| e657bcf6 | 26 | #include "setup.h" |
| aa44ef4d | 27 | |
| 174e7796 | 28 | #include "db8500-regs.h" |
| 7a4f2609 LW |
29 | #include "id.h" |
| 30 | ||
| c00def71 LW |
31 | /* Magic triggers in backup RAM */ |
| 32 | #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 | |
| 33 | #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 | |
| aa44ef4d | 34 | |
| c00def71 | 35 | static void wakeup_secondary(void) |
| aa44ef4d | 36 | { |
| c00def71 LW |
37 | struct device_node *np; |
| 38 | static void __iomem *backupram; | |
| 9d704c04 | 39 | |
| c00def71 LW |
40 | np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram"); |
| 41 | if (!np) { | |
| 42 | pr_err("No backupram base address\n"); | |
| 43 | return; | |
| 44 | } | |
| 45 | backupram = of_iomap(np, 0); | |
| 46 | of_node_put(np); | |
| 47 | if (!backupram) { | |
| 48 | pr_err("No backupram remap\n"); | |
| 49 | return; | |
| aa44ef4d SK |
50 | } |
| 51 | ||
| aa44ef4d SK |
52 | /* |
| 53 | * write the address of secondary startup into the backup ram register | |
| 54 | * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the | |
| 55 | * backup ram register at offset 0x1FF0, which is what boot rom code | |
| c00def71 | 56 | * is waiting for. This will wake up the secondary core from WFE. |
| aa44ef4d | 57 | */ |
| c00def71 LW |
58 | writel(virt_to_phys(secondary_startup), |
| 59 | backupram + UX500_CPU1_JUMPADDR_OFFSET); | |
| 60 | writel(0xA1FEED01, | |
| 61 | backupram + UX500_CPU1_WAKEMAGIC_OFFSET); | |
| aa44ef4d SK |
62 | |
| 63 | /* make sure write buffer is drained */ | |
| 64 | mb(); | |
| c00def71 | 65 | iounmap(backupram); |
| aa44ef4d SK |
66 | } |
| 67 | ||
| c00def71 | 68 | static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) |
| aa44ef4d | 69 | { |
| 58202033 | 70 | struct device_node *np; |
| c00def71 LW |
71 | static void __iomem *scu_base; |
| 72 | unsigned int ncores; | |
| 73 | int i; | |
| aa44ef4d | 74 | |
| 58202033 | 75 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); |
| c00def71 LW |
76 | if (!np) { |
| 77 | pr_err("No SCU base address\n"); | |
| 78 | return; | |
| 79 | } | |
| 58202033 LW |
80 | scu_base = of_iomap(np, 0); |
| 81 | of_node_put(np); | |
| c00def71 LW |
82 | if (!scu_base) { |
| 83 | pr_err("No SCU remap\n"); | |
| 58202033 | 84 | return; |
| aa44ef4d SK |
85 | } |
| 86 | ||
| c00def71 LW |
87 | scu_enable(scu_base); |
| 88 | ncores = scu_get_core_count(scu_base); | |
| bbc3d14e RK |
89 | for (i = 0; i < ncores; i++) |
| 90 | set_cpu_possible(i, true); | |
| c00def71 | 91 | iounmap(scu_base); |
| bbc3d14e | 92 | } |
| aa44ef4d | 93 | |
| c00def71 | 94 | static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| bbc3d14e | 95 | { |
| 05c74a6c | 96 | wakeup_secondary(); |
| c00def71 LW |
97 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
| 98 | return 0; | |
| aa44ef4d | 99 | } |
| 5ac21a94 | 100 | |
| 75305275 | 101 | static const struct smp_operations ux500_smp_ops __initconst = { |
| 5ac21a94 | 102 | .smp_prepare_cpus = ux500_smp_prepare_cpus, |
| 5ac21a94 MZ |
103 | .smp_boot_secondary = ux500_boot_secondary, |
| 104 | #ifdef CONFIG_HOTPLUG_CPU | |
| 105 | .cpu_die = ux500_cpu_die, | |
| 106 | #endif | |
| 107 | }; | |
| c00def71 | 108 | CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops); |