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aa44ef4d SK |
1 | /* |
2 | * Copyright (C) 2002 ARM Ltd. | |
3 | * Copyright (C) 2008 STMicroelctronics. | |
4 | * Copyright (C) 2009 ST-Ericsson. | |
5 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
6 | * | |
7 | * This file is based on arm realview platform | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/io.h> | |
58202033 LW |
19 | #include <linux/of.h> |
20 | #include <linux/of_address.h> | |
aa44ef4d SK |
21 | |
22 | #include <asm/cacheflush.h> | |
eb50439b | 23 | #include <asm/smp_plat.h> |
aa44ef4d | 24 | #include <asm/smp_scu.h> |
7a4f2609 | 25 | |
e657bcf6 | 26 | #include "setup.h" |
aa44ef4d | 27 | |
174e7796 | 28 | #include "db8500-regs.h" |
7a4f2609 | 29 | |
c00def71 LW |
30 | /* Magic triggers in backup RAM */ |
31 | #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 | |
32 | #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 | |
aa44ef4d | 33 | |
c00def71 | 34 | static void wakeup_secondary(void) |
aa44ef4d | 35 | { |
c00def71 LW |
36 | struct device_node *np; |
37 | static void __iomem *backupram; | |
9d704c04 | 38 | |
c00def71 LW |
39 | np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram"); |
40 | if (!np) { | |
41 | pr_err("No backupram base address\n"); | |
42 | return; | |
43 | } | |
44 | backupram = of_iomap(np, 0); | |
45 | of_node_put(np); | |
46 | if (!backupram) { | |
47 | pr_err("No backupram remap\n"); | |
48 | return; | |
aa44ef4d SK |
49 | } |
50 | ||
aa44ef4d SK |
51 | /* |
52 | * write the address of secondary startup into the backup ram register | |
53 | * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the | |
54 | * backup ram register at offset 0x1FF0, which is what boot rom code | |
c00def71 | 55 | * is waiting for. This will wake up the secondary core from WFE. |
aa44ef4d | 56 | */ |
c00def71 LW |
57 | writel(virt_to_phys(secondary_startup), |
58 | backupram + UX500_CPU1_JUMPADDR_OFFSET); | |
59 | writel(0xA1FEED01, | |
60 | backupram + UX500_CPU1_WAKEMAGIC_OFFSET); | |
aa44ef4d SK |
61 | |
62 | /* make sure write buffer is drained */ | |
63 | mb(); | |
c00def71 | 64 | iounmap(backupram); |
aa44ef4d SK |
65 | } |
66 | ||
c00def71 | 67 | static void __init ux500_smp_prepare_cpus(unsigned int max_cpus) |
aa44ef4d | 68 | { |
58202033 | 69 | struct device_node *np; |
c00def71 LW |
70 | static void __iomem *scu_base; |
71 | unsigned int ncores; | |
72 | int i; | |
aa44ef4d | 73 | |
58202033 | 74 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); |
c00def71 LW |
75 | if (!np) { |
76 | pr_err("No SCU base address\n"); | |
77 | return; | |
78 | } | |
58202033 LW |
79 | scu_base = of_iomap(np, 0); |
80 | of_node_put(np); | |
c00def71 LW |
81 | if (!scu_base) { |
82 | pr_err("No SCU remap\n"); | |
58202033 | 83 | return; |
aa44ef4d SK |
84 | } |
85 | ||
c00def71 LW |
86 | scu_enable(scu_base); |
87 | ncores = scu_get_core_count(scu_base); | |
bbc3d14e RK |
88 | for (i = 0; i < ncores; i++) |
89 | set_cpu_possible(i, true); | |
c00def71 | 90 | iounmap(scu_base); |
bbc3d14e | 91 | } |
aa44ef4d | 92 | |
c00def71 | 93 | static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) |
bbc3d14e | 94 | { |
05c74a6c | 95 | wakeup_secondary(); |
c00def71 LW |
96 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
97 | return 0; | |
aa44ef4d | 98 | } |
5ac21a94 | 99 | |
75305275 | 100 | static const struct smp_operations ux500_smp_ops __initconst = { |
5ac21a94 | 101 | .smp_prepare_cpus = ux500_smp_prepare_cpus, |
5ac21a94 MZ |
102 | .smp_boot_secondary = ux500_boot_secondary, |
103 | #ifdef CONFIG_HOTPLUG_CPU | |
104 | .cpu_die = ux500_cpu_die, | |
105 | #endif | |
106 | }; | |
c00def71 | 107 | CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops); |