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aa44ef4d SK |
1 | /* |
2 | * Copyright (C) 2002 ARM Ltd. | |
3 | * Copyright (C) 2008 STMicroelctronics. | |
4 | * Copyright (C) 2009 ST-Ericsson. | |
5 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
6 | * | |
7 | * This file is based on arm realview platform | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/io.h> | |
19 | ||
20 | #include <asm/cacheflush.h> | |
aa44ef4d SK |
21 | #include <asm/smp_scu.h> |
22 | #include <mach/hardware.h> | |
92389ca8 | 23 | #include <mach/setup.h> |
aa44ef4d SK |
24 | |
25 | /* | |
26 | * control for which core is the next to come out of the secondary | |
27 | * boot "holding pen" | |
28 | */ | |
3c5728ed | 29 | volatile int pen_release = -1; |
aa44ef4d | 30 | |
3705ff6d RK |
31 | /* |
32 | * Write pen_release in a way that is guaranteed to be visible to all | |
33 | * observers, irrespective of whether they're taking part in coherency | |
34 | * or not. This is necessary for the hotplug code to work reliably. | |
35 | */ | |
36 | static void write_pen_release(int val) | |
aa44ef4d | 37 | { |
3705ff6d RK |
38 | pen_release = val; |
39 | smp_wmb(); | |
40 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
41 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
aa44ef4d SK |
42 | } |
43 | ||
92389ca8 RV |
44 | static void __iomem *scu_base_addr(void) |
45 | { | |
46 | if (cpu_is_u5500()) | |
47 | return __io_address(U5500_SCU_BASE); | |
48 | else if (cpu_is_u8500()) | |
49 | return __io_address(U8500_SCU_BASE); | |
50 | else | |
51 | ux500_unknown_soc(); | |
52 | ||
53 | return NULL; | |
54 | } | |
55 | ||
aa44ef4d SK |
56 | static DEFINE_SPINLOCK(boot_lock); |
57 | ||
58 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
59 | { | |
aa44ef4d SK |
60 | /* |
61 | * if any interrupts are already enabled for the primary | |
62 | * core (e.g. timer irq), then they will not have been enabled | |
63 | * for us: do so | |
64 | */ | |
38489533 | 65 | gic_secondary_init(0); |
aa44ef4d SK |
66 | |
67 | /* | |
68 | * let the primary processor know we're out of the | |
69 | * pen, then head off into the C entry point | |
70 | */ | |
3705ff6d | 71 | write_pen_release(-1); |
aa44ef4d SK |
72 | |
73 | /* | |
74 | * Synchronise with the boot thread. | |
75 | */ | |
76 | spin_lock(&boot_lock); | |
77 | spin_unlock(&boot_lock); | |
78 | } | |
79 | ||
80 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
81 | { | |
82 | unsigned long timeout; | |
83 | ||
84 | /* | |
85 | * set synchronisation state between this boot processor | |
86 | * and the secondary one | |
87 | */ | |
88 | spin_lock(&boot_lock); | |
89 | ||
90 | /* | |
91 | * The secondary processor is waiting to be released from | |
92 | * the holding pen - release it, then wait for it to flag | |
93 | * that it has been released by resetting pen_release. | |
94 | */ | |
3705ff6d | 95 | write_pen_release(cpu); |
aa44ef4d | 96 | |
ad3b6993 | 97 | smp_cross_call(cpumask_of(cpu), 1); |
9d704c04 | 98 | |
aa44ef4d SK |
99 | timeout = jiffies + (1 * HZ); |
100 | while (time_before(jiffies, timeout)) { | |
101 | if (pen_release == -1) | |
102 | break; | |
103 | } | |
104 | ||
105 | /* | |
106 | * now the secondary core is starting up let it run its | |
107 | * calibrations, then wait for it to finish | |
108 | */ | |
109 | spin_unlock(&boot_lock); | |
110 | ||
111 | return pen_release != -1 ? -ENOSYS : 0; | |
112 | } | |
113 | ||
114 | static void __init wakeup_secondary(void) | |
115 | { | |
92389ca8 RV |
116 | void __iomem *backupram; |
117 | ||
118 | if (cpu_is_u5500()) | |
119 | backupram = __io_address(U5500_BACKUPRAM0_BASE); | |
120 | else if (cpu_is_u8500()) | |
121 | backupram = __io_address(U8500_BACKUPRAM0_BASE); | |
122 | else | |
123 | ux500_unknown_soc(); | |
124 | ||
aa44ef4d SK |
125 | /* |
126 | * write the address of secondary startup into the backup ram register | |
127 | * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the | |
128 | * backup ram register at offset 0x1FF0, which is what boot rom code | |
129 | * is waiting for. This would wake up the secondary core from WFE | |
130 | */ | |
92389ca8 | 131 | #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 |
aa44ef4d | 132 | __raw_writel(virt_to_phys(u8500_secondary_startup), |
92389ca8 | 133 | backupram + UX500_CPU1_JUMPADDR_OFFSET); |
aa44ef4d | 134 | |
92389ca8 | 135 | #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 |
aa44ef4d | 136 | __raw_writel(0xA1FEED01, |
92389ca8 | 137 | backupram + UX500_CPU1_WAKEMAGIC_OFFSET); |
aa44ef4d SK |
138 | |
139 | /* make sure write buffer is drained */ | |
140 | mb(); | |
141 | } | |
142 | ||
143 | /* | |
144 | * Initialise the CPU possible map early - this describes the CPUs | |
145 | * which may be present or become present in the system. | |
146 | */ | |
147 | void __init smp_init_cpus(void) | |
148 | { | |
92389ca8 | 149 | void __iomem *scu_base = scu_base_addr(); |
fd778f0a | 150 | unsigned int i, ncores; |
aa44ef4d | 151 | |
92389ca8 | 152 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
aa44ef4d SK |
153 | |
154 | /* sanity check */ | |
bbc3d14e | 155 | if (ncores > NR_CPUS) { |
aa44ef4d SK |
156 | printk(KERN_WARNING |
157 | "U8500: no. of cores (%d) greater than configured " | |
158 | "maximum of %d - clipping\n", | |
bbc3d14e RK |
159 | ncores, NR_CPUS); |
160 | ncores = NR_CPUS; | |
aa44ef4d SK |
161 | } |
162 | ||
bbc3d14e RK |
163 | for (i = 0; i < ncores; i++) |
164 | set_cpu_possible(i, true); | |
165 | } | |
aa44ef4d | 166 | |
05c74a6c | 167 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
bbc3d14e | 168 | { |
bbc3d14e | 169 | int i; |
aa44ef4d SK |
170 | |
171 | /* | |
172 | * Initialise the present map, which describes the set of CPUs | |
173 | * actually populated at the present time. | |
174 | */ | |
175 | for (i = 0; i < max_cpus; i++) | |
176 | set_cpu_present(i, true); | |
177 | ||
92389ca8 | 178 | scu_enable(scu_base_addr()); |
05c74a6c | 179 | wakeup_secondary(); |
aa44ef4d | 180 | } |