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1 | /* |
2 | * Copyright (C) 2002 ARM Ltd. | |
3 | * Copyright (C) 2008 STMicroelctronics. | |
4 | * Copyright (C) 2009 ST-Ericsson. | |
5 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
6 | * | |
7 | * This file is based on arm realview platform | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/smp.h> | |
18 | #include <linux/io.h> | |
19 | ||
20 | #include <asm/cacheflush.h> | |
21 | #include <asm/localtimer.h> | |
22 | #include <asm/smp_scu.h> | |
23 | #include <mach/hardware.h> | |
24 | ||
25 | /* | |
26 | * control for which core is the next to come out of the secondary | |
27 | * boot "holding pen" | |
28 | */ | |
29 | volatile int __cpuinitdata pen_release = -1; | |
30 | ||
31 | static unsigned int __init get_core_count(void) | |
32 | { | |
817412d3 | 33 | return scu_get_core_count(__io_address(UX500_SCU_BASE)); |
aa44ef4d SK |
34 | } |
35 | ||
36 | static DEFINE_SPINLOCK(boot_lock); | |
37 | ||
38 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
39 | { | |
40 | trace_hardirqs_off(); | |
41 | ||
42 | /* | |
43 | * if any interrupts are already enabled for the primary | |
44 | * core (e.g. timer irq), then they will not have been enabled | |
45 | * for us: do so | |
46 | */ | |
817412d3 | 47 | gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); |
aa44ef4d SK |
48 | |
49 | /* | |
50 | * let the primary processor know we're out of the | |
51 | * pen, then head off into the C entry point | |
52 | */ | |
53 | pen_release = -1; | |
54 | ||
55 | /* | |
56 | * Synchronise with the boot thread. | |
57 | */ | |
58 | spin_lock(&boot_lock); | |
59 | spin_unlock(&boot_lock); | |
60 | } | |
61 | ||
62 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
63 | { | |
64 | unsigned long timeout; | |
65 | ||
66 | /* | |
67 | * set synchronisation state between this boot processor | |
68 | * and the secondary one | |
69 | */ | |
70 | spin_lock(&boot_lock); | |
71 | ||
72 | /* | |
73 | * The secondary processor is waiting to be released from | |
74 | * the holding pen - release it, then wait for it to flag | |
75 | * that it has been released by resetting pen_release. | |
76 | */ | |
77 | pen_release = cpu; | |
8e797a7e SK |
78 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); |
79 | outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); | |
aa44ef4d | 80 | |
9d704c04 SI |
81 | smp_cross_call(cpumask_of(cpu)); |
82 | ||
aa44ef4d SK |
83 | timeout = jiffies + (1 * HZ); |
84 | while (time_before(jiffies, timeout)) { | |
85 | if (pen_release == -1) | |
86 | break; | |
87 | } | |
88 | ||
89 | /* | |
90 | * now the secondary core is starting up let it run its | |
91 | * calibrations, then wait for it to finish | |
92 | */ | |
93 | spin_unlock(&boot_lock); | |
94 | ||
95 | return pen_release != -1 ? -ENOSYS : 0; | |
96 | } | |
97 | ||
98 | static void __init wakeup_secondary(void) | |
99 | { | |
100 | /* nobody is to be released from the pen yet */ | |
101 | pen_release = -1; | |
102 | ||
103 | /* | |
104 | * write the address of secondary startup into the backup ram register | |
105 | * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the | |
106 | * backup ram register at offset 0x1FF0, which is what boot rom code | |
107 | * is waiting for. This would wake up the secondary core from WFE | |
108 | */ | |
109 | #define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4 | |
110 | __raw_writel(virt_to_phys(u8500_secondary_startup), | |
817412d3 | 111 | __io_address(UX500_BACKUPRAM0_BASE) + |
aa44ef4d SK |
112 | U8500_CPU1_JUMPADDR_OFFSET); |
113 | ||
114 | #define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 | |
115 | __raw_writel(0xA1FEED01, | |
817412d3 | 116 | __io_address(UX500_BACKUPRAM0_BASE) + |
aa44ef4d SK |
117 | U8500_CPU1_WAKEMAGIC_OFFSET); |
118 | ||
119 | /* make sure write buffer is drained */ | |
120 | mb(); | |
121 | } | |
122 | ||
123 | /* | |
124 | * Initialise the CPU possible map early - this describes the CPUs | |
125 | * which may be present or become present in the system. | |
126 | */ | |
127 | void __init smp_init_cpus(void) | |
128 | { | |
129 | unsigned int i, ncores = get_core_count(); | |
130 | ||
131 | for (i = 0; i < ncores; i++) | |
132 | set_cpu_possible(i, true); | |
133 | } | |
134 | ||
135 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
136 | { | |
137 | unsigned int ncores = get_core_count(); | |
138 | unsigned int cpu = smp_processor_id(); | |
139 | int i; | |
140 | ||
141 | /* sanity check */ | |
142 | if (ncores == 0) { | |
143 | printk(KERN_ERR | |
144 | "U8500: strange CM count of 0? Default to 1\n"); | |
145 | ncores = 1; | |
146 | } | |
147 | ||
148 | if (ncores > num_possible_cpus()) { | |
149 | printk(KERN_WARNING | |
150 | "U8500: no. of cores (%d) greater than configured " | |
151 | "maximum of %d - clipping\n", | |
152 | ncores, num_possible_cpus()); | |
153 | ncores = num_possible_cpus(); | |
154 | } | |
155 | ||
156 | smp_store_cpu_info(cpu); | |
157 | ||
158 | /* | |
159 | * are we trying to boot more cores than exist? | |
160 | */ | |
161 | if (max_cpus > ncores) | |
162 | max_cpus = ncores; | |
163 | ||
164 | /* | |
165 | * Initialise the present map, which describes the set of CPUs | |
166 | * actually populated at the present time. | |
167 | */ | |
168 | for (i = 0; i < max_cpus; i++) | |
169 | set_cpu_present(i, true); | |
170 | ||
171 | if (max_cpus > 1) { | |
172 | /* | |
173 | * Enable the local timer or broadcast device for the | |
174 | * boot CPU, but only if we have more than one CPU. | |
175 | */ | |
176 | percpu_timer_setup(); | |
817412d3 | 177 | scu_enable(__io_address(UX500_SCU_BASE)); |
aa44ef4d SK |
178 | wakeup_secondary(); |
179 | } | |
180 | } |