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1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010-2013 | |
3 | * Author: Rickard Andersson <rickard.andersson@stericsson.com> for | |
4 | * ST-Ericsson. | |
5 | * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. | |
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6 | * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro. |
7 | * | |
1e22a8c6 LW |
8 | * License terms: GNU General Public License (GPL) version 2 |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/irqchip/arm-gic.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/io.h> | |
ead9e293 | 16 | #include <linux/suspend.h> |
1e22a8c6 LW |
17 | #include <linux/platform_data/arm-ux500-pm.h> |
18 | ||
174e7796 | 19 | #include "db8500-regs.h" |
1e22a8c6 LW |
20 | |
21 | /* ARM WFI Standby signal register */ | |
22 | #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) | |
23 | #define PRCM_ARM_WFI_STANDBY_WFI0 0x08 | |
24 | #define PRCM_ARM_WFI_STANDBY_WFI1 0x10 | |
25 | #define PRCM_IOCR (prcmu_base + 0x310) | |
26 | #define PRCM_IOCR_IOFORCE 0x1 | |
27 | ||
28 | /* Dual A9 core interrupt management unit registers */ | |
29 | #define PRCM_A9_MASK_REQ (prcmu_base + 0x328) | |
30 | #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 | |
31 | ||
32 | #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) | |
33 | #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) | |
34 | #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) | |
35 | #define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) | |
36 | #define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) | |
37 | #define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) | |
38 | #define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) | |
39 | #define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) | |
40 | #define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) | |
41 | #define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) | |
42 | ||
43 | static void __iomem *prcmu_base; | |
44 | ||
45 | /* This function decouple the gic from the prcmu */ | |
46 | int prcmu_gic_decouple(void) | |
47 | { | |
48 | u32 val = readl(PRCM_A9_MASK_REQ); | |
49 | ||
50 | /* Set bit 0 register value to 1 */ | |
51 | writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, | |
52 | PRCM_A9_MASK_REQ); | |
53 | ||
54 | /* Make sure the register is updated */ | |
55 | readl(PRCM_A9_MASK_REQ); | |
56 | ||
57 | /* Wait a few cycles for the gic mask completion */ | |
58 | udelay(1); | |
59 | ||
60 | return 0; | |
61 | } | |
62 | ||
63 | /* This function recouple the gic with the prcmu */ | |
64 | int prcmu_gic_recouple(void) | |
65 | { | |
66 | u32 val = readl(PRCM_A9_MASK_REQ); | |
67 | ||
68 | /* Set bit 0 register value to 0 */ | |
69 | writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
74 | #define PRCMU_GIC_NUMBER_REGS 5 | |
75 | ||
76 | /* | |
77 | * This function checks if there are pending irq on the gic. It only | |
78 | * makes sense if the gic has been decoupled before with the | |
79 | * db8500_prcmu_gic_decouple function. Disabling an interrupt only | |
80 | * disables the forwarding of the interrupt to any CPU interface. It | |
81 | * does not prevent the interrupt from changing state, for example | |
82 | * becoming pending, or active and pending if it is already | |
83 | * active. Hence, we have to check the interrupt is pending *and* is | |
84 | * active. | |
85 | */ | |
86 | bool prcmu_gic_pending_irq(void) | |
87 | { | |
88 | u32 pr; /* Pending register */ | |
89 | u32 er; /* Enable register */ | |
90 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); | |
91 | int i; | |
92 | ||
93 | /* 5 registers. STI & PPI not skipped */ | |
94 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { | |
95 | ||
96 | pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); | |
97 | er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
98 | ||
99 | if (pr & er) | |
100 | return true; /* There is a pending interrupt */ | |
101 | } | |
102 | ||
103 | return false; | |
104 | } | |
105 | ||
106 | /* | |
107 | * This function checks if there are pending interrupt on the | |
108 | * prcmu which has been delegated to monitor the irqs with the | |
109 | * db8500_prcmu_copy_gic_settings function. | |
110 | */ | |
111 | bool prcmu_pending_irq(void) | |
112 | { | |
113 | u32 it, im; | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { | |
117 | it = readl(PRCM_ARMITVAL31TO0 + i * 4); | |
118 | im = readl(PRCM_ARMITMSK31TO0 + i * 4); | |
119 | if (it & im) | |
120 | return true; /* There is a pending interrupt */ | |
121 | } | |
122 | ||
123 | return false; | |
124 | } | |
125 | ||
126 | /* | |
127 | * This function checks if the specified cpu is in in WFI. It's usage | |
128 | * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple | |
129 | * function. Of course passing smp_processor_id() to this function will | |
130 | * always return false... | |
131 | */ | |
132 | bool prcmu_is_cpu_in_wfi(int cpu) | |
133 | { | |
134 | return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : | |
135 | PRCM_ARM_WFI_STANDBY_WFI0; | |
136 | } | |
137 | ||
138 | /* | |
139 | * This function copies the gic SPI settings to the prcmu in order to | |
140 | * monitor them and abort/finish the retention/off sequence or state. | |
141 | */ | |
142 | int prcmu_copy_gic_settings(void) | |
143 | { | |
144 | u32 er; /* Enable register */ | |
145 | void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); | |
146 | int i; | |
147 | ||
148 | /* We skip the STI and PPI */ | |
149 | for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { | |
150 | er = readl_relaxed(dist_base + | |
151 | GIC_DIST_ENABLE_SET + (i + 1) * 4); | |
152 | writel(er, PRCM_ARMITMSK31TO0 + i * 4); | |
153 | } | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
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158 | #ifdef CONFIG_SUSPEND |
159 | static int ux500_suspend_enter(suspend_state_t state) | |
160 | { | |
161 | cpu_do_idle(); | |
162 | return 0; | |
163 | } | |
164 | ||
165 | static int ux500_suspend_valid(suspend_state_t state) | |
166 | { | |
167 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
168 | } | |
169 | ||
170 | static const struct platform_suspend_ops ux500_suspend_ops = { | |
171 | .enter = ux500_suspend_enter, | |
172 | .valid = ux500_suspend_valid, | |
173 | }; | |
174 | #define UX500_SUSPEND_OPS (&ux500_suspend_ops) | |
175 | #else | |
176 | #define UX500_SUSPEND_OPS NULL | |
177 | #endif | |
178 | ||
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179 | void __init ux500_pm_init(u32 phy_base, u32 size) |
180 | { | |
181 | prcmu_base = ioremap(phy_base, size); | |
182 | if (!prcmu_base) { | |
183 | pr_err("could not remap PRCMU for PM functions\n"); | |
184 | return; | |
185 | } | |
186 | /* | |
187 | * On watchdog reboot the GIC is in some cases decoupled. | |
188 | * This will make sure that the GIC is correctly configured. | |
189 | */ | |
190 | prcmu_gic_recouple(); | |
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191 | |
192 | /* Set up ux500 suspend callbacks. */ | |
193 | suspend_set_ops(UX500_SUSPEND_OPS); | |
1e22a8c6 | 194 | } |