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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-versatile/core.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/dma-mapping.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 | 25 | #include <linux/interrupt.h> |
3ba7222a GL |
26 | #include <linux/irqdomain.h> |
27 | #include <linux/of_address.h> | |
28 | #include <linux/of_platform.h> | |
a62c80e5 RK |
29 | #include <linux/amba/bus.h> |
30 | #include <linux/amba/clcd.h> | |
11c32d7b | 31 | #include <linux/platform_data/video-clcd-versatile.h> |
bbeddc43 | 32 | #include <linux/amba/pl061.h> |
6ef297f8 | 33 | #include <linux/amba/mmci.h> |
ef6f4b12 | 34 | #include <linux/amba/pl022.h> |
fced80c7 | 35 | #include <linux/io.h> |
9e47b8bf | 36 | #include <linux/irqchip/arm-vic.h> |
2389d501 | 37 | #include <linux/irqchip/versatile-fpga.h> |
5a0e3ad6 | 38 | #include <linux/gfp.h> |
6d803ba7 | 39 | #include <linux/clkdev.h> |
68c0e38c | 40 | #include <linux/mtd/physmap.h> |
e3e92a7b | 41 | #include <linux/bitops.h> |
7b6d864b | 42 | #include <linux/reboot.h> |
1da177e4 | 43 | |
0b7402dc SH |
44 | #include <clocksource/timer-sp804.h> |
45 | ||
1da177e4 | 46 | #include <asm/irq.h> |
c5a0adb5 | 47 | #include <asm/hardware/icst.h> |
dc5bc8f1 | 48 | #include <asm/mach-types.h> |
1da177e4 LT |
49 | |
50 | #include <asm/mach/arch.h> | |
1da177e4 LT |
51 | #include <asm/mach/irq.h> |
52 | #include <asm/mach/time.h> | |
53 | #include <asm/mach/map.h> | |
a285edcf RK |
54 | #include <mach/hardware.h> |
55 | #include <mach/platform.h> | |
1da177e4 | 56 | |
1da0c89c RK |
57 | #include <plat/sched_clock.h> |
58 | ||
1da177e4 | 59 | #include "core.h" |
1da177e4 LT |
60 | |
61 | /* | |
62 | * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx | |
63 | * is the (PA >> 12). | |
64 | * | |
65 | * Setup a VA for the Versatile Vectored Interrupt Controller. | |
66 | */ | |
2ad4f86b AV |
67 | #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) |
68 | #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) | |
1da177e4 | 69 | |
e3e92a7b LW |
70 | /* These PIC IRQs are valid in each configuration */ |
71 | #define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \ | |
72 | BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \ | |
73 | BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \ | |
74 | BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \ | |
75 | BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \ | |
76 | BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \ | |
77 | BIT(SIC_INT_PCI3) | |
1da177e4 LT |
78 | #if 1 |
79 | #define IRQ_MMCI0A IRQ_VICSOURCE22 | |
80 | #define IRQ_AACI IRQ_VICSOURCE24 | |
81 | #define IRQ_ETH IRQ_VICSOURCE25 | |
82 | #define PIC_MASK 0xFFD00000 | |
e3e92a7b | 83 | #define PIC_VALID PIC_VALID_ALL |
1da177e4 LT |
84 | #else |
85 | #define IRQ_MMCI0A IRQ_SIC_MMCI0A | |
86 | #define IRQ_AACI IRQ_SIC_AACI | |
87 | #define IRQ_ETH IRQ_SIC_ETH | |
88 | #define PIC_MASK 0 | |
e3e92a7b LW |
89 | #define PIC_VALID PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \ |
90 | BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \ | |
91 | BIT(SIC_INT_ETH) | |
1da177e4 LT |
92 | #endif |
93 | ||
3ba7222a GL |
94 | /* Lookup table for finding a DT node that represents the vic instance */ |
95 | static const struct of_device_id vic_of_match[] __initconst = { | |
96 | { .compatible = "arm,versatile-vic", }, | |
97 | {} | |
98 | }; | |
99 | ||
100 | static const struct of_device_id sic_of_match[] __initconst = { | |
101 | { .compatible = "arm,versatile-sic", }, | |
102 | {} | |
103 | }; | |
104 | ||
1da177e4 LT |
105 | void __init versatile_init_irq(void) |
106 | { | |
75294957 GL |
107 | struct device_node *np; |
108 | ||
109 | np = of_find_matching_node_by_address(NULL, vic_of_match, | |
110 | VERSATILE_VIC_BASE); | |
e641b987 | 111 | __vic_init(VA_VIC_BASE, 0, IRQ_VIC_START, ~0, 0, np); |
1da177e4 | 112 | |
1da177e4 LT |
113 | writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); |
114 | ||
3108e6ab LW |
115 | np = of_find_matching_node_by_address(NULL, sic_of_match, |
116 | VERSATILE_SIC_BASE); | |
117 | ||
118 | fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START, | |
e3e92a7b | 119 | IRQ_VICSOURCE31, PIC_VALID, np); |
1da177e4 LT |
120 | |
121 | /* | |
122 | * Interrupts on secondary controller from 0 to 8 are routed to | |
123 | * source 31 on PIC. | |
124 | * Interrupts from 21 to 31 are routed directly to the VIC on | |
125 | * the corresponding number on primary controller. This is controlled | |
126 | * by setting PIC_ENABLEx. | |
127 | */ | |
128 | writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE); | |
129 | } | |
130 | ||
060fd1be | 131 | static struct map_desc versatile_io_desc[] __initdata __maybe_unused = { |
1311521f DS |
132 | { |
133 | .virtual = IO_ADDRESS(VERSATILE_SYS_BASE), | |
134 | .pfn = __phys_to_pfn(VERSATILE_SYS_BASE), | |
135 | .length = SZ_4K, | |
136 | .type = MT_DEVICE | |
137 | }, { | |
138 | .virtual = IO_ADDRESS(VERSATILE_SIC_BASE), | |
139 | .pfn = __phys_to_pfn(VERSATILE_SIC_BASE), | |
140 | .length = SZ_4K, | |
141 | .type = MT_DEVICE | |
142 | }, { | |
143 | .virtual = IO_ADDRESS(VERSATILE_VIC_BASE), | |
144 | .pfn = __phys_to_pfn(VERSATILE_VIC_BASE), | |
145 | .length = SZ_4K, | |
146 | .type = MT_DEVICE | |
147 | }, { | |
148 | .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE), | |
149 | .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE), | |
150 | .length = SZ_4K * 9, | |
151 | .type = MT_DEVICE | |
152 | }, | |
1da177e4 | 153 | #ifdef CONFIG_MACH_VERSATILE_AB |
1311521f | 154 | { |
1311521f DS |
155 | .virtual = IO_ADDRESS(VERSATILE_IB2_BASE), |
156 | .pfn = __phys_to_pfn(VERSATILE_IB2_BASE), | |
157 | .length = SZ_64M, | |
158 | .type = MT_DEVICE | |
159 | }, | |
1da177e4 LT |
160 | #endif |
161 | #ifdef CONFIG_DEBUG_LL | |
1311521f DS |
162 | { |
163 | .virtual = IO_ADDRESS(VERSATILE_UART0_BASE), | |
164 | .pfn = __phys_to_pfn(VERSATILE_UART0_BASE), | |
165 | .length = SZ_4K, | |
166 | .type = MT_DEVICE | |
167 | }, | |
1da177e4 | 168 | #endif |
c0da085a | 169 | #ifdef CONFIG_PCI |
1311521f DS |
170 | { |
171 | .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE), | |
172 | .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE), | |
173 | .length = SZ_4K, | |
174 | .type = MT_DEVICE | |
175 | }, { | |
399ad77b | 176 | .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE, |
1311521f DS |
177 | .pfn = __phys_to_pfn(VERSATILE_PCI_BASE), |
178 | .length = VERSATILE_PCI_BASE_SIZE, | |
179 | .type = MT_DEVICE | |
180 | }, { | |
399ad77b | 181 | .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE, |
1311521f DS |
182 | .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), |
183 | .length = VERSATILE_PCI_CFG_BASE_SIZE, | |
184 | .type = MT_DEVICE | |
1311521f | 185 | }, |
c0da085a | 186 | #endif |
1da177e4 LT |
187 | }; |
188 | ||
189 | void __init versatile_map_io(void) | |
190 | { | |
191 | iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc)); | |
192 | } | |
193 | ||
1da177e4 | 194 | |
2ad4f86b | 195 | #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) |
1da177e4 | 196 | |
667f390b | 197 | static void versatile_flash_set_vpp(struct platform_device *pdev, int on) |
1da177e4 LT |
198 | { |
199 | u32 val; | |
200 | ||
201 | val = __raw_readl(VERSATILE_FLASHCTRL); | |
202 | if (on) | |
203 | val |= VERSATILE_FLASHPROG_FLVPPEN; | |
204 | else | |
205 | val &= ~VERSATILE_FLASHPROG_FLVPPEN; | |
206 | __raw_writel(val, VERSATILE_FLASHCTRL); | |
207 | } | |
208 | ||
68c0e38c | 209 | static struct physmap_flash_data versatile_flash_data = { |
1da177e4 | 210 | .width = 4, |
1da177e4 LT |
211 | .set_vpp = versatile_flash_set_vpp, |
212 | }; | |
213 | ||
214 | static struct resource versatile_flash_resource = { | |
215 | .start = VERSATILE_FLASH_BASE, | |
a0c5a645 | 216 | .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1, |
1da177e4 LT |
217 | .flags = IORESOURCE_MEM, |
218 | }; | |
219 | ||
220 | static struct platform_device versatile_flash_device = { | |
68c0e38c | 221 | .name = "physmap-flash", |
1da177e4 LT |
222 | .id = 0, |
223 | .dev = { | |
224 | .platform_data = &versatile_flash_data, | |
225 | }, | |
226 | .num_resources = 1, | |
227 | .resource = &versatile_flash_resource, | |
228 | }; | |
229 | ||
230 | static struct resource smc91x_resources[] = { | |
231 | [0] = { | |
232 | .start = VERSATILE_ETH_BASE, | |
233 | .end = VERSATILE_ETH_BASE + SZ_64K - 1, | |
234 | .flags = IORESOURCE_MEM, | |
235 | }, | |
236 | [1] = { | |
237 | .start = IRQ_ETH, | |
238 | .end = IRQ_ETH, | |
239 | .flags = IORESOURCE_IRQ, | |
240 | }, | |
241 | }; | |
242 | ||
243 | static struct platform_device smc91x_device = { | |
244 | .name = "smc91x", | |
245 | .id = 0, | |
246 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
247 | .resource = smc91x_resources, | |
248 | }; | |
249 | ||
6b65cd74 RK |
250 | static struct resource versatile_i2c_resource = { |
251 | .start = VERSATILE_I2C_BASE, | |
252 | .end = VERSATILE_I2C_BASE + SZ_4K - 1, | |
253 | .flags = IORESOURCE_MEM, | |
254 | }; | |
255 | ||
256 | static struct platform_device versatile_i2c_device = { | |
257 | .name = "versatile-i2c", | |
533ad5e6 | 258 | .id = 0, |
6b65cd74 RK |
259 | .num_resources = 1, |
260 | .resource = &versatile_i2c_resource, | |
261 | }; | |
262 | ||
533ad5e6 CM |
263 | static struct i2c_board_info versatile_i2c_board_info[] = { |
264 | { | |
64e8be6e | 265 | I2C_BOARD_INFO("ds1338", 0xd0 >> 1), |
533ad5e6 CM |
266 | }, |
267 | }; | |
268 | ||
269 | static int __init versatile_i2c_init(void) | |
270 | { | |
271 | return i2c_register_board_info(0, versatile_i2c_board_info, | |
272 | ARRAY_SIZE(versatile_i2c_board_info)); | |
273 | } | |
274 | arch_initcall(versatile_i2c_init); | |
275 | ||
2ad4f86b | 276 | #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) |
1da177e4 LT |
277 | |
278 | unsigned int mmc_status(struct device *dev) | |
279 | { | |
280 | struct amba_device *adev = container_of(dev, struct amba_device, dev); | |
281 | u32 mask; | |
282 | ||
283 | if (adev->res.start == VERSATILE_MMCI0_BASE) | |
284 | mask = 1; | |
285 | else | |
286 | mask = 2; | |
287 | ||
288 | return readl(VERSATILE_SYSMCI) & mask; | |
289 | } | |
290 | ||
6ef297f8 | 291 | static struct mmci_platform_data mmc0_plat_data = { |
1da177e4 LT |
292 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
293 | .status = mmc_status, | |
7fb2bbf4 RK |
294 | .gpio_wp = -1, |
295 | .gpio_cd = -1, | |
1da177e4 LT |
296 | }; |
297 | ||
e2823266 | 298 | static struct resource char_lcd_resources[] = { |
d161edfb LW |
299 | { |
300 | .start = VERSATILE_CHAR_LCD_BASE, | |
301 | .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1), | |
302 | .flags = IORESOURCE_MEM, | |
303 | }, | |
304 | }; | |
305 | ||
306 | static struct platform_device char_lcd_device = { | |
307 | .name = "arm-charlcd", | |
308 | .id = -1, | |
309 | .num_resources = ARRAY_SIZE(char_lcd_resources), | |
310 | .resource = char_lcd_resources, | |
311 | }; | |
312 | ||
e4ecf2bd LW |
313 | static struct resource leds_resources[] = { |
314 | { | |
315 | .start = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET, | |
316 | .end = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET + 4, | |
317 | .flags = IORESOURCE_MEM, | |
318 | }, | |
319 | }; | |
320 | ||
321 | static struct platform_device leds_device = { | |
322 | .name = "versatile-leds", | |
323 | .id = -1, | |
324 | .num_resources = ARRAY_SIZE(leds_resources), | |
325 | .resource = leds_resources, | |
326 | }; | |
327 | ||
1da177e4 LT |
328 | /* |
329 | * Clock handling | |
330 | */ | |
39c0cb02 | 331 | static const struct icst_params versatile_oscvco_params = { |
64fceb1d | 332 | .ref = 24000000, |
4de2edbd | 333 | .vco_max = ICST307_VCO_MAX, |
e73a46a3 | 334 | .vco_min = ICST307_VCO_MIN, |
1da177e4 LT |
335 | .vd_min = 4 + 8, |
336 | .vd_max = 511 + 8, | |
337 | .rd_min = 1 + 2, | |
338 | .rd_max = 127 + 2, | |
232eaf7f RK |
339 | .s2div = icst307_s2div, |
340 | .idx2s = icst307_idx2s, | |
1da177e4 LT |
341 | }; |
342 | ||
39c0cb02 | 343 | static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco) |
1da177e4 | 344 | { |
d1914c7e | 345 | void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET; |
1da177e4 LT |
346 | u32 val; |
347 | ||
d1914c7e | 348 | val = readl(clk->vcoreg) & ~0x7ffff; |
1da177e4 LT |
349 | val |= vco.v | (vco.r << 9) | (vco.s << 16); |
350 | ||
351 | writel(0xa05f, sys_lock); | |
d1914c7e | 352 | writel(val, clk->vcoreg); |
1da177e4 LT |
353 | writel(0, sys_lock); |
354 | } | |
355 | ||
9bf5b2ef RK |
356 | static const struct clk_ops osc4_clk_ops = { |
357 | .round = icst_clk_round, | |
358 | .set = icst_clk_set, | |
359 | .setvco = versatile_oscvco_set, | |
360 | }; | |
361 | ||
71a06da0 | 362 | static struct clk osc4_clk = { |
9bf5b2ef | 363 | .ops = &osc4_clk_ops, |
1da177e4 | 364 | .params = &versatile_oscvco_params, |
71a06da0 RK |
365 | }; |
366 | ||
367 | /* | |
368 | * These are fixed clocks. | |
369 | */ | |
370 | static struct clk ref24_clk = { | |
371 | .rate = 24000000, | |
372 | }; | |
373 | ||
7ff550de RK |
374 | static struct clk sp804_clk = { |
375 | .rate = 1000000, | |
376 | }; | |
377 | ||
3126c7bc RK |
378 | static struct clk dummy_apb_pclk; |
379 | ||
982db663 | 380 | static struct clk_lookup lookups[] = { |
3126c7bc RK |
381 | { /* AMBA bus clock */ |
382 | .con_id = "apb_pclk", | |
383 | .clk = &dummy_apb_pclk, | |
384 | }, { /* UART0 */ | |
71a06da0 RK |
385 | .dev_id = "dev:f1", |
386 | .clk = &ref24_clk, | |
387 | }, { /* UART1 */ | |
388 | .dev_id = "dev:f2", | |
389 | .clk = &ref24_clk, | |
390 | }, { /* UART2 */ | |
391 | .dev_id = "dev:f3", | |
392 | .clk = &ref24_clk, | |
393 | }, { /* UART3 */ | |
394 | .dev_id = "fpga:09", | |
395 | .clk = &ref24_clk, | |
396 | }, { /* KMI0 */ | |
397 | .dev_id = "fpga:06", | |
398 | .clk = &ref24_clk, | |
399 | }, { /* KMI1 */ | |
400 | .dev_id = "fpga:07", | |
401 | .clk = &ref24_clk, | |
402 | }, { /* MMC0 */ | |
403 | .dev_id = "fpga:05", | |
404 | .clk = &ref24_clk, | |
405 | }, { /* MMC1 */ | |
406 | .dev_id = "fpga:0b", | |
407 | .clk = &ref24_clk, | |
ef6f4b12 LW |
408 | }, { /* SSP */ |
409 | .dev_id = "dev:f4", | |
410 | .clk = &ref24_clk, | |
71a06da0 RK |
411 | }, { /* CLCD */ |
412 | .dev_id = "dev:20", | |
413 | .clk = &osc4_clk, | |
7ff550de RK |
414 | }, { /* SP804 timers */ |
415 | .dev_id = "sp804", | |
416 | .clk = &sp804_clk, | |
417 | }, | |
1da177e4 LT |
418 | }; |
419 | ||
420 | /* | |
421 | * CLCD support. | |
422 | */ | |
423 | #define SYS_CLCD_MODE_MASK (3 << 0) | |
424 | #define SYS_CLCD_MODE_888 (0 << 0) | |
425 | #define SYS_CLCD_MODE_5551 (1 << 0) | |
426 | #define SYS_CLCD_MODE_565_RLSB (2 << 0) | |
427 | #define SYS_CLCD_MODE_565_BLSB (3 << 0) | |
428 | #define SYS_CLCD_NLCDIOON (1 << 2) | |
429 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) | |
430 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) | |
431 | #define SYS_CLCD_ID_MASK (0x1f << 8) | |
432 | #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) | |
433 | #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) | |
434 | #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) | |
435 | #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) | |
436 | #define SYS_CLCD_ID_VGA (0x1f << 8) | |
437 | ||
3414ba8c | 438 | static bool is_sanyo_2_5_lcd; |
1da177e4 LT |
439 | |
440 | /* | |
441 | * Disable all display connectors on the interface module. | |
442 | */ | |
443 | static void versatile_clcd_disable(struct clcd_fb *fb) | |
444 | { | |
2ad4f86b | 445 | void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; |
1da177e4 LT |
446 | u32 val; |
447 | ||
448 | val = readl(sys_clcd); | |
449 | val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | |
450 | writel(val, sys_clcd); | |
451 | ||
452 | #ifdef CONFIG_MACH_VERSATILE_AB | |
453 | /* | |
454 | * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off | |
455 | */ | |
3414ba8c | 456 | if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { |
2ad4f86b | 457 | void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); |
1da177e4 LT |
458 | unsigned long ctrl; |
459 | ||
460 | ctrl = readl(versatile_ib2_ctrl); | |
461 | ctrl &= ~0x01; | |
462 | writel(ctrl, versatile_ib2_ctrl); | |
463 | } | |
464 | #endif | |
465 | } | |
466 | ||
467 | /* | |
468 | * Enable the relevant connector on the interface module. | |
469 | */ | |
470 | static void versatile_clcd_enable(struct clcd_fb *fb) | |
471 | { | |
9728c1b6 | 472 | struct fb_var_screeninfo *var = &fb->fb.var; |
2ad4f86b | 473 | void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; |
1da177e4 LT |
474 | u32 val; |
475 | ||
476 | val = readl(sys_clcd); | |
477 | val &= ~SYS_CLCD_MODE_MASK; | |
478 | ||
9728c1b6 | 479 | switch (var->green.length) { |
1da177e4 LT |
480 | case 5: |
481 | val |= SYS_CLCD_MODE_5551; | |
482 | break; | |
483 | case 6: | |
9728c1b6 RK |
484 | if (var->red.offset == 0) |
485 | val |= SYS_CLCD_MODE_565_RLSB; | |
486 | else | |
487 | val |= SYS_CLCD_MODE_565_BLSB; | |
1da177e4 LT |
488 | break; |
489 | case 8: | |
490 | val |= SYS_CLCD_MODE_888; | |
491 | break; | |
492 | } | |
493 | ||
494 | /* | |
495 | * Set the MUX | |
496 | */ | |
497 | writel(val, sys_clcd); | |
498 | ||
499 | /* | |
500 | * And now enable the PSUs | |
501 | */ | |
502 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | |
503 | writel(val, sys_clcd); | |
504 | ||
505 | #ifdef CONFIG_MACH_VERSATILE_AB | |
506 | /* | |
507 | * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on | |
508 | */ | |
3414ba8c | 509 | if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) { |
2ad4f86b | 510 | void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); |
1da177e4 LT |
511 | unsigned long ctrl; |
512 | ||
513 | ctrl = readl(versatile_ib2_ctrl); | |
514 | ctrl |= 0x01; | |
515 | writel(ctrl, versatile_ib2_ctrl); | |
516 | } | |
517 | #endif | |
518 | } | |
519 | ||
3414ba8c RK |
520 | /* |
521 | * Detect which LCD panel is connected, and return the appropriate | |
522 | * clcd_panel structure. Note: we do not have any information on | |
523 | * the required timings for the 8.4in panel, so we presently assume | |
524 | * VGA timings. | |
525 | */ | |
1da177e4 LT |
526 | static int versatile_clcd_setup(struct clcd_fb *fb) |
527 | { | |
3414ba8c RK |
528 | void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; |
529 | const char *panel_name; | |
530 | u32 val; | |
1da177e4 | 531 | |
3414ba8c | 532 | is_sanyo_2_5_lcd = false; |
1da177e4 | 533 | |
3414ba8c RK |
534 | val = readl(sys_clcd) & SYS_CLCD_ID_MASK; |
535 | if (val == SYS_CLCD_ID_SANYO_3_8) | |
536 | panel_name = "Sanyo TM38QV67A02A"; | |
537 | else if (val == SYS_CLCD_ID_SANYO_2_5) { | |
538 | panel_name = "Sanyo QVGA Portrait"; | |
539 | is_sanyo_2_5_lcd = true; | |
540 | } else if (val == SYS_CLCD_ID_EPSON_2_2) | |
541 | panel_name = "Epson L2F50113T00"; | |
542 | else if (val == SYS_CLCD_ID_VGA) | |
543 | panel_name = "VGA"; | |
544 | else { | |
545 | printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", | |
546 | val); | |
547 | panel_name = "VGA"; | |
1da177e4 LT |
548 | } |
549 | ||
3414ba8c RK |
550 | fb->panel = versatile_clcd_get_panel(panel_name); |
551 | if (!fb->panel) | |
552 | return -EINVAL; | |
1da177e4 | 553 | |
3414ba8c | 554 | return versatile_clcd_setup_dma(fb, SZ_1M); |
1da177e4 LT |
555 | } |
556 | ||
9728c1b6 RK |
557 | static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs) |
558 | { | |
559 | clcdfb_decode(fb, regs); | |
560 | ||
561 | /* Always clear BGR for RGB565: we do the routing externally */ | |
562 | if (fb->fb.var.green.length == 6) | |
563 | regs->cntl &= ~CNTL_BGR; | |
564 | } | |
565 | ||
1da177e4 LT |
566 | static struct clcd_board clcd_plat_data = { |
567 | .name = "Versatile", | |
3414ba8c | 568 | .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, |
1da177e4 | 569 | .check = clcdfb_check, |
9728c1b6 | 570 | .decode = versatile_clcd_decode, |
1da177e4 LT |
571 | .disable = versatile_clcd_disable, |
572 | .enable = versatile_clcd_enable, | |
573 | .setup = versatile_clcd_setup, | |
3414ba8c RK |
574 | .mmap = versatile_clcd_mmap_dma, |
575 | .remove = versatile_clcd_remove_dma, | |
1da177e4 LT |
576 | }; |
577 | ||
bbeddc43 RK |
578 | static struct pl061_platform_data gpio0_plat_data = { |
579 | .gpio_base = 0, | |
580 | .irq_base = IRQ_GPIO0_START, | |
581 | }; | |
582 | ||
583 | static struct pl061_platform_data gpio1_plat_data = { | |
584 | .gpio_base = 8, | |
585 | .irq_base = IRQ_GPIO1_START, | |
586 | }; | |
587 | ||
bfc305af LW |
588 | static struct pl061_platform_data gpio2_plat_data = { |
589 | .gpio_base = 16, | |
590 | .irq_base = IRQ_GPIO2_START, | |
591 | }; | |
592 | ||
593 | static struct pl061_platform_data gpio3_plat_data = { | |
594 | .gpio_base = 24, | |
595 | .irq_base = IRQ_GPIO3_START, | |
596 | }; | |
597 | ||
ef6f4b12 LW |
598 | static struct pl022_ssp_controller ssp0_plat_data = { |
599 | .bus_id = 0, | |
600 | .enable_dma = 0, | |
601 | .num_chipselect = 1, | |
602 | }; | |
603 | ||
0dada61a | 604 | #define AACI_IRQ { IRQ_AACI } |
1da177e4 | 605 | #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } |
0dada61a RK |
606 | #define KMI0_IRQ { IRQ_SIC_KMI0 } |
607 | #define KMI1_IRQ { IRQ_SIC_KMI1 } | |
1da177e4 LT |
608 | |
609 | /* | |
610 | * These devices are connected directly to the multi-layer AHB switch | |
611 | */ | |
0dada61a RK |
612 | #define SMC_IRQ { } |
613 | #define MPMC_IRQ { } | |
614 | #define CLCD_IRQ { IRQ_CLCDINT } | |
615 | #define DMAC_IRQ { IRQ_DMAINT } | |
1da177e4 LT |
616 | |
617 | /* | |
618 | * These devices are connected via the core APB bridge | |
619 | */ | |
0dada61a RK |
620 | #define SCTL_IRQ { } |
621 | #define WATCHDOG_IRQ { IRQ_WDOGINT } | |
622 | #define GPIO0_IRQ { IRQ_GPIOINT0 } | |
623 | #define GPIO1_IRQ { IRQ_GPIOINT1 } | |
bfc305af LW |
624 | #define GPIO2_IRQ { IRQ_GPIOINT2 } |
625 | #define GPIO3_IRQ { IRQ_GPIOINT3 } | |
0dada61a | 626 | #define RTC_IRQ { IRQ_RTCINT } |
1da177e4 LT |
627 | |
628 | /* | |
629 | * These devices are connected via the DMA APB bridge | |
630 | */ | |
0dada61a RK |
631 | #define SCI_IRQ { IRQ_SCIINT } |
632 | #define UART0_IRQ { IRQ_UARTINT0 } | |
633 | #define UART1_IRQ { IRQ_UARTINT1 } | |
634 | #define UART2_IRQ { IRQ_UARTINT2 } | |
635 | #define SSP_IRQ { IRQ_SSPINT } | |
1da177e4 LT |
636 | |
637 | /* FPGA Primecells */ | |
8f5088b6 RK |
638 | APB_DEVICE(aaci, "fpga:04", AACI, NULL); |
639 | APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data); | |
640 | APB_DEVICE(kmi0, "fpga:06", KMI0, NULL); | |
641 | APB_DEVICE(kmi1, "fpga:07", KMI1, NULL); | |
1da177e4 LT |
642 | |
643 | /* DevChip Primecells */ | |
8f5088b6 RK |
644 | AHB_DEVICE(smc, "dev:00", SMC, NULL); |
645 | AHB_DEVICE(mpmc, "dev:10", MPMC, NULL); | |
646 | AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); | |
647 | AHB_DEVICE(dmac, "dev:30", DMAC, NULL); | |
648 | APB_DEVICE(sctl, "dev:e0", SCTL, NULL); | |
649 | APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); | |
650 | APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data); | |
651 | APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); | |
bfc305af LW |
652 | APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); |
653 | APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data); | |
8f5088b6 RK |
654 | APB_DEVICE(rtc, "dev:e8", RTC, NULL); |
655 | APB_DEVICE(sci0, "dev:f0", SCI, NULL); | |
656 | APB_DEVICE(uart0, "dev:f1", UART0, NULL); | |
657 | APB_DEVICE(uart1, "dev:f2", UART1, NULL); | |
658 | APB_DEVICE(uart2, "dev:f3", UART2, NULL); | |
659 | APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data); | |
1da177e4 LT |
660 | |
661 | static struct amba_device *amba_devs[] __initdata = { | |
662 | &dmac_device, | |
663 | &uart0_device, | |
664 | &uart1_device, | |
665 | &uart2_device, | |
666 | &smc_device, | |
667 | &mpmc_device, | |
668 | &clcd_device, | |
669 | &sctl_device, | |
670 | &wdog_device, | |
671 | &gpio0_device, | |
672 | &gpio1_device, | |
bfc305af LW |
673 | &gpio2_device, |
674 | &gpio3_device, | |
1da177e4 LT |
675 | &rtc_device, |
676 | &sci0_device, | |
677 | &ssp0_device, | |
678 | &aaci_device, | |
679 | &mmc0_device, | |
680 | &kmi0_device, | |
681 | &kmi1_device, | |
682 | }; | |
683 | ||
3ba7222a GL |
684 | #ifdef CONFIG_OF |
685 | /* | |
686 | * Lookup table for attaching a specific name and platform_data pointer to | |
687 | * devices as they get created by of_platform_populate(). Ideally this table | |
688 | * would not exist, but the current clock implementation depends on some devices | |
689 | * having a specific name. | |
690 | */ | |
691 | struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = { | |
d12379ac | 692 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data), |
3ba7222a GL |
693 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL), |
694 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL), | |
695 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL), | |
d12379ac | 696 | /* FIXME: this is buggy, the platform data is needed for this MMC instance too */ |
3ba7222a GL |
697 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL), |
698 | ||
699 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data), | |
700 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL), | |
701 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL), | |
702 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL), | |
d12379ac | 703 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data), |
3ba7222a GL |
704 | |
705 | #if 0 | |
706 | /* | |
707 | * These entries are unnecessary because no clocks referencing | |
708 | * them. I've left them in for now as place holders in case | |
709 | * any of them need to be added back, but they should be | |
710 | * removed before actually committing this patch. --gcl | |
711 | */ | |
712 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL), | |
713 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL), | |
714 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL), | |
715 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL), | |
716 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL), | |
717 | ||
718 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL), | |
719 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL), | |
720 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL), | |
721 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL), | |
722 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL), | |
723 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL), | |
724 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL), | |
725 | OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL), | |
726 | #endif | |
727 | {} | |
728 | }; | |
729 | #endif | |
730 | ||
7b6d864b | 731 | void versatile_restart(enum reboot_mode mode, const char *cmd) |
b56a7c6b RK |
732 | { |
733 | void __iomem *sys = __io_address(VERSATILE_SYS_BASE); | |
734 | u32 val; | |
735 | ||
736 | val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET); | |
737 | val |= 0x105; | |
738 | ||
739 | __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET); | |
740 | __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET); | |
741 | __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET); | |
742 | } | |
743 | ||
ad3bb19c RK |
744 | /* Early initializations */ |
745 | void __init versatile_init_early(void) | |
1da177e4 | 746 | { |
818270d5 | 747 | u32 val; |
ad3bb19c | 748 | void __iomem *sys = __io_address(VERSATILE_SYS_BASE); |
d1914c7e | 749 | |
ad3bb19c | 750 | osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET; |
0a0300dc | 751 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
1da177e4 | 752 | |
ad3bb19c | 753 | versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000); |
818270d5 RH |
754 | |
755 | /* | |
756 | * set clock frequency: | |
757 | * VERSATILE_REFCLK is 32KHz | |
758 | * VERSATILE_TIMCLK is 1MHz | |
759 | */ | |
760 | val = readl(__io_address(VERSATILE_SCTL_BASE)); | |
761 | writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | | |
762 | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | | |
763 | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | | |
764 | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, | |
765 | __io_address(VERSATILE_SCTL_BASE)); | |
ad3bb19c RK |
766 | } |
767 | ||
768 | void __init versatile_init(void) | |
769 | { | |
770 | int i; | |
771 | ||
1da177e4 | 772 | platform_device_register(&versatile_flash_device); |
6b65cd74 | 773 | platform_device_register(&versatile_i2c_device); |
1da177e4 | 774 | platform_device_register(&smc91x_device); |
d161edfb | 775 | platform_device_register(&char_lcd_device); |
e4ecf2bd | 776 | platform_device_register(&leds_device); |
1da177e4 LT |
777 | |
778 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | |
779 | struct amba_device *d = amba_devs[i]; | |
780 | amba_device_register(d, &iomem_resource); | |
781 | } | |
1da177e4 LT |
782 | } |
783 | ||
784 | /* | |
785 | * Where is the timer (VA)? | |
786 | */ | |
2ad4f86b AV |
787 | #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE) |
788 | #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20) | |
789 | #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE) | |
790 | #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20) | |
b49c87c2 | 791 | |
1da177e4 LT |
792 | /* |
793 | * Set up timer interrupt, and return the current time in seconds. | |
794 | */ | |
6bb27d73 | 795 | void __init versatile_timer_init(void) |
1da177e4 | 796 | { |
1da177e4 LT |
797 | |
798 | /* | |
799 | * Initialise to a known state (all timers off) | |
800 | */ | |
1e5f0519 SH |
801 | sp804_timer_disable(TIMER0_VA_BASE); |
802 | sp804_timer_disable(TIMER1_VA_BASE); | |
803 | sp804_timer_disable(TIMER2_VA_BASE); | |
804 | sp804_timer_disable(TIMER3_VA_BASE); | |
b720f732 | 805 | |
fb593cf3 | 806 | sp804_clocksource_init(TIMER3_VA_BASE, "timer3"); |
57cc4f7d | 807 | sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0"); |
1da177e4 | 808 | } |