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ARM: mm: introduce present, faulting entries for PAGE_NONE
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
1da177e4
LT		 21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
d052d1be 24#include <linux/platform_device.h>
1da177e4 25#include <linux/interrupt.h>
3ba7222a
GL		 26#include <linux/irqdomain.h>
27#include <linux/of_address.h>
28#include <linux/of_platform.h>
a62c80e5
RK		 29#include <linux/amba/bus.h>
30#include <linux/amba/clcd.h>
bbeddc43 31#include <linux/amba/pl061.h>
6ef297f8 32#include <linux/amba/mmci.h>
ef6f4b12 33#include <linux/amba/pl022.h>
fced80c7 34#include <linux/io.h>
5a0e3ad6 35#include <linux/gfp.h>
6d803ba7 36#include <linux/clkdev.h>
68c0e38c 37#include <linux/mtd/physmap.h>
1da177e4 38
1da177e4 39#include <asm/irq.h>
b720f732 40#include <asm/hardware/arm_timer.h>
c5a0adb5 41#include <asm/hardware/icst.h>
fa0fe48f 42#include <asm/hardware/vic.h>
dc5bc8f1 43#include <asm/mach-types.h>
1da177e4
LT		 44
45#include <asm/mach/arch.h>
1da177e4
LT		 46#include <asm/mach/irq.h>
47#include <asm/mach/time.h>
48#include <asm/mach/map.h>
a285edcf
RK		 49#include <mach/hardware.h>
50#include <mach/platform.h>
8a9618f5 51#include <asm/hardware/timer-sp.h>
1da177e4 52
3414ba8c 53#include <plat/clcd.h>
c41b16f8 54#include <plat/fpga-irq.h>
1da0c89c
RK		 55#include <plat/sched_clock.h>
56
1da177e4 57#include "core.h"
1da177e4
LT		 58
59/*
60 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
61 * is the (PA >> 12).
62 *
63 * Setup a VA for the Versatile Vectored Interrupt Controller.
64 */
2ad4f86b
AV		 65#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
66#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4 67
1da177e4
LT		 68#if 1
69#define IRQ_MMCI0A IRQ_VICSOURCE22
70#define IRQ_AACI IRQ_VICSOURCE24
71#define IRQ_ETH IRQ_VICSOURCE25
72#define PIC_MASK 0xFFD00000
73#else
74#define IRQ_MMCI0A IRQ_SIC_MMCI0A
75#define IRQ_AACI IRQ_SIC_AACI
76#define IRQ_ETH IRQ_SIC_ETH
77#define PIC_MASK 0
78#endif
79
3ba7222a
GL		 80/* Lookup table for finding a DT node that represents the vic instance */
81static const struct of_device_id vic_of_match[] __initconst = {
82 { .compatible = "arm,versatile-vic", },
83 {}
84};
85
86static const struct of_device_id sic_of_match[] __initconst = {
87 { .compatible = "arm,versatile-sic", },
88 {}
89};
90
1da177e4
LT		 91void __init versatile_init_irq(void)
92{
75294957
GL		 93 struct device_node *np;
94
95 np = of_find_matching_node_by_address(NULL, vic_of_match,
96 VERSATILE_VIC_BASE);
97 __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
1da177e4 98
1da177e4
LT		 99 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
100
3108e6ab
LW		 101 np = of_find_matching_node_by_address(NULL, sic_of_match,
102 VERSATILE_SIC_BASE);
103
104 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
105 IRQ_VICSOURCE31, ~PIC_MASK, np);
1da177e4
LT		 106
107 /*
108 * Interrupts on secondary controller from 0 to 8 are routed to
109 * source 31 on PIC.
110 * Interrupts from 21 to 31 are routed directly to the VIC on
111 * the corresponding number on primary controller. This is controlled
112 * by setting PIC_ENABLEx.
113 */
114 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
115}
116
117static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 118 {
119 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
120 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
121 .length = SZ_4K,
122 .type = MT_DEVICE
123 }, {
124 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
125 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
126 .length = SZ_4K,
127 .type = MT_DEVICE
128 }, {
129 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
130 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
131 .length = SZ_4K,
132 .type = MT_DEVICE
133 }, {
134 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
135 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
136 .length = SZ_4K * 9,
137 .type = MT_DEVICE
138 },
1da177e4 139#ifdef CONFIG_MACH_VERSATILE_AB
1311521f 140 {
1311521f
DS		 141 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
142 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
143 .length = SZ_64M,
144 .type = MT_DEVICE
145 },
1da177e4
LT		 146#endif
147#ifdef CONFIG_DEBUG_LL
1311521f
DS		 148 {
149 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
150 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
151 .length = SZ_4K,
152 .type = MT_DEVICE
153 },
1da177e4 154#endif
c0da085a 155#ifdef CONFIG_PCI
1311521f
DS		 156 {
157 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
158 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
159 .length = SZ_4K,
160 .type = MT_DEVICE
161 }, {
399ad77b 162 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
1311521f
DS		 163 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
164 .length = VERSATILE_PCI_BASE_SIZE,
165 .type = MT_DEVICE
166 }, {
399ad77b 167 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
1311521f
DS		 168 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
169 .length = VERSATILE_PCI_CFG_BASE_SIZE,
170 .type = MT_DEVICE
1311521f 171 },
c0da085a 172#endif
1da177e4
LT		 173};
174
175void __init versatile_map_io(void)
176{
177 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
178}
179
1da177e4 180
2ad4f86b 181#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4 182
667f390b 183static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4
LT		 184{
185 u32 val;
186
187 val = __raw_readl(VERSATILE_FLASHCTRL);
188 if (on)
189 val |= VERSATILE_FLASHPROG_FLVPPEN;
190 else
191 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
192 __raw_writel(val, VERSATILE_FLASHCTRL);
193}
194
68c0e38c 195static struct physmap_flash_data versatile_flash_data = {
1da177e4 196 .width = 4,
1da177e4
LT		 197 .set_vpp = versatile_flash_set_vpp,
198};
199
200static struct resource versatile_flash_resource = {
201 .start = VERSATILE_FLASH_BASE,
a0c5a645 202 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
1da177e4
LT		 203 .flags = IORESOURCE_MEM,
204};
205
206static struct platform_device versatile_flash_device = {
68c0e38c 207 .name = "physmap-flash",
1da177e4
LT		 208 .id = 0,
209 .dev = {
210 .platform_data = &versatile_flash_data,
211 },
212 .num_resources = 1,
213 .resource = &versatile_flash_resource,
214};
215
216static struct resource smc91x_resources[] = {
217 [0] = {
218 .start = VERSATILE_ETH_BASE,
219 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 [1] = {
223 .start = IRQ_ETH,
224 .end = IRQ_ETH,
225 .flags = IORESOURCE_IRQ,
226 },
227};
228
229static struct platform_device smc91x_device = {
230 .name = "smc91x",
231 .id = 0,
232 .num_resources = ARRAY_SIZE(smc91x_resources),
233 .resource = smc91x_resources,
234};
235
6b65cd74
RK		 236static struct resource versatile_i2c_resource = {
237 .start = VERSATILE_I2C_BASE,
238 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
239 .flags = IORESOURCE_MEM,
240};
241
242static struct platform_device versatile_i2c_device = {
243 .name = "versatile-i2c",
533ad5e6 244 .id = 0,
6b65cd74
RK		 245 .num_resources = 1,
246 .resource = &versatile_i2c_resource,
247};
248
533ad5e6
CM		 249static struct i2c_board_info versatile_i2c_board_info[] = {
250 {
64e8be6e 251 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6
CM		 252 },
253};
254
255static int __init versatile_i2c_init(void)
256{
257 return i2c_register_board_info(0, versatile_i2c_board_info,
258 ARRAY_SIZE(versatile_i2c_board_info));
259}
260arch_initcall(versatile_i2c_init);
261
2ad4f86b 262#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 263
264unsigned int mmc_status(struct device *dev)
265{
266 struct amba_device *adev = container_of(dev, struct amba_device, dev);
267 u32 mask;
268
269 if (adev->res.start == VERSATILE_MMCI0_BASE)
270 mask = 1;
271 else
272 mask = 2;
273
274 return readl(VERSATILE_SYSMCI) & mask;
275}
276
6ef297f8 277static struct mmci_platform_data mmc0_plat_data = {
1da177e4
LT		 278 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
279 .status = mmc_status,
7fb2bbf4
RK		 280 .gpio_wp = -1,
281 .gpio_cd = -1,
1da177e4
LT		 282};
283
e2823266 284static struct resource char_lcd_resources[] = {
d161edfb
LW		 285 {
286 .start = VERSATILE_CHAR_LCD_BASE,
287 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
288 .flags = IORESOURCE_MEM,
289 },
290};
291
292static struct platform_device char_lcd_device = {
293 .name = "arm-charlcd",
294 .id = -1,
295 .num_resources = ARRAY_SIZE(char_lcd_resources),
296 .resource = char_lcd_resources,
297};
298
1da177e4
LT		 299/*
300 * Clock handling
301 */
39c0cb02 302static const struct icst_params versatile_oscvco_params = {
64fceb1d 303 .ref = 24000000,
4de2edbd 304 .vco_max = ICST307_VCO_MAX,
e73a46a3 305 .vco_min = ICST307_VCO_MIN,
1da177e4
LT		 306 .vd_min = 4 + 8,
307 .vd_max = 511 + 8,
308 .rd_min = 1 + 2,
309 .rd_max = 127 + 2,
232eaf7f
RK		 310 .s2div = icst307_s2div,
311 .idx2s = icst307_idx2s,
1da177e4
LT		 312};
313
39c0cb02 314static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
1da177e4 315{
d1914c7e 316 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
1da177e4
LT		 317 u32 val;
318
d1914c7e 319 val = readl(clk->vcoreg) & ~0x7ffff;
1da177e4
LT		 320 val |= vco.v | (vco.r << 9) | (vco.s << 16);
321
322 writel(0xa05f, sys_lock);
d1914c7e 323 writel(val, clk->vcoreg);
1da177e4
LT		 324 writel(0, sys_lock);
325}
326
9bf5b2ef
RK		 327static const struct clk_ops osc4_clk_ops = {
328 .round = icst_clk_round,
329 .set = icst_clk_set,
330 .setvco = versatile_oscvco_set,
331};
332
71a06da0 333static struct clk osc4_clk = {
9bf5b2ef 334 .ops = &osc4_clk_ops,
1da177e4 335 .params = &versatile_oscvco_params,
71a06da0
RK		 336};
337
338/*
339 * These are fixed clocks.
340 */
341static struct clk ref24_clk = {
342 .rate = 24000000,
343};
344
7ff550de
RK		 345static struct clk sp804_clk = {
346 .rate = 1000000,
347};
348
3126c7bc
RK		 349static struct clk dummy_apb_pclk;
350
982db663 351static struct clk_lookup lookups[] = {
3126c7bc
RK		 352 { /* AMBA bus clock */
353 .con_id = "apb_pclk",
354 .clk = &dummy_apb_pclk,
355 }, { /* UART0 */
71a06da0
RK		 356 .dev_id = "dev:f1",
357 .clk = &ref24_clk,
358 }, { /* UART1 */
359 .dev_id = "dev:f2",
360 .clk = &ref24_clk,
361 }, { /* UART2 */
362 .dev_id = "dev:f3",
363 .clk = &ref24_clk,
364 }, { /* UART3 */
365 .dev_id = "fpga:09",
366 .clk = &ref24_clk,
367 }, { /* KMI0 */
368 .dev_id = "fpga:06",
369 .clk = &ref24_clk,
370 }, { /* KMI1 */
371 .dev_id = "fpga:07",
372 .clk = &ref24_clk,
373 }, { /* MMC0 */
374 .dev_id = "fpga:05",
375 .clk = &ref24_clk,
376 }, { /* MMC1 */
377 .dev_id = "fpga:0b",
378 .clk = &ref24_clk,
ef6f4b12
LW		 379 }, { /* SSP */
380 .dev_id = "dev:f4",
381 .clk = &ref24_clk,
71a06da0
RK		 382 }, { /* CLCD */
383 .dev_id = "dev:20",
384 .clk = &osc4_clk,
7ff550de
RK		 385 }, { /* SP804 timers */
386 .dev_id = "sp804",
387 .clk = &sp804_clk,
388 },
1da177e4
LT		 389};
390
391/*
392 * CLCD support.
393 */
394#define SYS_CLCD_MODE_MASK (3 << 0)
395#define SYS_CLCD_MODE_888 (0 << 0)
396#define SYS_CLCD_MODE_5551 (1 << 0)
397#define SYS_CLCD_MODE_565_RLSB (2 << 0)
398#define SYS_CLCD_MODE_565_BLSB (3 << 0)
399#define SYS_CLCD_NLCDIOON (1 << 2)
400#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
401#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
402#define SYS_CLCD_ID_MASK (0x1f << 8)
403#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
404#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
405#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
406#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
407#define SYS_CLCD_ID_VGA (0x1f << 8)
408
3414ba8c 409static bool is_sanyo_2_5_lcd;
1da177e4
LT		 410
411/*
412 * Disable all display connectors on the interface module.
413 */
414static void versatile_clcd_disable(struct clcd_fb *fb)
415{
2ad4f86b 416 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 417 u32 val;
418
419 val = readl(sys_clcd);
420 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
421 writel(val, sys_clcd);
422
423#ifdef CONFIG_MACH_VERSATILE_AB
424 /*
425 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
426 */
3414ba8c 427 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
2ad4f86b 428 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 429 unsigned long ctrl;
430
431 ctrl = readl(versatile_ib2_ctrl);
432 ctrl &= ~0x01;
433 writel(ctrl, versatile_ib2_ctrl);
434 }
435#endif
436}
437
438/*
439 * Enable the relevant connector on the interface module.
440 */
441static void versatile_clcd_enable(struct clcd_fb *fb)
442{
9728c1b6 443 struct fb_var_screeninfo *var = &fb->fb.var;
2ad4f86b 444 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 445 u32 val;
446
447 val = readl(sys_clcd);
448 val &= ~SYS_CLCD_MODE_MASK;
449
9728c1b6 450 switch (var->green.length) {
1da177e4
LT		 451 case 5:
452 val |= SYS_CLCD_MODE_5551;
453 break;
454 case 6:
9728c1b6
RK		 455 if (var->red.offset == 0)
456 val |= SYS_CLCD_MODE_565_RLSB;
457 else
458 val |= SYS_CLCD_MODE_565_BLSB;
1da177e4
LT		 459 break;
460 case 8:
461 val |= SYS_CLCD_MODE_888;
462 break;
463 }
464
465 /*
466 * Set the MUX
467 */
468 writel(val, sys_clcd);
469
470 /*
471 * And now enable the PSUs
472 */
473 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
474 writel(val, sys_clcd);
475
476#ifdef CONFIG_MACH_VERSATILE_AB
477 /*
478 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
479 */
3414ba8c 480 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
2ad4f86b 481 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 482 unsigned long ctrl;
483
484 ctrl = readl(versatile_ib2_ctrl);
485 ctrl |= 0x01;
486 writel(ctrl, versatile_ib2_ctrl);
487 }
488#endif
489}
490
3414ba8c
RK		 491/*
492 * Detect which LCD panel is connected, and return the appropriate
493 * clcd_panel structure. Note: we do not have any information on
494 * the required timings for the 8.4in panel, so we presently assume
495 * VGA timings.
496 */
1da177e4
LT		 497static int versatile_clcd_setup(struct clcd_fb *fb)
498{
3414ba8c
RK		 499 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
500 const char *panel_name;
501 u32 val;
1da177e4 502
3414ba8c 503 is_sanyo_2_5_lcd = false;
1da177e4 504
3414ba8c
RK		 505 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
506 if (val == SYS_CLCD_ID_SANYO_3_8)
507 panel_name = "Sanyo TM38QV67A02A";
508 else if (val == SYS_CLCD_ID_SANYO_2_5) {
509 panel_name = "Sanyo QVGA Portrait";
510 is_sanyo_2_5_lcd = true;
511 } else if (val == SYS_CLCD_ID_EPSON_2_2)
512 panel_name = "Epson L2F50113T00";
513 else if (val == SYS_CLCD_ID_VGA)
514 panel_name = "VGA";
515 else {
516 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
517 val);
518 panel_name = "VGA";
1da177e4
LT		 519 }
520
3414ba8c
RK		 521 fb->panel = versatile_clcd_get_panel(panel_name);
522 if (!fb->panel)
523 return -EINVAL;
1da177e4 524
3414ba8c 525 return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4
LT		 526}
527
9728c1b6
RK		 528static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
529{
530 clcdfb_decode(fb, regs);
531
532 /* Always clear BGR for RGB565: we do the routing externally */
533 if (fb->fb.var.green.length == 6)
534 regs->cntl &= ~CNTL_BGR;
535}
536
1da177e4
LT		 537static struct clcd_board clcd_plat_data = {
538 .name = "Versatile",
3414ba8c 539 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
1da177e4 540 .check = clcdfb_check,
9728c1b6 541 .decode = versatile_clcd_decode,
1da177e4
LT		 542 .disable = versatile_clcd_disable,
543 .enable = versatile_clcd_enable,
544 .setup = versatile_clcd_setup,
3414ba8c
RK		 545 .mmap = versatile_clcd_mmap_dma,
546 .remove = versatile_clcd_remove_dma,
1da177e4
LT		 547};
548
bbeddc43
RK		 549static struct pl061_platform_data gpio0_plat_data = {
550 .gpio_base = 0,
551 .irq_base = IRQ_GPIO0_START,
552};
553
554static struct pl061_platform_data gpio1_plat_data = {
555 .gpio_base = 8,
556 .irq_base = IRQ_GPIO1_START,
557};
558
ef6f4b12
LW		 559static struct pl022_ssp_controller ssp0_plat_data = {
560 .bus_id = 0,
561 .enable_dma = 0,
562 .num_chipselect = 1,
563};
564
0dada61a 565#define AACI_IRQ { IRQ_AACI }
1da177e4 566#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
0dada61a
RK		 567#define KMI0_IRQ { IRQ_SIC_KMI0 }
568#define KMI1_IRQ { IRQ_SIC_KMI1 }
1da177e4
LT		 569
570/*
571 * These devices are connected directly to the multi-layer AHB switch
572 */
0dada61a
RK		 573#define SMC_IRQ { }
574#define MPMC_IRQ { }
575#define CLCD_IRQ { IRQ_CLCDINT }
576#define DMAC_IRQ { IRQ_DMAINT }
1da177e4
LT		 577
578/*
579 * These devices are connected via the core APB bridge
580 */
0dada61a
RK		 581#define SCTL_IRQ { }
582#define WATCHDOG_IRQ { IRQ_WDOGINT }
583#define GPIO0_IRQ { IRQ_GPIOINT0 }
584#define GPIO1_IRQ { IRQ_GPIOINT1 }
585#define RTC_IRQ { IRQ_RTCINT }
1da177e4
LT		 586
587/*
588 * These devices are connected via the DMA APB bridge
589 */
0dada61a
RK		 590#define SCI_IRQ { IRQ_SCIINT }
591#define UART0_IRQ { IRQ_UARTINT0 }
592#define UART1_IRQ { IRQ_UARTINT1 }
593#define UART2_IRQ { IRQ_UARTINT2 }
594#define SSP_IRQ { IRQ_SSPINT }
1da177e4
LT		 595
596/* FPGA Primecells */
8f5088b6
RK		 597APB_DEVICE(aaci, "fpga:04", AACI, NULL);
598APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
599APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
600APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
1da177e4
LT		 601
602/* DevChip Primecells */
8f5088b6
RK		 603AHB_DEVICE(smc, "dev:00", SMC, NULL);
604AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
605AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
606AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
607APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
608APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
609APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
610APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
611APB_DEVICE(rtc, "dev:e8", RTC, NULL);
612APB_DEVICE(sci0, "dev:f0", SCI, NULL);
613APB_DEVICE(uart0, "dev:f1", UART0, NULL);
614APB_DEVICE(uart1, "dev:f2", UART1, NULL);
615APB_DEVICE(uart2, "dev:f3", UART2, NULL);
616APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
1da177e4
LT		 617
618static struct amba_device *amba_devs[] __initdata = {
619 &dmac_device,
620 &uart0_device,
621 &uart1_device,
622 &uart2_device,
623 &smc_device,
624 &mpmc_device,
625 &clcd_device,
626 &sctl_device,
627 &wdog_device,
628 &gpio0_device,
629 &gpio1_device,
630 &rtc_device,
631 &sci0_device,
632 &ssp0_device,
633 &aaci_device,
634 &mmc0_device,
635 &kmi0_device,
636 &kmi1_device,
637};
638
3ba7222a
GL		 639#ifdef CONFIG_OF
640/*
641 * Lookup table for attaching a specific name and platform_data pointer to
642 * devices as they get created by of_platform_populate(). Ideally this table
643 * would not exist, but the current clock implementation depends on some devices
644 * having a specific name.
645 */
646struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
d12379ac 647 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
3ba7222a
GL		 648 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
649 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
650 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
d12379ac 651 /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
3ba7222a
GL		 652 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
653
654 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
655 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
656 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
657 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
d12379ac 658 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
3ba7222a
GL		 659
660#if 0
661 /*
662 * These entries are unnecessary because no clocks referencing
663 * them. I've left them in for now as place holders in case
664 * any of them need to be added back, but they should be
665 * removed before actually committing this patch. --gcl
666 */
667 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
668 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
670 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
672
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
678 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
679 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
680 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
681#endif
682 {}
683};
684#endif
685
1da177e4 686#ifdef CONFIG_LEDS
2ad4f86b 687#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 688
689static void versatile_leds_event(led_event_t ledevt)
690{
691 unsigned long flags;
692 u32 val;
693
694 local_irq_save(flags);
695 val = readl(VA_LEDS_BASE);
696
697 switch (ledevt) {
698 case led_idle_start:
699 val = val & ~VERSATILE_SYS_LED0;
700 break;
701
702 case led_idle_end:
703 val = val | VERSATILE_SYS_LED0;
704 break;
705
706 case led_timer:
707 val = val ^ VERSATILE_SYS_LED1;
708 break;
709
710 case led_halted:
711 val = 0;
712 break;
713
714 default:
715 break;
716 }
717
718 writel(val, VA_LEDS_BASE);
719 local_irq_restore(flags);
720}
721#endif /* CONFIG_LEDS */
722
b56a7c6b
RK		 723void versatile_restart(char mode, const char *cmd)
724{
725 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
726 u32 val;
727
728 val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
729 val |= 0x105;
730
731 __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
732 __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
733 __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
734}
735
ad3bb19c
RK		 736/* Early initializations */
737void __init versatile_init_early(void)
1da177e4 738{
ad3bb19c 739 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
d1914c7e 740
ad3bb19c 741 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
0a0300dc 742 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1da177e4 743
ad3bb19c
RK		 744 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
745}
746
747void __init versatile_init(void)
748{
749 int i;
750
1da177e4 751 platform_device_register(&versatile_flash_device);
6b65cd74 752 platform_device_register(&versatile_i2c_device);
1da177e4 753 platform_device_register(&smc91x_device);
d161edfb 754 platform_device_register(&char_lcd_device);
1da177e4
LT		 755
756 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
757 struct amba_device *d = amba_devs[i];
758 amba_device_register(d, &iomem_resource);
759 }
1da177e4
LT		 760}
761
762/*
763 * Where is the timer (VA)?
764 */
2ad4f86b
AV		 765#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
766#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
767#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
768#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
b49c87c2 769
1da177e4
LT		 770/*
771 * Set up timer interrupt, and return the current time in seconds.
772 */
773static void __init versatile_timer_init(void)
774{
b720f732 775 u32 val;
1da177e4
LT		 776
777 /*
778 * set clock frequency:
779 * VERSATILE_REFCLK is 32KHz
780 * VERSATILE_TIMCLK is 1MHz
781 */
2ad4f86b 782 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 783 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
784 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
785 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
786 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 787 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 788
789 /*
790 * Initialise to a known state (all timers off)
791 */
b720f732
RK		 792 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
793 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
794 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
795 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
796
fb593cf3 797 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
57cc4f7d 798 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
1da177e4
LT		 799}
800
801struct sys_timer versatile_timer = {
802 .init = versatile_timer_init,
1da177e4 803};
b49c87c2 804
Linux kernel - Deliverables
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