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ARM: OMAP: Fix Beagleboard DVI reset gpio
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
1da177e4
LT		 21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
d052d1be 24#include <linux/platform_device.h>
1da177e4 25#include <linux/interrupt.h>
3ba7222a
GL		 26#include <linux/irqdomain.h>
27#include <linux/of_address.h>
28#include <linux/of_platform.h>
a62c80e5
RK		 29#include <linux/amba/bus.h>
30#include <linux/amba/clcd.h>
bbeddc43 31#include <linux/amba/pl061.h>
6ef297f8 32#include <linux/amba/mmci.h>
ef6f4b12 33#include <linux/amba/pl022.h>
fced80c7 34#include <linux/io.h>
5a0e3ad6 35#include <linux/gfp.h>
6d803ba7 36#include <linux/clkdev.h>
68c0e38c 37#include <linux/mtd/physmap.h>
1da177e4 38
1da177e4
LT		 39#include <asm/irq.h>
40#include <asm/leds.h>
b720f732 41#include <asm/hardware/arm_timer.h>
c5a0adb5 42#include <asm/hardware/icst.h>
fa0fe48f 43#include <asm/hardware/vic.h>
dc5bc8f1 44#include <asm/mach-types.h>
1da177e4
LT		 45
46#include <asm/mach/arch.h>
1da177e4
LT		 47#include <asm/mach/irq.h>
48#include <asm/mach/time.h>
49#include <asm/mach/map.h>
a285edcf
RK		 50#include <mach/hardware.h>
51#include <mach/platform.h>
8a9618f5 52#include <asm/hardware/timer-sp.h>
1da177e4 53
3414ba8c 54#include <plat/clcd.h>
c41b16f8 55#include <plat/fpga-irq.h>
1da0c89c
RK		 56#include <plat/sched_clock.h>
57
1da177e4 58#include "core.h"
1da177e4
LT		 59
60/*
61 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
62 * is the (PA >> 12).
63 *
64 * Setup a VA for the Versatile Vectored Interrupt Controller.
65 */
2ad4f86b
AV		 66#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
67#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4 68
1da177e4
LT		 69#if 1
70#define IRQ_MMCI0A IRQ_VICSOURCE22
71#define IRQ_AACI IRQ_VICSOURCE24
72#define IRQ_ETH IRQ_VICSOURCE25
73#define PIC_MASK 0xFFD00000
74#else
75#define IRQ_MMCI0A IRQ_SIC_MMCI0A
76#define IRQ_AACI IRQ_SIC_AACI
77#define IRQ_ETH IRQ_SIC_ETH
78#define PIC_MASK 0
79#endif
80
3ba7222a
GL		 81/* Lookup table for finding a DT node that represents the vic instance */
82static const struct of_device_id vic_of_match[] __initconst = {
83 { .compatible = "arm,versatile-vic", },
84 {}
85};
86
87static const struct of_device_id sic_of_match[] __initconst = {
88 { .compatible = "arm,versatile-sic", },
89 {}
90};
91
1da177e4
LT		 92void __init versatile_init_irq(void)
93{
75294957
GL		 94 struct device_node *np;
95
96 np = of_find_matching_node_by_address(NULL, vic_of_match,
97 VERSATILE_VIC_BASE);
98 __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
1da177e4 99
1da177e4
LT		 100 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
101
3108e6ab
LW		 102 np = of_find_matching_node_by_address(NULL, sic_of_match,
103 VERSATILE_SIC_BASE);
104
105 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
106 IRQ_VICSOURCE31, ~PIC_MASK, np);
1da177e4
LT		 107
108 /*
109 * Interrupts on secondary controller from 0 to 8 are routed to
110 * source 31 on PIC.
111 * Interrupts from 21 to 31 are routed directly to the VIC on
112 * the corresponding number on primary controller. This is controlled
113 * by setting PIC_ENABLEx.
114 */
115 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
116}
117
118static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 119 {
120 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
121 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
122 .length = SZ_4K,
123 .type = MT_DEVICE
124 }, {
125 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
126 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
127 .length = SZ_4K,
128 .type = MT_DEVICE
129 }, {
130 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
131 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
132 .length = SZ_4K,
133 .type = MT_DEVICE
134 }, {
135 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
136 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
137 .length = SZ_4K * 9,
138 .type = MT_DEVICE
139 },
1da177e4 140#ifdef CONFIG_MACH_VERSATILE_AB
1311521f 141 {
1311521f
DS		 142 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
143 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
144 .length = SZ_64M,
145 .type = MT_DEVICE
146 },
1da177e4
LT		 147#endif
148#ifdef CONFIG_DEBUG_LL
1311521f
DS		 149 {
150 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
151 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
152 .length = SZ_4K,
153 .type = MT_DEVICE
154 },
1da177e4 155#endif
c0da085a 156#ifdef CONFIG_PCI
1311521f
DS		 157 {
158 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
159 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
160 .length = SZ_4K,
161 .type = MT_DEVICE
162 }, {
399ad77b 163 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
1311521f
DS		 164 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
165 .length = VERSATILE_PCI_BASE_SIZE,
166 .type = MT_DEVICE
167 }, {
399ad77b 168 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
1311521f
DS		 169 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
170 .length = VERSATILE_PCI_CFG_BASE_SIZE,
171 .type = MT_DEVICE
172 },
c0da085a 173#if 0
1311521f
DS		 174 {
175 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
176 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
177 .length = SZ_16M,
178 .type = MT_DEVICE
179 }, {
180 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
181 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
182 .length = SZ_16M,
183 .type = MT_DEVICE
184 }, {
185 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
186 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
187 .length = SZ_16M,
188 .type = MT_DEVICE
189 },
c0da085a 190#endif
1da177e4
LT		 191#endif
192};
193
194void __init versatile_map_io(void)
195{
196 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
197}
198
1da177e4 199
2ad4f86b 200#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4 201
667f390b 202static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
1da177e4
LT		 203{
204 u32 val;
205
206 val = __raw_readl(VERSATILE_FLASHCTRL);
207 if (on)
208 val |= VERSATILE_FLASHPROG_FLVPPEN;
209 else
210 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
211 __raw_writel(val, VERSATILE_FLASHCTRL);
212}
213
68c0e38c 214static struct physmap_flash_data versatile_flash_data = {
1da177e4 215 .width = 4,
1da177e4
LT		 216 .set_vpp = versatile_flash_set_vpp,
217};
218
219static struct resource versatile_flash_resource = {
220 .start = VERSATILE_FLASH_BASE,
a0c5a645 221 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
1da177e4
LT		 222 .flags = IORESOURCE_MEM,
223};
224
225static struct platform_device versatile_flash_device = {
68c0e38c 226 .name = "physmap-flash",
1da177e4
LT		 227 .id = 0,
228 .dev = {
229 .platform_data = &versatile_flash_data,
230 },
231 .num_resources = 1,
232 .resource = &versatile_flash_resource,
233};
234
235static struct resource smc91x_resources[] = {
236 [0] = {
237 .start = VERSATILE_ETH_BASE,
238 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
239 .flags = IORESOURCE_MEM,
240 },
241 [1] = {
242 .start = IRQ_ETH,
243 .end = IRQ_ETH,
244 .flags = IORESOURCE_IRQ,
245 },
246};
247
248static struct platform_device smc91x_device = {
249 .name = "smc91x",
250 .id = 0,
251 .num_resources = ARRAY_SIZE(smc91x_resources),
252 .resource = smc91x_resources,
253};
254
6b65cd74
RK		 255static struct resource versatile_i2c_resource = {
256 .start = VERSATILE_I2C_BASE,
257 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
258 .flags = IORESOURCE_MEM,
259};
260
261static struct platform_device versatile_i2c_device = {
262 .name = "versatile-i2c",
533ad5e6 263 .id = 0,
6b65cd74
RK		 264 .num_resources = 1,
265 .resource = &versatile_i2c_resource,
266};
267
533ad5e6
CM		 268static struct i2c_board_info versatile_i2c_board_info[] = {
269 {
64e8be6e 270 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6
CM		 271 },
272};
273
274static int __init versatile_i2c_init(void)
275{
276 return i2c_register_board_info(0, versatile_i2c_board_info,
277 ARRAY_SIZE(versatile_i2c_board_info));
278}
279arch_initcall(versatile_i2c_init);
280
2ad4f86b 281#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 282
283unsigned int mmc_status(struct device *dev)
284{
285 struct amba_device *adev = container_of(dev, struct amba_device, dev);
286 u32 mask;
287
288 if (adev->res.start == VERSATILE_MMCI0_BASE)
289 mask = 1;
290 else
291 mask = 2;
292
293 return readl(VERSATILE_SYSMCI) & mask;
294}
295
6ef297f8 296static struct mmci_platform_data mmc0_plat_data = {
1da177e4
LT		 297 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
298 .status = mmc_status,
7fb2bbf4
RK		 299 .gpio_wp = -1,
300 .gpio_cd = -1,
1da177e4
LT		 301};
302
e2823266 303static struct resource char_lcd_resources[] = {
d161edfb
LW		 304 {
305 .start = VERSATILE_CHAR_LCD_BASE,
306 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
307 .flags = IORESOURCE_MEM,
308 },
309};
310
311static struct platform_device char_lcd_device = {
312 .name = "arm-charlcd",
313 .id = -1,
314 .num_resources = ARRAY_SIZE(char_lcd_resources),
315 .resource = char_lcd_resources,
316};
317
1da177e4
LT		 318/*
319 * Clock handling
320 */
39c0cb02 321static const struct icst_params versatile_oscvco_params = {
64fceb1d 322 .ref = 24000000,
4de2edbd 323 .vco_max = ICST307_VCO_MAX,
e73a46a3 324 .vco_min = ICST307_VCO_MIN,
1da177e4
LT		 325 .vd_min = 4 + 8,
326 .vd_max = 511 + 8,
327 .rd_min = 1 + 2,
328 .rd_max = 127 + 2,
232eaf7f
RK		 329 .s2div = icst307_s2div,
330 .idx2s = icst307_idx2s,
1da177e4
LT		 331};
332
39c0cb02 333static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
1da177e4 334{
d1914c7e 335 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
1da177e4
LT		 336 u32 val;
337
d1914c7e 338 val = readl(clk->vcoreg) & ~0x7ffff;
1da177e4
LT		 339 val |= vco.v | (vco.r << 9) | (vco.s << 16);
340
341 writel(0xa05f, sys_lock);
d1914c7e 342 writel(val, clk->vcoreg);
1da177e4
LT		 343 writel(0, sys_lock);
344}
345
9bf5b2ef
RK		 346static const struct clk_ops osc4_clk_ops = {
347 .round = icst_clk_round,
348 .set = icst_clk_set,
349 .setvco = versatile_oscvco_set,
350};
351
71a06da0 352static struct clk osc4_clk = {
9bf5b2ef 353 .ops = &osc4_clk_ops,
1da177e4 354 .params = &versatile_oscvco_params,
71a06da0
RK		 355};
356
357/*
358 * These are fixed clocks.
359 */
360static struct clk ref24_clk = {
361 .rate = 24000000,
362};
363
7ff550de
RK		 364static struct clk sp804_clk = {
365 .rate = 1000000,
366};
367
3126c7bc
RK		 368static struct clk dummy_apb_pclk;
369
982db663 370static struct clk_lookup lookups[] = {
3126c7bc
RK		 371 { /* AMBA bus clock */
372 .con_id = "apb_pclk",
373 .clk = &dummy_apb_pclk,
374 }, { /* UART0 */
71a06da0
RK		 375 .dev_id = "dev:f1",
376 .clk = &ref24_clk,
377 }, { /* UART1 */
378 .dev_id = "dev:f2",
379 .clk = &ref24_clk,
380 }, { /* UART2 */
381 .dev_id = "dev:f3",
382 .clk = &ref24_clk,
383 }, { /* UART3 */
384 .dev_id = "fpga:09",
385 .clk = &ref24_clk,
386 }, { /* KMI0 */
387 .dev_id = "fpga:06",
388 .clk = &ref24_clk,
389 }, { /* KMI1 */
390 .dev_id = "fpga:07",
391 .clk = &ref24_clk,
392 }, { /* MMC0 */
393 .dev_id = "fpga:05",
394 .clk = &ref24_clk,
395 }, { /* MMC1 */
396 .dev_id = "fpga:0b",
397 .clk = &ref24_clk,
ef6f4b12
LW		 398 }, { /* SSP */
399 .dev_id = "dev:f4",
400 .clk = &ref24_clk,
71a06da0
RK		 401 }, { /* CLCD */
402 .dev_id = "dev:20",
403 .clk = &osc4_clk,
7ff550de
RK		 404 }, { /* SP804 timers */
405 .dev_id = "sp804",
406 .clk = &sp804_clk,
407 },
1da177e4
LT		 408};
409
410/*
411 * CLCD support.
412 */
413#define SYS_CLCD_MODE_MASK (3 << 0)
414#define SYS_CLCD_MODE_888 (0 << 0)
415#define SYS_CLCD_MODE_5551 (1 << 0)
416#define SYS_CLCD_MODE_565_RLSB (2 << 0)
417#define SYS_CLCD_MODE_565_BLSB (3 << 0)
418#define SYS_CLCD_NLCDIOON (1 << 2)
419#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
420#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
421#define SYS_CLCD_ID_MASK (0x1f << 8)
422#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
423#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
424#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
425#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
426#define SYS_CLCD_ID_VGA (0x1f << 8)
427
3414ba8c 428static bool is_sanyo_2_5_lcd;
1da177e4
LT		 429
430/*
431 * Disable all display connectors on the interface module.
432 */
433static void versatile_clcd_disable(struct clcd_fb *fb)
434{
2ad4f86b 435 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 436 u32 val;
437
438 val = readl(sys_clcd);
439 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
440 writel(val, sys_clcd);
441
442#ifdef CONFIG_MACH_VERSATILE_AB
443 /*
444 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
445 */
3414ba8c 446 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
2ad4f86b 447 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 448 unsigned long ctrl;
449
450 ctrl = readl(versatile_ib2_ctrl);
451 ctrl &= ~0x01;
452 writel(ctrl, versatile_ib2_ctrl);
453 }
454#endif
455}
456
457/*
458 * Enable the relevant connector on the interface module.
459 */
460static void versatile_clcd_enable(struct clcd_fb *fb)
461{
9728c1b6 462 struct fb_var_screeninfo *var = &fb->fb.var;
2ad4f86b 463 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 464 u32 val;
465
466 val = readl(sys_clcd);
467 val &= ~SYS_CLCD_MODE_MASK;
468
9728c1b6 469 switch (var->green.length) {
1da177e4
LT		 470 case 5:
471 val |= SYS_CLCD_MODE_5551;
472 break;
473 case 6:
9728c1b6
RK		 474 if (var->red.offset == 0)
475 val |= SYS_CLCD_MODE_565_RLSB;
476 else
477 val |= SYS_CLCD_MODE_565_BLSB;
1da177e4
LT		 478 break;
479 case 8:
480 val |= SYS_CLCD_MODE_888;
481 break;
482 }
483
484 /*
485 * Set the MUX
486 */
487 writel(val, sys_clcd);
488
489 /*
490 * And now enable the PSUs
491 */
492 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
493 writel(val, sys_clcd);
494
495#ifdef CONFIG_MACH_VERSATILE_AB
496 /*
497 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
498 */
3414ba8c 499 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
2ad4f86b 500 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 501 unsigned long ctrl;
502
503 ctrl = readl(versatile_ib2_ctrl);
504 ctrl |= 0x01;
505 writel(ctrl, versatile_ib2_ctrl);
506 }
507#endif
508}
509
3414ba8c
RK		 510/*
511 * Detect which LCD panel is connected, and return the appropriate
512 * clcd_panel structure. Note: we do not have any information on
513 * the required timings for the 8.4in panel, so we presently assume
514 * VGA timings.
515 */
1da177e4
LT		 516static int versatile_clcd_setup(struct clcd_fb *fb)
517{
3414ba8c
RK		 518 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
519 const char *panel_name;
520 u32 val;
1da177e4 521
3414ba8c 522 is_sanyo_2_5_lcd = false;
1da177e4 523
3414ba8c
RK		 524 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
525 if (val == SYS_CLCD_ID_SANYO_3_8)
526 panel_name = "Sanyo TM38QV67A02A";
527 else if (val == SYS_CLCD_ID_SANYO_2_5) {
528 panel_name = "Sanyo QVGA Portrait";
529 is_sanyo_2_5_lcd = true;
530 } else if (val == SYS_CLCD_ID_EPSON_2_2)
531 panel_name = "Epson L2F50113T00";
532 else if (val == SYS_CLCD_ID_VGA)
533 panel_name = "VGA";
534 else {
535 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
536 val);
537 panel_name = "VGA";
1da177e4
LT		 538 }
539
3414ba8c
RK		 540 fb->panel = versatile_clcd_get_panel(panel_name);
541 if (!fb->panel)
542 return -EINVAL;
1da177e4 543
3414ba8c 544 return versatile_clcd_setup_dma(fb, SZ_1M);
1da177e4
LT		 545}
546
9728c1b6
RK		 547static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
548{
549 clcdfb_decode(fb, regs);
550
551 /* Always clear BGR for RGB565: we do the routing externally */
552 if (fb->fb.var.green.length == 6)
553 regs->cntl &= ~CNTL_BGR;
554}
555
1da177e4
LT		 556static struct clcd_board clcd_plat_data = {
557 .name = "Versatile",
3414ba8c 558 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
1da177e4 559 .check = clcdfb_check,
9728c1b6 560 .decode = versatile_clcd_decode,
1da177e4
LT		 561 .disable = versatile_clcd_disable,
562 .enable = versatile_clcd_enable,
563 .setup = versatile_clcd_setup,
3414ba8c
RK		 564 .mmap = versatile_clcd_mmap_dma,
565 .remove = versatile_clcd_remove_dma,
1da177e4
LT		 566};
567
bbeddc43
RK		 568static struct pl061_platform_data gpio0_plat_data = {
569 .gpio_base = 0,
570 .irq_base = IRQ_GPIO0_START,
571};
572
573static struct pl061_platform_data gpio1_plat_data = {
574 .gpio_base = 8,
575 .irq_base = IRQ_GPIO1_START,
576};
577
ef6f4b12
LW		 578static struct pl022_ssp_controller ssp0_plat_data = {
579 .bus_id = 0,
580 .enable_dma = 0,
581 .num_chipselect = 1,
582};
583
0dada61a 584#define AACI_IRQ { IRQ_AACI }
1da177e4 585#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
0dada61a
RK		 586#define KMI0_IRQ { IRQ_SIC_KMI0 }
587#define KMI1_IRQ { IRQ_SIC_KMI1 }
1da177e4
LT		 588
589/*
590 * These devices are connected directly to the multi-layer AHB switch
591 */
0dada61a
RK		 592#define SMC_IRQ { }
593#define MPMC_IRQ { }
594#define CLCD_IRQ { IRQ_CLCDINT }
595#define DMAC_IRQ { IRQ_DMAINT }
1da177e4
LT		 596
597/*
598 * These devices are connected via the core APB bridge
599 */
0dada61a
RK		 600#define SCTL_IRQ { }
601#define WATCHDOG_IRQ { IRQ_WDOGINT }
602#define GPIO0_IRQ { IRQ_GPIOINT0 }
603#define GPIO1_IRQ { IRQ_GPIOINT1 }
604#define RTC_IRQ { IRQ_RTCINT }
1da177e4
LT		 605
606/*
607 * These devices are connected via the DMA APB bridge
608 */
0dada61a
RK		 609#define SCI_IRQ { IRQ_SCIINT }
610#define UART0_IRQ { IRQ_UARTINT0 }
611#define UART1_IRQ { IRQ_UARTINT1 }
612#define UART2_IRQ { IRQ_UARTINT2 }
613#define SSP_IRQ { IRQ_SSPINT }
1da177e4
LT		 614
615/* FPGA Primecells */
8f5088b6
RK		 616APB_DEVICE(aaci, "fpga:04", AACI, NULL);
617APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
618APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
619APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
1da177e4
LT		 620
621/* DevChip Primecells */
8f5088b6
RK		 622AHB_DEVICE(smc, "dev:00", SMC, NULL);
623AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
624AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
625AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
626APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
627APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
628APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
629APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
630APB_DEVICE(rtc, "dev:e8", RTC, NULL);
631APB_DEVICE(sci0, "dev:f0", SCI, NULL);
632APB_DEVICE(uart0, "dev:f1", UART0, NULL);
633APB_DEVICE(uart1, "dev:f2", UART1, NULL);
634APB_DEVICE(uart2, "dev:f3", UART2, NULL);
635APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
1da177e4
LT		 636
637static struct amba_device *amba_devs[] __initdata = {
638 &dmac_device,
639 &uart0_device,
640 &uart1_device,
641 &uart2_device,
642 &smc_device,
643 &mpmc_device,
644 &clcd_device,
645 &sctl_device,
646 &wdog_device,
647 &gpio0_device,
648 &gpio1_device,
649 &rtc_device,
650 &sci0_device,
651 &ssp0_device,
652 &aaci_device,
653 &mmc0_device,
654 &kmi0_device,
655 &kmi1_device,
656};
657
3ba7222a
GL		 658#ifdef CONFIG_OF
659/*
660 * Lookup table for attaching a specific name and platform_data pointer to
661 * devices as they get created by of_platform_populate(). Ideally this table
662 * would not exist, but the current clock implementation depends on some devices
663 * having a specific name.
664 */
665struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
d12379ac 666 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
3ba7222a
GL		 667 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
668 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
d12379ac 670 /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
3ba7222a
GL		 671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
672
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
d12379ac 677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
3ba7222a
GL		 678
679#if 0
680 /*
681 * These entries are unnecessary because no clocks referencing
682 * them. I've left them in for now as place holders in case
683 * any of them need to be added back, but they should be
684 * removed before actually committing this patch. --gcl
685 */
686 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
687 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
688 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
689 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
690 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
691
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
695 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
696 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
697 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
698 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
699 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
700#endif
701 {}
702};
703#endif
704
1da177e4 705#ifdef CONFIG_LEDS
2ad4f86b 706#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 707
708static void versatile_leds_event(led_event_t ledevt)
709{
710 unsigned long flags;
711 u32 val;
712
713 local_irq_save(flags);
714 val = readl(VA_LEDS_BASE);
715
716 switch (ledevt) {
717 case led_idle_start:
718 val = val & ~VERSATILE_SYS_LED0;
719 break;
720
721 case led_idle_end:
722 val = val | VERSATILE_SYS_LED0;
723 break;
724
725 case led_timer:
726 val = val ^ VERSATILE_SYS_LED1;
727 break;
728
729 case led_halted:
730 val = 0;
731 break;
732
733 default:
734 break;
735 }
736
737 writel(val, VA_LEDS_BASE);
738 local_irq_restore(flags);
739}
740#endif /* CONFIG_LEDS */
741
b56a7c6b
RK		 742void versatile_restart(char mode, const char *cmd)
743{
744 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
745 u32 val;
746
747 val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
748 val |= 0x105;
749
750 __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
751 __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
752 __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
753}
754
ad3bb19c
RK		 755/* Early initializations */
756void __init versatile_init_early(void)
1da177e4 757{
ad3bb19c 758 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
d1914c7e 759
ad3bb19c 760 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
0a0300dc 761 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1da177e4 762
ad3bb19c
RK		 763 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
764}
765
766void __init versatile_init(void)
767{
768 int i;
769
1da177e4 770 platform_device_register(&versatile_flash_device);
6b65cd74 771 platform_device_register(&versatile_i2c_device);
1da177e4 772 platform_device_register(&smc91x_device);
d161edfb 773 platform_device_register(&char_lcd_device);
1da177e4
LT		 774
775 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
776 struct amba_device *d = amba_devs[i];
777 amba_device_register(d, &iomem_resource);
778 }
779
780#ifdef CONFIG_LEDS
781 leds_event = versatile_leds_event;
782#endif
783}
784
785/*
786 * Where is the timer (VA)?
787 */
2ad4f86b
AV		 788#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
789#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
790#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
791#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
b49c87c2 792
1da177e4
LT		 793/*
794 * Set up timer interrupt, and return the current time in seconds.
795 */
796static void __init versatile_timer_init(void)
797{
b720f732 798 u32 val;
1da177e4
LT		 799
800 /*
801 * set clock frequency:
802 * VERSATILE_REFCLK is 32KHz
803 * VERSATILE_TIMCLK is 1MHz
804 */
2ad4f86b 805 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 806 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
807 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
808 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
809 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 810 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 811
812 /*
813 * Initialise to a known state (all timers off)
814 */
b720f732
RK		 815 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
816 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
817 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
818 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
819
fb593cf3 820 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
57cc4f7d 821 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
1da177e4
LT		 822}
823
824struct sys_timer versatile_timer = {
825 .init = versatile_timer_init,
1da177e4 826};
b49c87c2 827
Linux kernel - Deliverables
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