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MMC: MMCI: use AMBA bus accessors
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
1da177e4
LT		 21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
d052d1be 24#include <linux/platform_device.h>
1da177e4
LT		 25#include <linux/sysdev.h>
26#include <linux/interrupt.h>
a62c80e5
RK		 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h>
bbeddc43 29#include <linux/amba/pl061.h>
b49c87c2 30#include <linux/clocksource.h>
89df1272 31#include <linux/clockchips.h>
b4f151ff 32#include <linux/cnt32_to_63.h>
fced80c7 33#include <linux/io.h>
1da177e4 34
71a06da0 35#include <asm/clkdev.h>
1da177e4 36#include <asm/system.h>
a09e64fb 37#include <mach/hardware.h>
1da177e4
LT		 38#include <asm/irq.h>
39#include <asm/leds.h>
b720f732 40#include <asm/hardware/arm_timer.h>
1da177e4 41#include <asm/hardware/icst307.h>
fa0fe48f 42#include <asm/hardware/vic.h>
dc5bc8f1 43#include <asm/mach-types.h>
1da177e4
LT		 44
45#include <asm/mach/arch.h>
46#include <asm/mach/flash.h>
47#include <asm/mach/irq.h>
48#include <asm/mach/time.h>
49#include <asm/mach/map.h>
50#include <asm/mach/mmc.h>
51
52#include "core.h"
53#include "clock.h"
54
55/*
56 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
57 * is the (PA >> 12).
58 *
59 * Setup a VA for the Versatile Vectored Interrupt Controller.
60 */
2ad4f86b
AV		 61#define __io_address(n) __io(IO_ADDRESS(n))
62#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
63#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4 64
1da177e4
LT		 65static void sic_mask_irq(unsigned int irq)
66{
67 irq -= IRQ_SIC_START;
68 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
69}
70
71static void sic_unmask_irq(unsigned int irq)
72{
73 irq -= IRQ_SIC_START;
74 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
75}
76
38c677cb
DB		 77static struct irq_chip sic_chip = {
78 .name = "SIC",
1da177e4
LT		 79 .ack = sic_mask_irq,
80 .mask = sic_mask_irq,
81 .unmask = sic_unmask_irq,
82};
83
84static void
10dd5ce2 85sic_handle_irq(unsigned int irq, struct irq_desc *desc)
1da177e4
LT		 86{
87 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
88
89 if (status == 0) {
0cd61b68 90 do_bad_IRQ(irq, desc);
1da177e4
LT		 91 return;
92 }
93
94 do {
95 irq = ffs(status) - 1;
96 status &= ~(1 << irq);
97
98 irq += IRQ_SIC_START;
99
d8aa0251 100 generic_handle_irq(irq);
1da177e4
LT		 101 } while (status);
102}
103
104#if 1
105#define IRQ_MMCI0A IRQ_VICSOURCE22
106#define IRQ_AACI IRQ_VICSOURCE24
107#define IRQ_ETH IRQ_VICSOURCE25
108#define PIC_MASK 0xFFD00000
109#else
110#define IRQ_MMCI0A IRQ_SIC_MMCI0A
111#define IRQ_AACI IRQ_SIC_AACI
112#define IRQ_ETH IRQ_SIC_ETH
113#define PIC_MASK 0
114#endif
115
116void __init versatile_init_irq(void)
117{
fa0fe48f 118 unsigned int i;
1da177e4 119
c07f87f2 120 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
1da177e4 121
56f1319e 122 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
1da177e4
LT		 123
124 /* Do second interrupt controller */
125 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
126
127 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
128 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
129 set_irq_chip(i, &sic_chip);
10dd5ce2 130 set_irq_handler(i, handle_level_irq);
1da177e4
LT		 131 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
132 }
133 }
134
135 /*
136 * Interrupts on secondary controller from 0 to 8 are routed to
137 * source 31 on PIC.
138 * Interrupts from 21 to 31 are routed directly to the VIC on
139 * the corresponding number on primary controller. This is controlled
140 * by setting PIC_ENABLEx.
141 */
142 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
143}
144
145static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 146 {
147 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
148 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
149 .length = SZ_4K,
150 .type = MT_DEVICE
151 }, {
152 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
153 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
154 .length = SZ_4K,
155 .type = MT_DEVICE
156 }, {
157 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
158 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
159 .length = SZ_4K,
160 .type = MT_DEVICE
161 }, {
162 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
163 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
164 .length = SZ_4K * 9,
165 .type = MT_DEVICE
166 },
1da177e4 167#ifdef CONFIG_MACH_VERSATILE_AB
1311521f
DS		 168 {
169 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
170 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
171 .length = SZ_4K,
172 .type = MT_DEVICE
173 }, {
174 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
175 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
176 .length = SZ_64M,
177 .type = MT_DEVICE
178 },
1da177e4
LT		 179#endif
180#ifdef CONFIG_DEBUG_LL
1311521f
DS		 181 {
182 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
183 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
184 .length = SZ_4K,
185 .type = MT_DEVICE
186 },
1da177e4 187#endif
c0da085a 188#ifdef CONFIG_PCI
1311521f
DS		 189 {
190 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
191 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
192 .length = SZ_4K,
193 .type = MT_DEVICE
194 }, {
399ad77b 195 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
1311521f
DS		 196 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
197 .length = VERSATILE_PCI_BASE_SIZE,
198 .type = MT_DEVICE
199 }, {
399ad77b 200 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
1311521f
DS		 201 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
202 .length = VERSATILE_PCI_CFG_BASE_SIZE,
203 .type = MT_DEVICE
204 },
c0da085a 205#if 0
1311521f
DS		 206 {
207 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
208 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
209 .length = SZ_16M,
210 .type = MT_DEVICE
211 }, {
212 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
213 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
214 .length = SZ_16M,
215 .type = MT_DEVICE
216 }, {
217 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
218 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
219 .length = SZ_16M,
220 .type = MT_DEVICE
221 },
c0da085a 222#endif
1da177e4
LT		 223#endif
224};
225
226void __init versatile_map_io(void)
227{
228 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
229}
230
2ad4f86b 231#define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
1da177e4
LT		 232
233/*
234 * This is the Versatile sched_clock implementation. This has
752bee17
NP		 235 * a resolution of 41.7ns, and a maximum value of about 35583 days.
236 *
237 * The return value is guaranteed to be monotonic in that range as
238 * long as there is always less than 89 seconds between successive
239 * calls to this function.
1da177e4
LT		 240 */
241unsigned long long sched_clock(void)
242{
752bee17 243 unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
1da177e4 244
752bee17
NP		 245 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
246 v *= 125<<1;
247 do_div(v, 3<<1);
1da177e4
LT		 248
249 return v;
250}
251
252
2ad4f86b 253#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4
LT		 254
255static int versatile_flash_init(void)
256{
257 u32 val;
258
259 val = __raw_readl(VERSATILE_FLASHCTRL);
260 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
261 __raw_writel(val, VERSATILE_FLASHCTRL);
262
263 return 0;
264}
265
266static void versatile_flash_exit(void)
267{
268 u32 val;
269
270 val = __raw_readl(VERSATILE_FLASHCTRL);
271 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
272 __raw_writel(val, VERSATILE_FLASHCTRL);
273}
274
275static void versatile_flash_set_vpp(int on)
276{
277 u32 val;
278
279 val = __raw_readl(VERSATILE_FLASHCTRL);
280 if (on)
281 val |= VERSATILE_FLASHPROG_FLVPPEN;
282 else
283 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
284 __raw_writel(val, VERSATILE_FLASHCTRL);
285}
286
287static struct flash_platform_data versatile_flash_data = {
288 .map_name = "cfi_probe",
289 .width = 4,
290 .init = versatile_flash_init,
291 .exit = versatile_flash_exit,
292 .set_vpp = versatile_flash_set_vpp,
293};
294
295static struct resource versatile_flash_resource = {
296 .start = VERSATILE_FLASH_BASE,
a0c5a645 297 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
1da177e4
LT		 298 .flags = IORESOURCE_MEM,
299};
300
301static struct platform_device versatile_flash_device = {
302 .name = "armflash",
303 .id = 0,
304 .dev = {
305 .platform_data = &versatile_flash_data,
306 },
307 .num_resources = 1,
308 .resource = &versatile_flash_resource,
309};
310
311static struct resource smc91x_resources[] = {
312 [0] = {
313 .start = VERSATILE_ETH_BASE,
314 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = IRQ_ETH,
319 .end = IRQ_ETH,
320 .flags = IORESOURCE_IRQ,
321 },
322};
323
324static struct platform_device smc91x_device = {
325 .name = "smc91x",
326 .id = 0,
327 .num_resources = ARRAY_SIZE(smc91x_resources),
328 .resource = smc91x_resources,
329};
330
6b65cd74
RK		 331static struct resource versatile_i2c_resource = {
332 .start = VERSATILE_I2C_BASE,
333 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
334 .flags = IORESOURCE_MEM,
335};
336
337static struct platform_device versatile_i2c_device = {
338 .name = "versatile-i2c",
533ad5e6 339 .id = 0,
6b65cd74
RK		 340 .num_resources = 1,
341 .resource = &versatile_i2c_resource,
342};
343
533ad5e6
CM		 344static struct i2c_board_info versatile_i2c_board_info[] = {
345 {
346 I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
347 .type = "ds1338",
348 },
349};
350
351static int __init versatile_i2c_init(void)
352{
353 return i2c_register_board_info(0, versatile_i2c_board_info,
354 ARRAY_SIZE(versatile_i2c_board_info));
355}
356arch_initcall(versatile_i2c_init);
357
2ad4f86b 358#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 359
360unsigned int mmc_status(struct device *dev)
361{
362 struct amba_device *adev = container_of(dev, struct amba_device, dev);
363 u32 mask;
364
365 if (adev->res.start == VERSATILE_MMCI0_BASE)
366 mask = 1;
367 else
368 mask = 2;
369
370 return readl(VERSATILE_SYSMCI) & mask;
371}
372
373static struct mmc_platform_data mmc0_plat_data = {
374 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
375 .status = mmc_status,
376};
377
378/*
379 * Clock handling
380 */
381static const struct icst307_params versatile_oscvco_params = {
382 .ref = 24000,
383 .vco_max = 200000,
384 .vd_min = 4 + 8,
385 .vd_max = 511 + 8,
386 .rd_min = 1 + 2,
387 .rd_max = 127 + 2,
388};
389
390static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
391{
71a06da0
RK		 392 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
393 void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
1da177e4
LT		 394 u32 val;
395
71a06da0 396 val = readl(sys + clk->oscoff) & ~0x7ffff;
1da177e4
LT		 397 val |= vco.v | (vco.r << 9) | (vco.s << 16);
398
399 writel(0xa05f, sys_lock);
71a06da0 400 writel(val, sys + clk->oscoff);
1da177e4
LT		 401 writel(0, sys_lock);
402}
403
71a06da0 404static struct clk osc4_clk = {
1da177e4 405 .params = &versatile_oscvco_params,
71a06da0
RK		 406 .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
407 .setvco = versatile_oscvco_set,
408};
409
410/*
411 * These are fixed clocks.
412 */
413static struct clk ref24_clk = {
414 .rate = 24000000,
415};
416
982db663 417static struct clk_lookup lookups[] = {
71a06da0
RK		 418 { /* UART0 */
419 .dev_id = "dev:f1",
420 .clk = &ref24_clk,
421 }, { /* UART1 */
422 .dev_id = "dev:f2",
423 .clk = &ref24_clk,
424 }, { /* UART2 */
425 .dev_id = "dev:f3",
426 .clk = &ref24_clk,
427 }, { /* UART3 */
428 .dev_id = "fpga:09",
429 .clk = &ref24_clk,
430 }, { /* KMI0 */
431 .dev_id = "fpga:06",
432 .clk = &ref24_clk,
433 }, { /* KMI1 */
434 .dev_id = "fpga:07",
435 .clk = &ref24_clk,
436 }, { /* MMC0 */
437 .dev_id = "fpga:05",
438 .clk = &ref24_clk,
439 }, { /* MMC1 */
440 .dev_id = "fpga:0b",
441 .clk = &ref24_clk,
442 }, { /* CLCD */
443 .dev_id = "dev:20",
444 .clk = &osc4_clk,
445 }
1da177e4
LT		 446};
447
448/*
449 * CLCD support.
450 */
451#define SYS_CLCD_MODE_MASK (3 << 0)
452#define SYS_CLCD_MODE_888 (0 << 0)
453#define SYS_CLCD_MODE_5551 (1 << 0)
454#define SYS_CLCD_MODE_565_RLSB (2 << 0)
455#define SYS_CLCD_MODE_565_BLSB (3 << 0)
456#define SYS_CLCD_NLCDIOON (1 << 2)
457#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
458#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
459#define SYS_CLCD_ID_MASK (0x1f << 8)
460#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
461#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
462#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
463#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
464#define SYS_CLCD_ID_VGA (0x1f << 8)
465
466static struct clcd_panel vga = {
467 .mode = {
468 .name = "VGA",
469 .refresh = 60,
470 .xres = 640,
471 .yres = 480,
472 .pixclock = 39721,
473 .left_margin = 40,
474 .right_margin = 24,
475 .upper_margin = 32,
476 .lower_margin = 11,
477 .hsync_len = 96,
478 .vsync_len = 2,
479 .sync = 0,
480 .vmode = FB_VMODE_NONINTERLACED,
481 },
482 .width = -1,
483 .height = -1,
484 .tim2 = TIM2_BCD | TIM2_IPC,
485 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
486 .bpp = 16,
487};
488
489static struct clcd_panel sanyo_3_8_in = {
490 .mode = {
491 .name = "Sanyo QVGA",
492 .refresh = 116,
493 .xres = 320,
494 .yres = 240,
495 .pixclock = 100000,
496 .left_margin = 6,
497 .right_margin = 6,
498 .upper_margin = 5,
499 .lower_margin = 5,
500 .hsync_len = 6,
501 .vsync_len = 6,
502 .sync = 0,
503 .vmode = FB_VMODE_NONINTERLACED,
504 },
505 .width = -1,
506 .height = -1,
507 .tim2 = TIM2_BCD,
508 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
509 .bpp = 16,
510};
511
512static struct clcd_panel sanyo_2_5_in = {
513 .mode = {
514 .name = "Sanyo QVGA Portrait",
515 .refresh = 116,
516 .xres = 240,
517 .yres = 320,
518 .pixclock = 100000,
519 .left_margin = 20,
520 .right_margin = 10,
521 .upper_margin = 2,
522 .lower_margin = 2,
523 .hsync_len = 10,
524 .vsync_len = 2,
525 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
526 .vmode = FB_VMODE_NONINTERLACED,
527 },
528 .width = -1,
529 .height = -1,
530 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
531 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
532 .bpp = 16,
533};
534
535static struct clcd_panel epson_2_2_in = {
536 .mode = {
537 .name = "Epson QCIF",
538 .refresh = 390,
539 .xres = 176,
540 .yres = 220,
541 .pixclock = 62500,
542 .left_margin = 3,
543 .right_margin = 2,
544 .upper_margin = 1,
545 .lower_margin = 0,
546 .hsync_len = 3,
547 .vsync_len = 2,
548 .sync = 0,
549 .vmode = FB_VMODE_NONINTERLACED,
550 },
551 .width = -1,
552 .height = -1,
553 .tim2 = TIM2_BCD | TIM2_IPC,
554 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
555 .bpp = 16,
556};
557
558/*
559 * Detect which LCD panel is connected, and return the appropriate
560 * clcd_panel structure. Note: we do not have any information on
561 * the required timings for the 8.4in panel, so we presently assume
562 * VGA timings.
563 */
564static struct clcd_panel *versatile_clcd_panel(void)
565{
2ad4f86b 566 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 567 struct clcd_panel *panel = &vga;
568 u32 val;
569
570 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
571 if (val == SYS_CLCD_ID_SANYO_3_8)
572 panel = &sanyo_3_8_in;
573 else if (val == SYS_CLCD_ID_SANYO_2_5)
574 panel = &sanyo_2_5_in;
575 else if (val == SYS_CLCD_ID_EPSON_2_2)
576 panel = &epson_2_2_in;
577 else if (val == SYS_CLCD_ID_VGA)
578 panel = &vga;
579 else {
580 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
581 val);
582 panel = &vga;
583 }
584
585 return panel;
586}
587
588/*
589 * Disable all display connectors on the interface module.
590 */
591static void versatile_clcd_disable(struct clcd_fb *fb)
592{
2ad4f86b 593 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 594 u32 val;
595
596 val = readl(sys_clcd);
597 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
598 writel(val, sys_clcd);
599
600#ifdef CONFIG_MACH_VERSATILE_AB
601 /*
602 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
603 */
dc5bc8f1 604 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 605 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 606 unsigned long ctrl;
607
608 ctrl = readl(versatile_ib2_ctrl);
609 ctrl &= ~0x01;
610 writel(ctrl, versatile_ib2_ctrl);
611 }
612#endif
613}
614
615/*
616 * Enable the relevant connector on the interface module.
617 */
618static void versatile_clcd_enable(struct clcd_fb *fb)
619{
2ad4f86b 620 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 621 u32 val;
622
623 val = readl(sys_clcd);
624 val &= ~SYS_CLCD_MODE_MASK;
625
626 switch (fb->fb.var.green.length) {
627 case 5:
628 val |= SYS_CLCD_MODE_5551;
629 break;
630 case 6:
90ef713b 631 val |= SYS_CLCD_MODE_565_RLSB;
1da177e4
LT		 632 break;
633 case 8:
634 val |= SYS_CLCD_MODE_888;
635 break;
636 }
637
638 /*
639 * Set the MUX
640 */
641 writel(val, sys_clcd);
642
643 /*
644 * And now enable the PSUs
645 */
646 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
647 writel(val, sys_clcd);
648
649#ifdef CONFIG_MACH_VERSATILE_AB
650 /*
651 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
652 */
dc5bc8f1 653 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 654 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 655 unsigned long ctrl;
656
657 ctrl = readl(versatile_ib2_ctrl);
658 ctrl |= 0x01;
659 writel(ctrl, versatile_ib2_ctrl);
660 }
661#endif
662}
663
664static unsigned long framesize = SZ_1M;
665
666static int versatile_clcd_setup(struct clcd_fb *fb)
667{
668 dma_addr_t dma;
669
670 fb->panel = versatile_clcd_panel();
671
672 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
673 &dma, GFP_KERNEL);
674 if (!fb->fb.screen_base) {
675 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
676 return -ENOMEM;
677 }
678
679 fb->fb.fix.smem_start = dma;
680 fb->fb.fix.smem_len = framesize;
681
682 return 0;
683}
684
685static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
686{
687 return dma_mmap_writecombine(&fb->dev->dev, vma,
688 fb->fb.screen_base,
689 fb->fb.fix.smem_start,
690 fb->fb.fix.smem_len);
691}
692
693static void versatile_clcd_remove(struct clcd_fb *fb)
694{
695 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
696 fb->fb.screen_base, fb->fb.fix.smem_start);
697}
698
699static struct clcd_board clcd_plat_data = {
700 .name = "Versatile",
701 .check = clcdfb_check,
702 .decode = clcdfb_decode,
703 .disable = versatile_clcd_disable,
704 .enable = versatile_clcd_enable,
705 .setup = versatile_clcd_setup,
706 .mmap = versatile_clcd_mmap,
707 .remove = versatile_clcd_remove,
708};
709
bbeddc43
RK		 710static struct pl061_platform_data gpio0_plat_data = {
711 .gpio_base = 0,
712 .irq_base = IRQ_GPIO0_START,
713};
714
715static struct pl061_platform_data gpio1_plat_data = {
716 .gpio_base = 8,
717 .irq_base = IRQ_GPIO1_START,
718};
719
1da177e4
LT		 720#define AACI_IRQ { IRQ_AACI, NO_IRQ }
721#define AACI_DMA { 0x80, 0x81 }
722#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
723#define MMCI0_DMA { 0x84, 0 }
724#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
725#define KMI0_DMA { 0, 0 }
726#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
727#define KMI1_DMA { 0, 0 }
728
729/*
730 * These devices are connected directly to the multi-layer AHB switch
731 */
732#define SMC_IRQ { NO_IRQ, NO_IRQ }
733#define SMC_DMA { 0, 0 }
734#define MPMC_IRQ { NO_IRQ, NO_IRQ }
735#define MPMC_DMA { 0, 0 }
736#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
737#define CLCD_DMA { 0, 0 }
738#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
739#define DMAC_DMA { 0, 0 }
740
741/*
742 * These devices are connected via the core APB bridge
743 */
744#define SCTL_IRQ { NO_IRQ, NO_IRQ }
745#define SCTL_DMA { 0, 0 }
746#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
747#define WATCHDOG_DMA { 0, 0 }
748#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
749#define GPIO0_DMA { 0, 0 }
750#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
751#define GPIO1_DMA { 0, 0 }
752#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
753#define RTC_DMA { 0, 0 }
754
755/*
756 * These devices are connected via the DMA APB bridge
757 */
758#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
759#define SCI_DMA { 7, 6 }
760#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
761#define UART0_DMA { 15, 14 }
762#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
763#define UART1_DMA { 13, 12 }
764#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
765#define UART2_DMA { 11, 10 }
766#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
767#define SSP_DMA { 9, 8 }
768
769/* FPGA Primecells */
770AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
771AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
772AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
773AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
774
775/* DevChip Primecells */
776AMBA_DEVICE(smc, "dev:00", SMC, NULL);
777AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
778AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
779AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
780AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
781AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
bbeddc43
RK		 782AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
783AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
1da177e4
LT		 784AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
785AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
786AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
787AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
788AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
789AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
790
791static struct amba_device *amba_devs[] __initdata = {
792 &dmac_device,
793 &uart0_device,
794 &uart1_device,
795 &uart2_device,
796 &smc_device,
797 &mpmc_device,
798 &clcd_device,
799 &sctl_device,
800 &wdog_device,
801 &gpio0_device,
802 &gpio1_device,
803 &rtc_device,
804 &sci0_device,
805 &ssp0_device,
806 &aaci_device,
807 &mmc0_device,
808 &kmi0_device,
809 &kmi1_device,
810};
811
812#ifdef CONFIG_LEDS
2ad4f86b 813#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 814
815static void versatile_leds_event(led_event_t ledevt)
816{
817 unsigned long flags;
818 u32 val;
819
820 local_irq_save(flags);
821 val = readl(VA_LEDS_BASE);
822
823 switch (ledevt) {
824 case led_idle_start:
825 val = val & ~VERSATILE_SYS_LED0;
826 break;
827
828 case led_idle_end:
829 val = val | VERSATILE_SYS_LED0;
830 break;
831
832 case led_timer:
833 val = val ^ VERSATILE_SYS_LED1;
834 break;
835
836 case led_halted:
837 val = 0;
838 break;
839
840 default:
841 break;
842 }
843
844 writel(val, VA_LEDS_BASE);
845 local_irq_restore(flags);
846}
847#endif /* CONFIG_LEDS */
848
849void __init versatile_init(void)
850{
851 int i;
852
71a06da0
RK		 853 for (i = 0; i < ARRAY_SIZE(lookups); i++)
854 clkdev_add(&lookups[i]);
1da177e4
LT		 855
856 platform_device_register(&versatile_flash_device);
6b65cd74 857 platform_device_register(&versatile_i2c_device);
1da177e4
LT		 858 platform_device_register(&smc91x_device);
859
860 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
861 struct amba_device *d = amba_devs[i];
862 amba_device_register(d, &iomem_resource);
863 }
864
865#ifdef CONFIG_LEDS
866 leds_event = versatile_leds_event;
867#endif
868}
869
870/*
871 * Where is the timer (VA)?
872 */
2ad4f86b
AV		 873#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
874#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
875#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
876#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
877#define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
1da177e4
LT		 878
879/*
880 * How long is the timer interval?
881 */
882#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
883#if TIMER_INTERVAL >= 0x100000
b720f732
RK		 884#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
885#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
1da177e4
LT		 886#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
887#elif TIMER_INTERVAL >= 0x10000
888#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
b720f732 889#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
1da177e4
LT		 890#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
891#else
892#define TIMER_RELOAD (TIMER_INTERVAL)
b720f732 893#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
1da177e4
LT		 894#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
895#endif
896
89df1272
KH		 897static void timer_set_mode(enum clock_event_mode mode,
898 struct clock_event_device *clk)
899{
900 unsigned long ctrl;
901
902 switch(mode) {
903 case CLOCK_EVT_MODE_PERIODIC:
904 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
905
906 ctrl = TIMER_CTRL_PERIODIC;
907 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
908 break;
909 case CLOCK_EVT_MODE_ONESHOT:
910 /* period set, and timer enabled in 'next_event' hook */
911 ctrl = TIMER_CTRL_ONESHOT;
912 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
913 break;
914 case CLOCK_EVT_MODE_UNUSED:
915 case CLOCK_EVT_MODE_SHUTDOWN:
916 default:
917 ctrl = 0;
918 }
919
920 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
921}
922
923static int timer_set_next_event(unsigned long evt,
924 struct clock_event_device *unused)
925{
926 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
927
928 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
929 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
930
931 return 0;
932}
933
934static struct clock_event_device timer0_clockevent = {
935 .name = "timer0",
936 .shift = 32,
937 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
938 .set_mode = timer_set_mode,
939 .set_next_event = timer_set_next_event,
940};
941
1da177e4
LT		 942/*
943 * IRQ handler for the timer
944 */
0cd61b68 945static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
1da177e4 946{
89df1272 947 struct clock_event_device *evt = &timer0_clockevent;
1da177e4 948
b720f732 949 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
1da177e4 950
89df1272 951 evt->event_handler(evt);
1da177e4
LT		 952
953 return IRQ_HANDLED;
954}
955
956static struct irqaction versatile_timer_irq = {
957 .name = "Versatile Timer Tick",
b30fabad 958 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
09b8b5f8 959 .handler = versatile_timer_interrupt,
1da177e4
LT		 960};
961
8e19608e 962static cycle_t versatile_get_cycles(struct clocksource *cs)
b49c87c2
KH		 963{
964 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
965}
966
967static struct clocksource clocksource_versatile = {
968 .name = "timer3",
969 .rating = 200,
970 .read = versatile_get_cycles,
971 .mask = CLOCKSOURCE_MASK(32),
972 .shift = 20,
973 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
974};
975
976static int __init versatile_clocksource_init(void)
977{
978 /* setup timer3 as free-running clocksource */
979 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
980 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
981 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
982 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
983 TIMER3_VA_BASE + TIMER_CTRL);
984
985 clocksource_versatile.mult =
986 clocksource_khz2mult(1000, clocksource_versatile.shift);
987 clocksource_register(&clocksource_versatile);
988
989 return 0;
990}
991
1da177e4
LT		 992/*
993 * Set up timer interrupt, and return the current time in seconds.
994 */
995static void __init versatile_timer_init(void)
996{
b720f732 997 u32 val;
1da177e4
LT		 998
999 /*
1000 * set clock frequency:
1001 * VERSATILE_REFCLK is 32KHz
1002 * VERSATILE_TIMCLK is 1MHz
1003 */
2ad4f86b 1004 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 1005 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
1006 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
1007 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
1008 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 1009 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 1010
1011 /*
1012 * Initialise to a known state (all timers off)
1013 */
b720f732
RK		 1014 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
1015 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
1016 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
1017 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
1018
1da177e4
LT		 1019 /*
1020 * Make irqs happen for the system timer
1021 */
1022 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
b49c87c2
KH		 1023
1024 versatile_clocksource_init();
89df1272
KH		 1025
1026 timer0_clockevent.mult =
1027 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
1028 timer0_clockevent.max_delta_ns =
1029 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1030 timer0_clockevent.min_delta_ns =
1031 clockevent_delta2ns(0xf, &timer0_clockevent);
1032
320ab2b0 1033 timer0_clockevent.cpumask = cpumask_of(0);
89df1272 1034 clockevents_register_device(&timer0_clockevent);
1da177e4
LT		 1035}
1036
1037struct sys_timer versatile_timer = {
1038 .init = versatile_timer_init,
1da177e4 1039};
b49c87c2 1040
Linux kernel - Deliverables
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