projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial blind fixup for arm for irq changes
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
1da177e4
LT		 21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
d052d1be 24#include <linux/platform_device.h>
1da177e4
LT		 25#include <linux/sysdev.h>
26#include <linux/interrupt.h>
a62c80e5
RK		 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h>
1da177e4
LT		 29
30#include <asm/system.h>
31#include <asm/hardware.h>
32#include <asm/io.h>
33#include <asm/irq.h>
34#include <asm/leds.h>
b720f732 35#include <asm/hardware/arm_timer.h>
1da177e4 36#include <asm/hardware/icst307.h>
fa0fe48f 37#include <asm/hardware/vic.h>
dc5bc8f1 38#include <asm/mach-types.h>
1da177e4
LT		 39
40#include <asm/mach/arch.h>
41#include <asm/mach/flash.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/time.h>
44#include <asm/mach/map.h>
45#include <asm/mach/mmc.h>
46
47#include "core.h"
48#include "clock.h"
49
50/*
51 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
52 * is the (PA >> 12).
53 *
54 * Setup a VA for the Versatile Vectored Interrupt Controller.
55 */
2ad4f86b
AV		 56#define __io_address(n) __io(IO_ADDRESS(n))
57#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
58#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4 59
1da177e4
LT		 60static void sic_mask_irq(unsigned int irq)
61{
62 irq -= IRQ_SIC_START;
63 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
64}
65
66static void sic_unmask_irq(unsigned int irq)
67{
68 irq -= IRQ_SIC_START;
69 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
70}
71
38c677cb
DB		 72static struct irq_chip sic_chip = {
73 .name = "SIC",
1da177e4
LT		 74 .ack = sic_mask_irq,
75 .mask = sic_mask_irq,
76 .unmask = sic_unmask_irq,
77};
78
79static void
0cd61b68 80sic_handle_irq(unsigned int irq, struct irqdesc *desc)
1da177e4
LT		 81{
82 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
83
84 if (status == 0) {
0cd61b68 85 do_bad_IRQ(irq, desc);
1da177e4
LT		 86 return;
87 }
88
89 do {
90 irq = ffs(status) - 1;
91 status &= ~(1 << irq);
92
93 irq += IRQ_SIC_START;
94
95 desc = irq_desc + irq;
0cd61b68 96 desc_handle_irq(irq, desc);
1da177e4
LT		 97 } while (status);
98}
99
100#if 1
101#define IRQ_MMCI0A IRQ_VICSOURCE22
102#define IRQ_AACI IRQ_VICSOURCE24
103#define IRQ_ETH IRQ_VICSOURCE25
104#define PIC_MASK 0xFFD00000
105#else
106#define IRQ_MMCI0A IRQ_SIC_MMCI0A
107#define IRQ_AACI IRQ_SIC_AACI
108#define IRQ_ETH IRQ_SIC_ETH
109#define PIC_MASK 0
110#endif
111
112void __init versatile_init_irq(void)
113{
fa0fe48f 114 unsigned int i;
1da177e4 115
56f1319e 116 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
1da177e4 117
56f1319e 118 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
1da177e4
LT		 119
120 /* Do second interrupt controller */
121 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
122
123 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
124 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
125 set_irq_chip(i, &sic_chip);
126 set_irq_handler(i, do_level_IRQ);
127 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
128 }
129 }
130
131 /*
132 * Interrupts on secondary controller from 0 to 8 are routed to
133 * source 31 on PIC.
134 * Interrupts from 21 to 31 are routed directly to the VIC on
135 * the corresponding number on primary controller. This is controlled
136 * by setting PIC_ENABLEx.
137 */
138 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
139}
140
141static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 142 {
143 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
144 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
145 .length = SZ_4K,
146 .type = MT_DEVICE
147 }, {
148 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
149 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
150 .length = SZ_4K,
151 .type = MT_DEVICE
152 }, {
153 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
154 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
155 .length = SZ_4K,
156 .type = MT_DEVICE
157 }, {
158 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
159 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
160 .length = SZ_4K * 9,
161 .type = MT_DEVICE
162 },
1da177e4 163#ifdef CONFIG_MACH_VERSATILE_AB
1311521f
DS		 164 {
165 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
166 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
167 .length = SZ_4K,
168 .type = MT_DEVICE
169 }, {
170 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
171 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
172 .length = SZ_64M,
173 .type = MT_DEVICE
174 },
1da177e4
LT		 175#endif
176#ifdef CONFIG_DEBUG_LL
1311521f
DS		 177 {
178 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
179 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
180 .length = SZ_4K,
181 .type = MT_DEVICE
182 },
1da177e4 183#endif
c0da085a 184#ifdef CONFIG_PCI
1311521f
DS		 185 {
186 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
187 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
188 .length = SZ_4K,
189 .type = MT_DEVICE
190 }, {
191 .virtual = VERSATILE_PCI_VIRT_BASE,
192 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
193 .length = VERSATILE_PCI_BASE_SIZE,
194 .type = MT_DEVICE
195 }, {
196 .virtual = VERSATILE_PCI_CFG_VIRT_BASE,
197 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
198 .length = VERSATILE_PCI_CFG_BASE_SIZE,
199 .type = MT_DEVICE
200 },
c0da085a 201#if 0
1311521f
DS		 202 {
203 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
204 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
205 .length = SZ_16M,
206 .type = MT_DEVICE
207 }, {
208 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
209 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
210 .length = SZ_16M,
211 .type = MT_DEVICE
212 }, {
213 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
214 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
215 .length = SZ_16M,
216 .type = MT_DEVICE
217 },
c0da085a 218#endif
1da177e4
LT		 219#endif
220};
221
222void __init versatile_map_io(void)
223{
224 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
225}
226
2ad4f86b 227#define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
1da177e4
LT		 228
229/*
230 * This is the Versatile sched_clock implementation. This has
231 * a resolution of 41.7ns, and a maximum value of about 179s.
232 */
233unsigned long long sched_clock(void)
234{
235 unsigned long long v;
236
237 v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
238 do_div(v, 3);
239
240 return v;
241}
242
243
2ad4f86b 244#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4
LT		 245
246static int versatile_flash_init(void)
247{
248 u32 val;
249
250 val = __raw_readl(VERSATILE_FLASHCTRL);
251 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
252 __raw_writel(val, VERSATILE_FLASHCTRL);
253
254 return 0;
255}
256
257static void versatile_flash_exit(void)
258{
259 u32 val;
260
261 val = __raw_readl(VERSATILE_FLASHCTRL);
262 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
263 __raw_writel(val, VERSATILE_FLASHCTRL);
264}
265
266static void versatile_flash_set_vpp(int on)
267{
268 u32 val;
269
270 val = __raw_readl(VERSATILE_FLASHCTRL);
271 if (on)
272 val |= VERSATILE_FLASHPROG_FLVPPEN;
273 else
274 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
275 __raw_writel(val, VERSATILE_FLASHCTRL);
276}
277
278static struct flash_platform_data versatile_flash_data = {
279 .map_name = "cfi_probe",
280 .width = 4,
281 .init = versatile_flash_init,
282 .exit = versatile_flash_exit,
283 .set_vpp = versatile_flash_set_vpp,
284};
285
286static struct resource versatile_flash_resource = {
287 .start = VERSATILE_FLASH_BASE,
a0c5a645 288 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
1da177e4
LT		 289 .flags = IORESOURCE_MEM,
290};
291
292static struct platform_device versatile_flash_device = {
293 .name = "armflash",
294 .id = 0,
295 .dev = {
296 .platform_data = &versatile_flash_data,
297 },
298 .num_resources = 1,
299 .resource = &versatile_flash_resource,
300};
301
302static struct resource smc91x_resources[] = {
303 [0] = {
304 .start = VERSATILE_ETH_BASE,
305 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
306 .flags = IORESOURCE_MEM,
307 },
308 [1] = {
309 .start = IRQ_ETH,
310 .end = IRQ_ETH,
311 .flags = IORESOURCE_IRQ,
312 },
313};
314
315static struct platform_device smc91x_device = {
316 .name = "smc91x",
317 .id = 0,
318 .num_resources = ARRAY_SIZE(smc91x_resources),
319 .resource = smc91x_resources,
320};
321
2ad4f86b 322#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 323
324unsigned int mmc_status(struct device *dev)
325{
326 struct amba_device *adev = container_of(dev, struct amba_device, dev);
327 u32 mask;
328
329 if (adev->res.start == VERSATILE_MMCI0_BASE)
330 mask = 1;
331 else
332 mask = 2;
333
334 return readl(VERSATILE_SYSMCI) & mask;
335}
336
337static struct mmc_platform_data mmc0_plat_data = {
338 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
339 .status = mmc_status,
340};
341
342/*
343 * Clock handling
344 */
345static const struct icst307_params versatile_oscvco_params = {
346 .ref = 24000,
347 .vco_max = 200000,
348 .vd_min = 4 + 8,
349 .vd_max = 511 + 8,
350 .rd_min = 1 + 2,
351 .rd_max = 127 + 2,
352};
353
354static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
355{
2ad4f86b 356 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
dc5bc8f1 357 void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
1da177e4
LT		 358 u32 val;
359
360 val = readl(sys_osc) & ~0x7ffff;
361 val |= vco.v | (vco.r << 9) | (vco.s << 16);
362
363 writel(0xa05f, sys_lock);
364 writel(val, sys_osc);
365 writel(0, sys_lock);
366}
367
368static struct clk versatile_clcd_clk = {
369 .name = "CLCDCLK",
370 .params = &versatile_oscvco_params,
371 .setvco = versatile_oscvco_set,
372};
373
374/*
375 * CLCD support.
376 */
377#define SYS_CLCD_MODE_MASK (3 << 0)
378#define SYS_CLCD_MODE_888 (0 << 0)
379#define SYS_CLCD_MODE_5551 (1 << 0)
380#define SYS_CLCD_MODE_565_RLSB (2 << 0)
381#define SYS_CLCD_MODE_565_BLSB (3 << 0)
382#define SYS_CLCD_NLCDIOON (1 << 2)
383#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
384#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
385#define SYS_CLCD_ID_MASK (0x1f << 8)
386#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
387#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
388#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
389#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
390#define SYS_CLCD_ID_VGA (0x1f << 8)
391
392static struct clcd_panel vga = {
393 .mode = {
394 .name = "VGA",
395 .refresh = 60,
396 .xres = 640,
397 .yres = 480,
398 .pixclock = 39721,
399 .left_margin = 40,
400 .right_margin = 24,
401 .upper_margin = 32,
402 .lower_margin = 11,
403 .hsync_len = 96,
404 .vsync_len = 2,
405 .sync = 0,
406 .vmode = FB_VMODE_NONINTERLACED,
407 },
408 .width = -1,
409 .height = -1,
410 .tim2 = TIM2_BCD | TIM2_IPC,
411 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
412 .bpp = 16,
413};
414
415static struct clcd_panel sanyo_3_8_in = {
416 .mode = {
417 .name = "Sanyo QVGA",
418 .refresh = 116,
419 .xres = 320,
420 .yres = 240,
421 .pixclock = 100000,
422 .left_margin = 6,
423 .right_margin = 6,
424 .upper_margin = 5,
425 .lower_margin = 5,
426 .hsync_len = 6,
427 .vsync_len = 6,
428 .sync = 0,
429 .vmode = FB_VMODE_NONINTERLACED,
430 },
431 .width = -1,
432 .height = -1,
433 .tim2 = TIM2_BCD,
434 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
435 .bpp = 16,
436};
437
438static struct clcd_panel sanyo_2_5_in = {
439 .mode = {
440 .name = "Sanyo QVGA Portrait",
441 .refresh = 116,
442 .xres = 240,
443 .yres = 320,
444 .pixclock = 100000,
445 .left_margin = 20,
446 .right_margin = 10,
447 .upper_margin = 2,
448 .lower_margin = 2,
449 .hsync_len = 10,
450 .vsync_len = 2,
451 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
452 .vmode = FB_VMODE_NONINTERLACED,
453 },
454 .width = -1,
455 .height = -1,
456 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
457 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
458 .bpp = 16,
459};
460
461static struct clcd_panel epson_2_2_in = {
462 .mode = {
463 .name = "Epson QCIF",
464 .refresh = 390,
465 .xres = 176,
466 .yres = 220,
467 .pixclock = 62500,
468 .left_margin = 3,
469 .right_margin = 2,
470 .upper_margin = 1,
471 .lower_margin = 0,
472 .hsync_len = 3,
473 .vsync_len = 2,
474 .sync = 0,
475 .vmode = FB_VMODE_NONINTERLACED,
476 },
477 .width = -1,
478 .height = -1,
479 .tim2 = TIM2_BCD | TIM2_IPC,
480 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
481 .bpp = 16,
482};
483
484/*
485 * Detect which LCD panel is connected, and return the appropriate
486 * clcd_panel structure. Note: we do not have any information on
487 * the required timings for the 8.4in panel, so we presently assume
488 * VGA timings.
489 */
490static struct clcd_panel *versatile_clcd_panel(void)
491{
2ad4f86b 492 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 493 struct clcd_panel *panel = &vga;
494 u32 val;
495
496 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
497 if (val == SYS_CLCD_ID_SANYO_3_8)
498 panel = &sanyo_3_8_in;
499 else if (val == SYS_CLCD_ID_SANYO_2_5)
500 panel = &sanyo_2_5_in;
501 else if (val == SYS_CLCD_ID_EPSON_2_2)
502 panel = &epson_2_2_in;
503 else if (val == SYS_CLCD_ID_VGA)
504 panel = &vga;
505 else {
506 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
507 val);
508 panel = &vga;
509 }
510
511 return panel;
512}
513
514/*
515 * Disable all display connectors on the interface module.
516 */
517static void versatile_clcd_disable(struct clcd_fb *fb)
518{
2ad4f86b 519 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 520 u32 val;
521
522 val = readl(sys_clcd);
523 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
524 writel(val, sys_clcd);
525
526#ifdef CONFIG_MACH_VERSATILE_AB
527 /*
528 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
529 */
dc5bc8f1 530 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 531 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 532 unsigned long ctrl;
533
534 ctrl = readl(versatile_ib2_ctrl);
535 ctrl &= ~0x01;
536 writel(ctrl, versatile_ib2_ctrl);
537 }
538#endif
539}
540
541/*
542 * Enable the relevant connector on the interface module.
543 */
544static void versatile_clcd_enable(struct clcd_fb *fb)
545{
2ad4f86b 546 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 547 u32 val;
548
549 val = readl(sys_clcd);
550 val &= ~SYS_CLCD_MODE_MASK;
551
552 switch (fb->fb.var.green.length) {
553 case 5:
554 val |= SYS_CLCD_MODE_5551;
555 break;
556 case 6:
90ef713b 557 val |= SYS_CLCD_MODE_565_RLSB;
1da177e4
LT		 558 break;
559 case 8:
560 val |= SYS_CLCD_MODE_888;
561 break;
562 }
563
564 /*
565 * Set the MUX
566 */
567 writel(val, sys_clcd);
568
569 /*
570 * And now enable the PSUs
571 */
572 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
573 writel(val, sys_clcd);
574
575#ifdef CONFIG_MACH_VERSATILE_AB
576 /*
577 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
578 */
dc5bc8f1 579 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 580 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 581 unsigned long ctrl;
582
583 ctrl = readl(versatile_ib2_ctrl);
584 ctrl |= 0x01;
585 writel(ctrl, versatile_ib2_ctrl);
586 }
587#endif
588}
589
590static unsigned long framesize = SZ_1M;
591
592static int versatile_clcd_setup(struct clcd_fb *fb)
593{
594 dma_addr_t dma;
595
596 fb->panel = versatile_clcd_panel();
597
598 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
599 &dma, GFP_KERNEL);
600 if (!fb->fb.screen_base) {
601 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
602 return -ENOMEM;
603 }
604
605 fb->fb.fix.smem_start = dma;
606 fb->fb.fix.smem_len = framesize;
607
608 return 0;
609}
610
611static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
612{
613 return dma_mmap_writecombine(&fb->dev->dev, vma,
614 fb->fb.screen_base,
615 fb->fb.fix.smem_start,
616 fb->fb.fix.smem_len);
617}
618
619static void versatile_clcd_remove(struct clcd_fb *fb)
620{
621 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
622 fb->fb.screen_base, fb->fb.fix.smem_start);
623}
624
625static struct clcd_board clcd_plat_data = {
626 .name = "Versatile",
627 .check = clcdfb_check,
628 .decode = clcdfb_decode,
629 .disable = versatile_clcd_disable,
630 .enable = versatile_clcd_enable,
631 .setup = versatile_clcd_setup,
632 .mmap = versatile_clcd_mmap,
633 .remove = versatile_clcd_remove,
634};
635
636#define AACI_IRQ { IRQ_AACI, NO_IRQ }
637#define AACI_DMA { 0x80, 0x81 }
638#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
639#define MMCI0_DMA { 0x84, 0 }
640#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
641#define KMI0_DMA { 0, 0 }
642#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
643#define KMI1_DMA { 0, 0 }
644
645/*
646 * These devices are connected directly to the multi-layer AHB switch
647 */
648#define SMC_IRQ { NO_IRQ, NO_IRQ }
649#define SMC_DMA { 0, 0 }
650#define MPMC_IRQ { NO_IRQ, NO_IRQ }
651#define MPMC_DMA { 0, 0 }
652#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
653#define CLCD_DMA { 0, 0 }
654#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
655#define DMAC_DMA { 0, 0 }
656
657/*
658 * These devices are connected via the core APB bridge
659 */
660#define SCTL_IRQ { NO_IRQ, NO_IRQ }
661#define SCTL_DMA { 0, 0 }
662#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
663#define WATCHDOG_DMA { 0, 0 }
664#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
665#define GPIO0_DMA { 0, 0 }
666#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
667#define GPIO1_DMA { 0, 0 }
668#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
669#define RTC_DMA { 0, 0 }
670
671/*
672 * These devices are connected via the DMA APB bridge
673 */
674#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
675#define SCI_DMA { 7, 6 }
676#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
677#define UART0_DMA { 15, 14 }
678#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
679#define UART1_DMA { 13, 12 }
680#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
681#define UART2_DMA { 11, 10 }
682#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
683#define SSP_DMA { 9, 8 }
684
685/* FPGA Primecells */
686AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
687AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
688AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
689AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
690
691/* DevChip Primecells */
692AMBA_DEVICE(smc, "dev:00", SMC, NULL);
693AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
694AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
695AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
696AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
697AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
698AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
699AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
700AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
701AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
702AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
703AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
704AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
705AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
706
707static struct amba_device *amba_devs[] __initdata = {
708 &dmac_device,
709 &uart0_device,
710 &uart1_device,
711 &uart2_device,
712 &smc_device,
713 &mpmc_device,
714 &clcd_device,
715 &sctl_device,
716 &wdog_device,
717 &gpio0_device,
718 &gpio1_device,
719 &rtc_device,
720 &sci0_device,
721 &ssp0_device,
722 &aaci_device,
723 &mmc0_device,
724 &kmi0_device,
725 &kmi1_device,
726};
727
728#ifdef CONFIG_LEDS
2ad4f86b 729#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 730
731static void versatile_leds_event(led_event_t ledevt)
732{
733 unsigned long flags;
734 u32 val;
735
736 local_irq_save(flags);
737 val = readl(VA_LEDS_BASE);
738
739 switch (ledevt) {
740 case led_idle_start:
741 val = val & ~VERSATILE_SYS_LED0;
742 break;
743
744 case led_idle_end:
745 val = val | VERSATILE_SYS_LED0;
746 break;
747
748 case led_timer:
749 val = val ^ VERSATILE_SYS_LED1;
750 break;
751
752 case led_halted:
753 val = 0;
754 break;
755
756 default:
757 break;
758 }
759
760 writel(val, VA_LEDS_BASE);
761 local_irq_restore(flags);
762}
763#endif /* CONFIG_LEDS */
764
765void __init versatile_init(void)
766{
767 int i;
768
769 clk_register(&versatile_clcd_clk);
770
771 platform_device_register(&versatile_flash_device);
772 platform_device_register(&smc91x_device);
773
774 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
775 struct amba_device *d = amba_devs[i];
776 amba_device_register(d, &iomem_resource);
777 }
778
779#ifdef CONFIG_LEDS
780 leds_event = versatile_leds_event;
781#endif
782}
783
784/*
785 * Where is the timer (VA)?
786 */
2ad4f86b
AV		 787#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
788#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
789#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
790#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
791#define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
1da177e4
LT		 792
793/*
794 * How long is the timer interval?
795 */
796#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
797#if TIMER_INTERVAL >= 0x100000
b720f732
RK		 798#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
799#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
1da177e4
LT		 800#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
801#elif TIMER_INTERVAL >= 0x10000
802#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
b720f732 803#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
1da177e4
LT		 804#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
805#else
806#define TIMER_RELOAD (TIMER_INTERVAL)
b720f732 807#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
1da177e4
LT		 808#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
809#endif
810
1da177e4
LT		 811/*
812 * Returns number of ms since last clock interrupt. Note that interrupts
813 * will have been disabled by do_gettimeoffset()
814 */
815static unsigned long versatile_gettimeoffset(void)
816{
1da177e4
LT		 817 unsigned long ticks1, ticks2, status;
818
819 /*
820 * Get the current number of ticks. Note that there is a race
821 * condition between us reading the timer and checking for
822 * an interrupt. We get around this by ensuring that the
823 * counter has not reloaded between our two reads.
824 */
b720f732 825 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
1da177e4
LT		 826 do {
827 ticks1 = ticks2;
fa0fe48f 828 status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
b720f732 829 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
1da177e4
LT		 830 } while (ticks2 > ticks1);
831
832 /*
833 * Number of ticks since last interrupt.
834 */
835 ticks1 = TIMER_RELOAD - ticks2;
836
837 /*
838 * Interrupt pending? If so, we've reloaded once already.
839 *
840 * FIXME: Need to check this is effectively timer 0 that expires
841 */
842 if (status & IRQMASK_TIMERINT0_1)
843 ticks1 += TIMER_RELOAD;
844
845 /*
846 * Convert the ticks to usecs
847 */
848 return TICKS2USECS(ticks1);
849}
850
851/*
852 * IRQ handler for the timer
853 */
0cd61b68 854static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
1da177e4 855{
1da177e4
LT		 856 write_seqlock(&xtime_lock);
857
858 // ...clear the interrupt
b720f732 859 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
1da177e4 860
0cd61b68 861 timer_tick();
1da177e4
LT		 862
863 write_sequnlock(&xtime_lock);
864
865 return IRQ_HANDLED;
866}
867
868static struct irqaction versatile_timer_irq = {
869 .name = "Versatile Timer Tick",
52e405ea 870 .flags = IRQF_DISABLED | IRQF_TIMER,
09b8b5f8 871 .handler = versatile_timer_interrupt,
1da177e4
LT		 872};
873
874/*
875 * Set up timer interrupt, and return the current time in seconds.
876 */
877static void __init versatile_timer_init(void)
878{
b720f732 879 u32 val;
1da177e4
LT		 880
881 /*
882 * set clock frequency:
883 * VERSATILE_REFCLK is 32KHz
884 * VERSATILE_TIMCLK is 1MHz
885 */
2ad4f86b 886 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 887 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
888 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
889 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
890 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 891 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 892
893 /*
894 * Initialise to a known state (all timers off)
895 */
b720f732
RK		 896 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
897 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
898 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
899 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
900
901 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
902 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
903 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
904 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
1da177e4
LT		 905
906 /*
907 * Make irqs happen for the system timer
908 */
909 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
910}
911
912struct sys_timer versatile_timer = {
913 .init = versatile_timer_init,
914 .offset = versatile_gettimeoffset,
915};
Linux kernel - Deliverables
This page took 0.213168 seconds and 5 git commands to generate.