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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-versatile/core.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/dma-mapping.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
1da177e4 LT |
25 | #include <linux/sysdev.h> |
26 | #include <linux/interrupt.h> | |
a62c80e5 RK |
27 | #include <linux/amba/bus.h> |
28 | #include <linux/amba/clcd.h> | |
bbeddc43 | 29 | #include <linux/amba/pl061.h> |
6ef297f8 | 30 | #include <linux/amba/mmci.h> |
b49c87c2 | 31 | #include <linux/clocksource.h> |
89df1272 | 32 | #include <linux/clockchips.h> |
b4f151ff | 33 | #include <linux/cnt32_to_63.h> |
fced80c7 | 34 | #include <linux/io.h> |
1da177e4 | 35 | |
71a06da0 | 36 | #include <asm/clkdev.h> |
1da177e4 | 37 | #include <asm/system.h> |
a09e64fb | 38 | #include <mach/hardware.h> |
1da177e4 LT |
39 | #include <asm/irq.h> |
40 | #include <asm/leds.h> | |
b720f732 | 41 | #include <asm/hardware/arm_timer.h> |
1da177e4 | 42 | #include <asm/hardware/icst307.h> |
fa0fe48f | 43 | #include <asm/hardware/vic.h> |
dc5bc8f1 | 44 | #include <asm/mach-types.h> |
1da177e4 LT |
45 | |
46 | #include <asm/mach/arch.h> | |
47 | #include <asm/mach/flash.h> | |
48 | #include <asm/mach/irq.h> | |
49 | #include <asm/mach/time.h> | |
50 | #include <asm/mach/map.h> | |
1da177e4 LT |
51 | |
52 | #include "core.h" | |
53 | #include "clock.h" | |
54 | ||
55 | /* | |
56 | * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx | |
57 | * is the (PA >> 12). | |
58 | * | |
59 | * Setup a VA for the Versatile Vectored Interrupt Controller. | |
60 | */ | |
2ad4f86b AV |
61 | #define __io_address(n) __io(IO_ADDRESS(n)) |
62 | #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) | |
63 | #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) | |
1da177e4 | 64 | |
1da177e4 LT |
65 | static void sic_mask_irq(unsigned int irq) |
66 | { | |
67 | irq -= IRQ_SIC_START; | |
68 | writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); | |
69 | } | |
70 | ||
71 | static void sic_unmask_irq(unsigned int irq) | |
72 | { | |
73 | irq -= IRQ_SIC_START; | |
74 | writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET); | |
75 | } | |
76 | ||
38c677cb DB |
77 | static struct irq_chip sic_chip = { |
78 | .name = "SIC", | |
1da177e4 LT |
79 | .ack = sic_mask_irq, |
80 | .mask = sic_mask_irq, | |
81 | .unmask = sic_unmask_irq, | |
82 | }; | |
83 | ||
84 | static void | |
10dd5ce2 | 85 | sic_handle_irq(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
86 | { |
87 | unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS); | |
88 | ||
89 | if (status == 0) { | |
0cd61b68 | 90 | do_bad_IRQ(irq, desc); |
1da177e4 LT |
91 | return; |
92 | } | |
93 | ||
94 | do { | |
95 | irq = ffs(status) - 1; | |
96 | status &= ~(1 << irq); | |
97 | ||
98 | irq += IRQ_SIC_START; | |
99 | ||
d8aa0251 | 100 | generic_handle_irq(irq); |
1da177e4 LT |
101 | } while (status); |
102 | } | |
103 | ||
104 | #if 1 | |
105 | #define IRQ_MMCI0A IRQ_VICSOURCE22 | |
106 | #define IRQ_AACI IRQ_VICSOURCE24 | |
107 | #define IRQ_ETH IRQ_VICSOURCE25 | |
108 | #define PIC_MASK 0xFFD00000 | |
109 | #else | |
110 | #define IRQ_MMCI0A IRQ_SIC_MMCI0A | |
111 | #define IRQ_AACI IRQ_SIC_AACI | |
112 | #define IRQ_ETH IRQ_SIC_ETH | |
113 | #define PIC_MASK 0 | |
114 | #endif | |
115 | ||
116 | void __init versatile_init_irq(void) | |
117 | { | |
fa0fe48f | 118 | unsigned int i; |
1da177e4 | 119 | |
c07f87f2 | 120 | vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0); |
1da177e4 | 121 | |
56f1319e | 122 | set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq); |
1da177e4 LT |
123 | |
124 | /* Do second interrupt controller */ | |
125 | writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); | |
126 | ||
127 | for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { | |
128 | if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) { | |
129 | set_irq_chip(i, &sic_chip); | |
10dd5ce2 | 130 | set_irq_handler(i, handle_level_irq); |
1da177e4 LT |
131 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
132 | } | |
133 | } | |
134 | ||
135 | /* | |
136 | * Interrupts on secondary controller from 0 to 8 are routed to | |
137 | * source 31 on PIC. | |
138 | * Interrupts from 21 to 31 are routed directly to the VIC on | |
139 | * the corresponding number on primary controller. This is controlled | |
140 | * by setting PIC_ENABLEx. | |
141 | */ | |
142 | writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE); | |
143 | } | |
144 | ||
145 | static struct map_desc versatile_io_desc[] __initdata = { | |
1311521f DS |
146 | { |
147 | .virtual = IO_ADDRESS(VERSATILE_SYS_BASE), | |
148 | .pfn = __phys_to_pfn(VERSATILE_SYS_BASE), | |
149 | .length = SZ_4K, | |
150 | .type = MT_DEVICE | |
151 | }, { | |
152 | .virtual = IO_ADDRESS(VERSATILE_SIC_BASE), | |
153 | .pfn = __phys_to_pfn(VERSATILE_SIC_BASE), | |
154 | .length = SZ_4K, | |
155 | .type = MT_DEVICE | |
156 | }, { | |
157 | .virtual = IO_ADDRESS(VERSATILE_VIC_BASE), | |
158 | .pfn = __phys_to_pfn(VERSATILE_VIC_BASE), | |
159 | .length = SZ_4K, | |
160 | .type = MT_DEVICE | |
161 | }, { | |
162 | .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE), | |
163 | .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE), | |
164 | .length = SZ_4K * 9, | |
165 | .type = MT_DEVICE | |
166 | }, | |
1da177e4 | 167 | #ifdef CONFIG_MACH_VERSATILE_AB |
1311521f DS |
168 | { |
169 | .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE), | |
170 | .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE), | |
171 | .length = SZ_4K, | |
172 | .type = MT_DEVICE | |
173 | }, { | |
174 | .virtual = IO_ADDRESS(VERSATILE_IB2_BASE), | |
175 | .pfn = __phys_to_pfn(VERSATILE_IB2_BASE), | |
176 | .length = SZ_64M, | |
177 | .type = MT_DEVICE | |
178 | }, | |
1da177e4 LT |
179 | #endif |
180 | #ifdef CONFIG_DEBUG_LL | |
1311521f DS |
181 | { |
182 | .virtual = IO_ADDRESS(VERSATILE_UART0_BASE), | |
183 | .pfn = __phys_to_pfn(VERSATILE_UART0_BASE), | |
184 | .length = SZ_4K, | |
185 | .type = MT_DEVICE | |
186 | }, | |
1da177e4 | 187 | #endif |
c0da085a | 188 | #ifdef CONFIG_PCI |
1311521f DS |
189 | { |
190 | .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE), | |
191 | .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE), | |
192 | .length = SZ_4K, | |
193 | .type = MT_DEVICE | |
194 | }, { | |
399ad77b | 195 | .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE, |
1311521f DS |
196 | .pfn = __phys_to_pfn(VERSATILE_PCI_BASE), |
197 | .length = VERSATILE_PCI_BASE_SIZE, | |
198 | .type = MT_DEVICE | |
199 | }, { | |
399ad77b | 200 | .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE, |
1311521f DS |
201 | .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), |
202 | .length = VERSATILE_PCI_CFG_BASE_SIZE, | |
203 | .type = MT_DEVICE | |
204 | }, | |
c0da085a | 205 | #if 0 |
1311521f DS |
206 | { |
207 | .virtual = VERSATILE_PCI_VIRT_MEM_BASE0, | |
208 | .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0), | |
209 | .length = SZ_16M, | |
210 | .type = MT_DEVICE | |
211 | }, { | |
212 | .virtual = VERSATILE_PCI_VIRT_MEM_BASE1, | |
213 | .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1), | |
214 | .length = SZ_16M, | |
215 | .type = MT_DEVICE | |
216 | }, { | |
217 | .virtual = VERSATILE_PCI_VIRT_MEM_BASE2, | |
218 | .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2), | |
219 | .length = SZ_16M, | |
220 | .type = MT_DEVICE | |
221 | }, | |
c0da085a | 222 | #endif |
1da177e4 LT |
223 | #endif |
224 | }; | |
225 | ||
226 | void __init versatile_map_io(void) | |
227 | { | |
228 | iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc)); | |
229 | } | |
230 | ||
2ad4f86b | 231 | #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET) |
1da177e4 LT |
232 | |
233 | /* | |
234 | * This is the Versatile sched_clock implementation. This has | |
752bee17 NP |
235 | * a resolution of 41.7ns, and a maximum value of about 35583 days. |
236 | * | |
237 | * The return value is guaranteed to be monotonic in that range as | |
238 | * long as there is always less than 89 seconds between successive | |
239 | * calls to this function. | |
1da177e4 LT |
240 | */ |
241 | unsigned long long sched_clock(void) | |
242 | { | |
752bee17 | 243 | unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER)); |
1da177e4 | 244 | |
752bee17 NP |
245 | /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ |
246 | v *= 125<<1; | |
247 | do_div(v, 3<<1); | |
1da177e4 LT |
248 | |
249 | return v; | |
250 | } | |
251 | ||
252 | ||
2ad4f86b | 253 | #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) |
1da177e4 LT |
254 | |
255 | static int versatile_flash_init(void) | |
256 | { | |
257 | u32 val; | |
258 | ||
259 | val = __raw_readl(VERSATILE_FLASHCTRL); | |
260 | val &= ~VERSATILE_FLASHPROG_FLVPPEN; | |
261 | __raw_writel(val, VERSATILE_FLASHCTRL); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static void versatile_flash_exit(void) | |
267 | { | |
268 | u32 val; | |
269 | ||
270 | val = __raw_readl(VERSATILE_FLASHCTRL); | |
271 | val &= ~VERSATILE_FLASHPROG_FLVPPEN; | |
272 | __raw_writel(val, VERSATILE_FLASHCTRL); | |
273 | } | |
274 | ||
275 | static void versatile_flash_set_vpp(int on) | |
276 | { | |
277 | u32 val; | |
278 | ||
279 | val = __raw_readl(VERSATILE_FLASHCTRL); | |
280 | if (on) | |
281 | val |= VERSATILE_FLASHPROG_FLVPPEN; | |
282 | else | |
283 | val &= ~VERSATILE_FLASHPROG_FLVPPEN; | |
284 | __raw_writel(val, VERSATILE_FLASHCTRL); | |
285 | } | |
286 | ||
287 | static struct flash_platform_data versatile_flash_data = { | |
288 | .map_name = "cfi_probe", | |
289 | .width = 4, | |
290 | .init = versatile_flash_init, | |
291 | .exit = versatile_flash_exit, | |
292 | .set_vpp = versatile_flash_set_vpp, | |
293 | }; | |
294 | ||
295 | static struct resource versatile_flash_resource = { | |
296 | .start = VERSATILE_FLASH_BASE, | |
a0c5a645 | 297 | .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1, |
1da177e4 LT |
298 | .flags = IORESOURCE_MEM, |
299 | }; | |
300 | ||
301 | static struct platform_device versatile_flash_device = { | |
302 | .name = "armflash", | |
303 | .id = 0, | |
304 | .dev = { | |
305 | .platform_data = &versatile_flash_data, | |
306 | }, | |
307 | .num_resources = 1, | |
308 | .resource = &versatile_flash_resource, | |
309 | }; | |
310 | ||
311 | static struct resource smc91x_resources[] = { | |
312 | [0] = { | |
313 | .start = VERSATILE_ETH_BASE, | |
314 | .end = VERSATILE_ETH_BASE + SZ_64K - 1, | |
315 | .flags = IORESOURCE_MEM, | |
316 | }, | |
317 | [1] = { | |
318 | .start = IRQ_ETH, | |
319 | .end = IRQ_ETH, | |
320 | .flags = IORESOURCE_IRQ, | |
321 | }, | |
322 | }; | |
323 | ||
324 | static struct platform_device smc91x_device = { | |
325 | .name = "smc91x", | |
326 | .id = 0, | |
327 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
328 | .resource = smc91x_resources, | |
329 | }; | |
330 | ||
6b65cd74 RK |
331 | static struct resource versatile_i2c_resource = { |
332 | .start = VERSATILE_I2C_BASE, | |
333 | .end = VERSATILE_I2C_BASE + SZ_4K - 1, | |
334 | .flags = IORESOURCE_MEM, | |
335 | }; | |
336 | ||
337 | static struct platform_device versatile_i2c_device = { | |
338 | .name = "versatile-i2c", | |
533ad5e6 | 339 | .id = 0, |
6b65cd74 RK |
340 | .num_resources = 1, |
341 | .resource = &versatile_i2c_resource, | |
342 | }; | |
343 | ||
533ad5e6 CM |
344 | static struct i2c_board_info versatile_i2c_board_info[] = { |
345 | { | |
64e8be6e | 346 | I2C_BOARD_INFO("ds1338", 0xd0 >> 1), |
533ad5e6 CM |
347 | }, |
348 | }; | |
349 | ||
350 | static int __init versatile_i2c_init(void) | |
351 | { | |
352 | return i2c_register_board_info(0, versatile_i2c_board_info, | |
353 | ARRAY_SIZE(versatile_i2c_board_info)); | |
354 | } | |
355 | arch_initcall(versatile_i2c_init); | |
356 | ||
2ad4f86b | 357 | #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) |
1da177e4 LT |
358 | |
359 | unsigned int mmc_status(struct device *dev) | |
360 | { | |
361 | struct amba_device *adev = container_of(dev, struct amba_device, dev); | |
362 | u32 mask; | |
363 | ||
364 | if (adev->res.start == VERSATILE_MMCI0_BASE) | |
365 | mask = 1; | |
366 | else | |
367 | mask = 2; | |
368 | ||
369 | return readl(VERSATILE_SYSMCI) & mask; | |
370 | } | |
371 | ||
6ef297f8 | 372 | static struct mmci_platform_data mmc0_plat_data = { |
1da177e4 LT |
373 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
374 | .status = mmc_status, | |
7fb2bbf4 RK |
375 | .gpio_wp = -1, |
376 | .gpio_cd = -1, | |
1da177e4 LT |
377 | }; |
378 | ||
379 | /* | |
380 | * Clock handling | |
381 | */ | |
382 | static const struct icst307_params versatile_oscvco_params = { | |
383 | .ref = 24000, | |
384 | .vco_max = 200000, | |
385 | .vd_min = 4 + 8, | |
386 | .vd_max = 511 + 8, | |
387 | .rd_min = 1 + 2, | |
388 | .rd_max = 127 + 2, | |
389 | }; | |
390 | ||
391 | static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco) | |
392 | { | |
71a06da0 RK |
393 | void __iomem *sys = __io_address(VERSATILE_SYS_BASE); |
394 | void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET; | |
1da177e4 LT |
395 | u32 val; |
396 | ||
71a06da0 | 397 | val = readl(sys + clk->oscoff) & ~0x7ffff; |
1da177e4 LT |
398 | val |= vco.v | (vco.r << 9) | (vco.s << 16); |
399 | ||
400 | writel(0xa05f, sys_lock); | |
71a06da0 | 401 | writel(val, sys + clk->oscoff); |
1da177e4 LT |
402 | writel(0, sys_lock); |
403 | } | |
404 | ||
71a06da0 | 405 | static struct clk osc4_clk = { |
1da177e4 | 406 | .params = &versatile_oscvco_params, |
71a06da0 RK |
407 | .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET, |
408 | .setvco = versatile_oscvco_set, | |
409 | }; | |
410 | ||
411 | /* | |
412 | * These are fixed clocks. | |
413 | */ | |
414 | static struct clk ref24_clk = { | |
415 | .rate = 24000000, | |
416 | }; | |
417 | ||
982db663 | 418 | static struct clk_lookup lookups[] = { |
71a06da0 RK |
419 | { /* UART0 */ |
420 | .dev_id = "dev:f1", | |
421 | .clk = &ref24_clk, | |
422 | }, { /* UART1 */ | |
423 | .dev_id = "dev:f2", | |
424 | .clk = &ref24_clk, | |
425 | }, { /* UART2 */ | |
426 | .dev_id = "dev:f3", | |
427 | .clk = &ref24_clk, | |
428 | }, { /* UART3 */ | |
429 | .dev_id = "fpga:09", | |
430 | .clk = &ref24_clk, | |
431 | }, { /* KMI0 */ | |
432 | .dev_id = "fpga:06", | |
433 | .clk = &ref24_clk, | |
434 | }, { /* KMI1 */ | |
435 | .dev_id = "fpga:07", | |
436 | .clk = &ref24_clk, | |
437 | }, { /* MMC0 */ | |
438 | .dev_id = "fpga:05", | |
439 | .clk = &ref24_clk, | |
440 | }, { /* MMC1 */ | |
441 | .dev_id = "fpga:0b", | |
442 | .clk = &ref24_clk, | |
443 | }, { /* CLCD */ | |
444 | .dev_id = "dev:20", | |
445 | .clk = &osc4_clk, | |
446 | } | |
1da177e4 LT |
447 | }; |
448 | ||
449 | /* | |
450 | * CLCD support. | |
451 | */ | |
452 | #define SYS_CLCD_MODE_MASK (3 << 0) | |
453 | #define SYS_CLCD_MODE_888 (0 << 0) | |
454 | #define SYS_CLCD_MODE_5551 (1 << 0) | |
455 | #define SYS_CLCD_MODE_565_RLSB (2 << 0) | |
456 | #define SYS_CLCD_MODE_565_BLSB (3 << 0) | |
457 | #define SYS_CLCD_NLCDIOON (1 << 2) | |
458 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) | |
459 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) | |
460 | #define SYS_CLCD_ID_MASK (0x1f << 8) | |
461 | #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) | |
462 | #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) | |
463 | #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) | |
464 | #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) | |
465 | #define SYS_CLCD_ID_VGA (0x1f << 8) | |
466 | ||
467 | static struct clcd_panel vga = { | |
468 | .mode = { | |
469 | .name = "VGA", | |
470 | .refresh = 60, | |
471 | .xres = 640, | |
472 | .yres = 480, | |
473 | .pixclock = 39721, | |
474 | .left_margin = 40, | |
475 | .right_margin = 24, | |
476 | .upper_margin = 32, | |
477 | .lower_margin = 11, | |
478 | .hsync_len = 96, | |
479 | .vsync_len = 2, | |
480 | .sync = 0, | |
481 | .vmode = FB_VMODE_NONINTERLACED, | |
482 | }, | |
483 | .width = -1, | |
484 | .height = -1, | |
485 | .tim2 = TIM2_BCD | TIM2_IPC, | |
486 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | |
487 | .bpp = 16, | |
488 | }; | |
489 | ||
490 | static struct clcd_panel sanyo_3_8_in = { | |
491 | .mode = { | |
492 | .name = "Sanyo QVGA", | |
493 | .refresh = 116, | |
494 | .xres = 320, | |
495 | .yres = 240, | |
496 | .pixclock = 100000, | |
497 | .left_margin = 6, | |
498 | .right_margin = 6, | |
499 | .upper_margin = 5, | |
500 | .lower_margin = 5, | |
501 | .hsync_len = 6, | |
502 | .vsync_len = 6, | |
503 | .sync = 0, | |
504 | .vmode = FB_VMODE_NONINTERLACED, | |
505 | }, | |
506 | .width = -1, | |
507 | .height = -1, | |
508 | .tim2 = TIM2_BCD, | |
509 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | |
510 | .bpp = 16, | |
511 | }; | |
512 | ||
513 | static struct clcd_panel sanyo_2_5_in = { | |
514 | .mode = { | |
515 | .name = "Sanyo QVGA Portrait", | |
516 | .refresh = 116, | |
517 | .xres = 240, | |
518 | .yres = 320, | |
519 | .pixclock = 100000, | |
520 | .left_margin = 20, | |
521 | .right_margin = 10, | |
522 | .upper_margin = 2, | |
523 | .lower_margin = 2, | |
524 | .hsync_len = 10, | |
525 | .vsync_len = 2, | |
526 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
527 | .vmode = FB_VMODE_NONINTERLACED, | |
528 | }, | |
529 | .width = -1, | |
530 | .height = -1, | |
531 | .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, | |
532 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | |
533 | .bpp = 16, | |
534 | }; | |
535 | ||
536 | static struct clcd_panel epson_2_2_in = { | |
537 | .mode = { | |
538 | .name = "Epson QCIF", | |
539 | .refresh = 390, | |
540 | .xres = 176, | |
541 | .yres = 220, | |
542 | .pixclock = 62500, | |
543 | .left_margin = 3, | |
544 | .right_margin = 2, | |
545 | .upper_margin = 1, | |
546 | .lower_margin = 0, | |
547 | .hsync_len = 3, | |
548 | .vsync_len = 2, | |
549 | .sync = 0, | |
550 | .vmode = FB_VMODE_NONINTERLACED, | |
551 | }, | |
552 | .width = -1, | |
553 | .height = -1, | |
554 | .tim2 = TIM2_BCD | TIM2_IPC, | |
555 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | |
556 | .bpp = 16, | |
557 | }; | |
558 | ||
559 | /* | |
560 | * Detect which LCD panel is connected, and return the appropriate | |
561 | * clcd_panel structure. Note: we do not have any information on | |
562 | * the required timings for the 8.4in panel, so we presently assume | |
563 | * VGA timings. | |
564 | */ | |
565 | static struct clcd_panel *versatile_clcd_panel(void) | |
566 | { | |
2ad4f86b | 567 | void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; |
1da177e4 LT |
568 | struct clcd_panel *panel = &vga; |
569 | u32 val; | |
570 | ||
571 | val = readl(sys_clcd) & SYS_CLCD_ID_MASK; | |
572 | if (val == SYS_CLCD_ID_SANYO_3_8) | |
573 | panel = &sanyo_3_8_in; | |
574 | else if (val == SYS_CLCD_ID_SANYO_2_5) | |
575 | panel = &sanyo_2_5_in; | |
576 | else if (val == SYS_CLCD_ID_EPSON_2_2) | |
577 | panel = &epson_2_2_in; | |
578 | else if (val == SYS_CLCD_ID_VGA) | |
579 | panel = &vga; | |
580 | else { | |
581 | printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", | |
582 | val); | |
583 | panel = &vga; | |
584 | } | |
585 | ||
586 | return panel; | |
587 | } | |
588 | ||
589 | /* | |
590 | * Disable all display connectors on the interface module. | |
591 | */ | |
592 | static void versatile_clcd_disable(struct clcd_fb *fb) | |
593 | { | |
2ad4f86b | 594 | void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; |
1da177e4 LT |
595 | u32 val; |
596 | ||
597 | val = readl(sys_clcd); | |
598 | val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | |
599 | writel(val, sys_clcd); | |
600 | ||
601 | #ifdef CONFIG_MACH_VERSATILE_AB | |
602 | /* | |
603 | * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off | |
604 | */ | |
dc5bc8f1 | 605 | if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) { |
2ad4f86b | 606 | void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); |
1da177e4 LT |
607 | unsigned long ctrl; |
608 | ||
609 | ctrl = readl(versatile_ib2_ctrl); | |
610 | ctrl &= ~0x01; | |
611 | writel(ctrl, versatile_ib2_ctrl); | |
612 | } | |
613 | #endif | |
614 | } | |
615 | ||
616 | /* | |
617 | * Enable the relevant connector on the interface module. | |
618 | */ | |
619 | static void versatile_clcd_enable(struct clcd_fb *fb) | |
620 | { | |
2ad4f86b | 621 | void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; |
1da177e4 LT |
622 | u32 val; |
623 | ||
624 | val = readl(sys_clcd); | |
625 | val &= ~SYS_CLCD_MODE_MASK; | |
626 | ||
627 | switch (fb->fb.var.green.length) { | |
628 | case 5: | |
629 | val |= SYS_CLCD_MODE_5551; | |
630 | break; | |
631 | case 6: | |
90ef713b | 632 | val |= SYS_CLCD_MODE_565_RLSB; |
1da177e4 LT |
633 | break; |
634 | case 8: | |
635 | val |= SYS_CLCD_MODE_888; | |
636 | break; | |
637 | } | |
638 | ||
639 | /* | |
640 | * Set the MUX | |
641 | */ | |
642 | writel(val, sys_clcd); | |
643 | ||
644 | /* | |
645 | * And now enable the PSUs | |
646 | */ | |
647 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | |
648 | writel(val, sys_clcd); | |
649 | ||
650 | #ifdef CONFIG_MACH_VERSATILE_AB | |
651 | /* | |
652 | * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on | |
653 | */ | |
dc5bc8f1 | 654 | if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) { |
2ad4f86b | 655 | void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); |
1da177e4 LT |
656 | unsigned long ctrl; |
657 | ||
658 | ctrl = readl(versatile_ib2_ctrl); | |
659 | ctrl |= 0x01; | |
660 | writel(ctrl, versatile_ib2_ctrl); | |
661 | } | |
662 | #endif | |
663 | } | |
664 | ||
665 | static unsigned long framesize = SZ_1M; | |
666 | ||
667 | static int versatile_clcd_setup(struct clcd_fb *fb) | |
668 | { | |
669 | dma_addr_t dma; | |
670 | ||
671 | fb->panel = versatile_clcd_panel(); | |
672 | ||
673 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | |
674 | &dma, GFP_KERNEL); | |
675 | if (!fb->fb.screen_base) { | |
676 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); | |
677 | return -ENOMEM; | |
678 | } | |
679 | ||
680 | fb->fb.fix.smem_start = dma; | |
681 | fb->fb.fix.smem_len = framesize; | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | |
687 | { | |
688 | return dma_mmap_writecombine(&fb->dev->dev, vma, | |
689 | fb->fb.screen_base, | |
690 | fb->fb.fix.smem_start, | |
691 | fb->fb.fix.smem_len); | |
692 | } | |
693 | ||
694 | static void versatile_clcd_remove(struct clcd_fb *fb) | |
695 | { | |
696 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | |
697 | fb->fb.screen_base, fb->fb.fix.smem_start); | |
698 | } | |
699 | ||
700 | static struct clcd_board clcd_plat_data = { | |
701 | .name = "Versatile", | |
702 | .check = clcdfb_check, | |
703 | .decode = clcdfb_decode, | |
704 | .disable = versatile_clcd_disable, | |
705 | .enable = versatile_clcd_enable, | |
706 | .setup = versatile_clcd_setup, | |
707 | .mmap = versatile_clcd_mmap, | |
708 | .remove = versatile_clcd_remove, | |
709 | }; | |
710 | ||
bbeddc43 RK |
711 | static struct pl061_platform_data gpio0_plat_data = { |
712 | .gpio_base = 0, | |
713 | .irq_base = IRQ_GPIO0_START, | |
714 | }; | |
715 | ||
716 | static struct pl061_platform_data gpio1_plat_data = { | |
717 | .gpio_base = 8, | |
718 | .irq_base = IRQ_GPIO1_START, | |
719 | }; | |
720 | ||
1da177e4 LT |
721 | #define AACI_IRQ { IRQ_AACI, NO_IRQ } |
722 | #define AACI_DMA { 0x80, 0x81 } | |
723 | #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } | |
724 | #define MMCI0_DMA { 0x84, 0 } | |
725 | #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ } | |
726 | #define KMI0_DMA { 0, 0 } | |
727 | #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ } | |
728 | #define KMI1_DMA { 0, 0 } | |
729 | ||
730 | /* | |
731 | * These devices are connected directly to the multi-layer AHB switch | |
732 | */ | |
733 | #define SMC_IRQ { NO_IRQ, NO_IRQ } | |
734 | #define SMC_DMA { 0, 0 } | |
735 | #define MPMC_IRQ { NO_IRQ, NO_IRQ } | |
736 | #define MPMC_DMA { 0, 0 } | |
737 | #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } | |
738 | #define CLCD_DMA { 0, 0 } | |
739 | #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } | |
740 | #define DMAC_DMA { 0, 0 } | |
741 | ||
742 | /* | |
743 | * These devices are connected via the core APB bridge | |
744 | */ | |
745 | #define SCTL_IRQ { NO_IRQ, NO_IRQ } | |
746 | #define SCTL_DMA { 0, 0 } | |
747 | #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } | |
748 | #define WATCHDOG_DMA { 0, 0 } | |
749 | #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } | |
750 | #define GPIO0_DMA { 0, 0 } | |
751 | #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } | |
752 | #define GPIO1_DMA { 0, 0 } | |
753 | #define RTC_IRQ { IRQ_RTCINT, NO_IRQ } | |
754 | #define RTC_DMA { 0, 0 } | |
755 | ||
756 | /* | |
757 | * These devices are connected via the DMA APB bridge | |
758 | */ | |
759 | #define SCI_IRQ { IRQ_SCIINT, NO_IRQ } | |
760 | #define SCI_DMA { 7, 6 } | |
761 | #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } | |
762 | #define UART0_DMA { 15, 14 } | |
763 | #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } | |
764 | #define UART1_DMA { 13, 12 } | |
765 | #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } | |
766 | #define UART2_DMA { 11, 10 } | |
767 | #define SSP_IRQ { IRQ_SSPINT, NO_IRQ } | |
768 | #define SSP_DMA { 9, 8 } | |
769 | ||
770 | /* FPGA Primecells */ | |
771 | AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); | |
772 | AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data); | |
773 | AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); | |
774 | AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); | |
775 | ||
776 | /* DevChip Primecells */ | |
777 | AMBA_DEVICE(smc, "dev:00", SMC, NULL); | |
778 | AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL); | |
779 | AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); | |
780 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); | |
781 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | |
782 | AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); | |
bbeddc43 RK |
783 | AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data); |
784 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); | |
1da177e4 LT |
785 | AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); |
786 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | |
787 | AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); | |
788 | AMBA_DEVICE(uart1, "dev:f2", UART1, NULL); | |
789 | AMBA_DEVICE(uart2, "dev:f3", UART2, NULL); | |
790 | AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL); | |
791 | ||
792 | static struct amba_device *amba_devs[] __initdata = { | |
793 | &dmac_device, | |
794 | &uart0_device, | |
795 | &uart1_device, | |
796 | &uart2_device, | |
797 | &smc_device, | |
798 | &mpmc_device, | |
799 | &clcd_device, | |
800 | &sctl_device, | |
801 | &wdog_device, | |
802 | &gpio0_device, | |
803 | &gpio1_device, | |
804 | &rtc_device, | |
805 | &sci0_device, | |
806 | &ssp0_device, | |
807 | &aaci_device, | |
808 | &mmc0_device, | |
809 | &kmi0_device, | |
810 | &kmi1_device, | |
811 | }; | |
812 | ||
813 | #ifdef CONFIG_LEDS | |
2ad4f86b | 814 | #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET) |
1da177e4 LT |
815 | |
816 | static void versatile_leds_event(led_event_t ledevt) | |
817 | { | |
818 | unsigned long flags; | |
819 | u32 val; | |
820 | ||
821 | local_irq_save(flags); | |
822 | val = readl(VA_LEDS_BASE); | |
823 | ||
824 | switch (ledevt) { | |
825 | case led_idle_start: | |
826 | val = val & ~VERSATILE_SYS_LED0; | |
827 | break; | |
828 | ||
829 | case led_idle_end: | |
830 | val = val | VERSATILE_SYS_LED0; | |
831 | break; | |
832 | ||
833 | case led_timer: | |
834 | val = val ^ VERSATILE_SYS_LED1; | |
835 | break; | |
836 | ||
837 | case led_halted: | |
838 | val = 0; | |
839 | break; | |
840 | ||
841 | default: | |
842 | break; | |
843 | } | |
844 | ||
845 | writel(val, VA_LEDS_BASE); | |
846 | local_irq_restore(flags); | |
847 | } | |
848 | #endif /* CONFIG_LEDS */ | |
849 | ||
850 | void __init versatile_init(void) | |
851 | { | |
852 | int i; | |
853 | ||
0a0300dc | 854 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
1da177e4 LT |
855 | |
856 | platform_device_register(&versatile_flash_device); | |
6b65cd74 | 857 | platform_device_register(&versatile_i2c_device); |
1da177e4 LT |
858 | platform_device_register(&smc91x_device); |
859 | ||
860 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | |
861 | struct amba_device *d = amba_devs[i]; | |
862 | amba_device_register(d, &iomem_resource); | |
863 | } | |
864 | ||
865 | #ifdef CONFIG_LEDS | |
866 | leds_event = versatile_leds_event; | |
867 | #endif | |
868 | } | |
869 | ||
870 | /* | |
871 | * Where is the timer (VA)? | |
872 | */ | |
2ad4f86b AV |
873 | #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE) |
874 | #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20) | |
875 | #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE) | |
876 | #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20) | |
877 | #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE) | |
1da177e4 LT |
878 | |
879 | /* | |
880 | * How long is the timer interval? | |
881 | */ | |
882 | #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) | |
883 | #if TIMER_INTERVAL >= 0x100000 | |
b720f732 RK |
884 | #define TIMER_RELOAD (TIMER_INTERVAL >> 8) |
885 | #define TIMER_DIVISOR (TIMER_CTRL_DIV256) | |
1da177e4 LT |
886 | #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) |
887 | #elif TIMER_INTERVAL >= 0x10000 | |
888 | #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ | |
b720f732 | 889 | #define TIMER_DIVISOR (TIMER_CTRL_DIV16) |
1da177e4 LT |
890 | #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) |
891 | #else | |
892 | #define TIMER_RELOAD (TIMER_INTERVAL) | |
b720f732 | 893 | #define TIMER_DIVISOR (TIMER_CTRL_DIV1) |
1da177e4 LT |
894 | #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) |
895 | #endif | |
896 | ||
89df1272 KH |
897 | static void timer_set_mode(enum clock_event_mode mode, |
898 | struct clock_event_device *clk) | |
899 | { | |
900 | unsigned long ctrl; | |
901 | ||
902 | switch(mode) { | |
903 | case CLOCK_EVT_MODE_PERIODIC: | |
904 | writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); | |
905 | ||
906 | ctrl = TIMER_CTRL_PERIODIC; | |
907 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; | |
908 | break; | |
909 | case CLOCK_EVT_MODE_ONESHOT: | |
910 | /* period set, and timer enabled in 'next_event' hook */ | |
911 | ctrl = TIMER_CTRL_ONESHOT; | |
912 | ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE; | |
913 | break; | |
914 | case CLOCK_EVT_MODE_UNUSED: | |
915 | case CLOCK_EVT_MODE_SHUTDOWN: | |
916 | default: | |
917 | ctrl = 0; | |
918 | } | |
919 | ||
920 | writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); | |
921 | } | |
922 | ||
923 | static int timer_set_next_event(unsigned long evt, | |
924 | struct clock_event_device *unused) | |
925 | { | |
926 | unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); | |
927 | ||
928 | writel(evt, TIMER0_VA_BASE + TIMER_LOAD); | |
929 | writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | static struct clock_event_device timer0_clockevent = { | |
935 | .name = "timer0", | |
936 | .shift = 32, | |
937 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
938 | .set_mode = timer_set_mode, | |
939 | .set_next_event = timer_set_next_event, | |
940 | }; | |
941 | ||
1da177e4 LT |
942 | /* |
943 | * IRQ handler for the timer | |
944 | */ | |
0cd61b68 | 945 | static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id) |
1da177e4 | 946 | { |
89df1272 | 947 | struct clock_event_device *evt = &timer0_clockevent; |
1da177e4 | 948 | |
b720f732 | 949 | writel(1, TIMER0_VA_BASE + TIMER_INTCLR); |
1da177e4 | 950 | |
89df1272 | 951 | evt->event_handler(evt); |
1da177e4 LT |
952 | |
953 | return IRQ_HANDLED; | |
954 | } | |
955 | ||
956 | static struct irqaction versatile_timer_irq = { | |
957 | .name = "Versatile Timer Tick", | |
b30fabad | 958 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
09b8b5f8 | 959 | .handler = versatile_timer_interrupt, |
1da177e4 LT |
960 | }; |
961 | ||
8e19608e | 962 | static cycle_t versatile_get_cycles(struct clocksource *cs) |
b49c87c2 KH |
963 | { |
964 | return ~readl(TIMER3_VA_BASE + TIMER_VALUE); | |
965 | } | |
966 | ||
967 | static struct clocksource clocksource_versatile = { | |
968 | .name = "timer3", | |
969 | .rating = 200, | |
970 | .read = versatile_get_cycles, | |
971 | .mask = CLOCKSOURCE_MASK(32), | |
972 | .shift = 20, | |
973 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
974 | }; | |
975 | ||
976 | static int __init versatile_clocksource_init(void) | |
977 | { | |
978 | /* setup timer3 as free-running clocksource */ | |
979 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | |
980 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); | |
981 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); | |
982 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | |
983 | TIMER3_VA_BASE + TIMER_CTRL); | |
984 | ||
985 | clocksource_versatile.mult = | |
986 | clocksource_khz2mult(1000, clocksource_versatile.shift); | |
987 | clocksource_register(&clocksource_versatile); | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
1da177e4 LT |
992 | /* |
993 | * Set up timer interrupt, and return the current time in seconds. | |
994 | */ | |
995 | static void __init versatile_timer_init(void) | |
996 | { | |
b720f732 | 997 | u32 val; |
1da177e4 LT |
998 | |
999 | /* | |
1000 | * set clock frequency: | |
1001 | * VERSATILE_REFCLK is 32KHz | |
1002 | * VERSATILE_TIMCLK is 1MHz | |
1003 | */ | |
2ad4f86b | 1004 | val = readl(__io_address(VERSATILE_SCTL_BASE)); |
b720f732 RK |
1005 | writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | |
1006 | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | | |
1007 | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | | |
1008 | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, | |
2ad4f86b | 1009 | __io_address(VERSATILE_SCTL_BASE)); |
1da177e4 LT |
1010 | |
1011 | /* | |
1012 | * Initialise to a known state (all timers off) | |
1013 | */ | |
b720f732 RK |
1014 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); |
1015 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | |
1016 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | |
1017 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | |
1018 | ||
1da177e4 LT |
1019 | /* |
1020 | * Make irqs happen for the system timer | |
1021 | */ | |
1022 | setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq); | |
b49c87c2 KH |
1023 | |
1024 | versatile_clocksource_init(); | |
89df1272 KH |
1025 | |
1026 | timer0_clockevent.mult = | |
1027 | div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); | |
1028 | timer0_clockevent.max_delta_ns = | |
1029 | clockevent_delta2ns(0xffffffff, &timer0_clockevent); | |
1030 | timer0_clockevent.min_delta_ns = | |
1031 | clockevent_delta2ns(0xf, &timer0_clockevent); | |
1032 | ||
320ab2b0 | 1033 | timer0_clockevent.cpumask = cpumask_of(0); |
89df1272 | 1034 | clockevents_register_device(&timer0_clockevent); |
1da177e4 LT |
1035 | } |
1036 | ||
1037 | struct sys_timer versatile_timer = { | |
1038 | .init = versatile_timer_init, | |
1da177e4 | 1039 | }; |
b49c87c2 | 1040 |