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Create platform_device.h to contain all the platform device details.
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/config.h>
22#include <linux/init.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
d052d1be 25#include <linux/platform_device.h>
1da177e4
LT		 26#include <linux/sysdev.h>
27#include <linux/interrupt.h>
28
29#include <asm/system.h>
30#include <asm/hardware.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/leds.h>
1da177e4
LT		 34#include <asm/hardware/amba.h>
35#include <asm/hardware/amba_clcd.h>
b720f732 36#include <asm/hardware/arm_timer.h>
1da177e4
LT		 37#include <asm/hardware/icst307.h>
38
39#include <asm/mach/arch.h>
40#include <asm/mach/flash.h>
41#include <asm/mach/irq.h>
42#include <asm/mach/time.h>
43#include <asm/mach/map.h>
44#include <asm/mach/mmc.h>
45
46#include "core.h"
47#include "clock.h"
48
49/*
50 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
51 * is the (PA >> 12).
52 *
53 * Setup a VA for the Versatile Vectored Interrupt Controller.
54 */
2ad4f86b
AV		 55#define __io_address(n) __io(IO_ADDRESS(n))
56#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
57#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4
LT		 58
59static void vic_mask_irq(unsigned int irq)
60{
61 irq -= IRQ_VIC_START;
62 writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
63}
64
65static void vic_unmask_irq(unsigned int irq)
66{
67 irq -= IRQ_VIC_START;
68 writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
69}
70
71static struct irqchip vic_chip = {
72 .ack = vic_mask_irq,
73 .mask = vic_mask_irq,
74 .unmask = vic_unmask_irq,
75};
76
77static void sic_mask_irq(unsigned int irq)
78{
79 irq -= IRQ_SIC_START;
80 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
81}
82
83static void sic_unmask_irq(unsigned int irq)
84{
85 irq -= IRQ_SIC_START;
86 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
87}
88
89static struct irqchip sic_chip = {
90 .ack = sic_mask_irq,
91 .mask = sic_mask_irq,
92 .unmask = sic_unmask_irq,
93};
94
95static void
96sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
97{
98 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
99
100 if (status == 0) {
101 do_bad_IRQ(irq, desc, regs);
102 return;
103 }
104
105 do {
106 irq = ffs(status) - 1;
107 status &= ~(1 << irq);
108
109 irq += IRQ_SIC_START;
110
111 desc = irq_desc + irq;
664399e1 112 desc_handle_irq(irq, desc, regs);
1da177e4
LT		 113 } while (status);
114}
115
116#if 1
117#define IRQ_MMCI0A IRQ_VICSOURCE22
118#define IRQ_AACI IRQ_VICSOURCE24
119#define IRQ_ETH IRQ_VICSOURCE25
120#define PIC_MASK 0xFFD00000
121#else
122#define IRQ_MMCI0A IRQ_SIC_MMCI0A
123#define IRQ_AACI IRQ_SIC_AACI
124#define IRQ_ETH IRQ_SIC_ETH
125#define PIC_MASK 0
126#endif
127
128void __init versatile_init_irq(void)
129{
130 unsigned int i, value;
131
132 /* Disable all interrupts initially. */
133
134 writel(0, VA_VIC_BASE + VIC_INT_SELECT);
135 writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
136 writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
137 writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
138 writel(0, VA_VIC_BASE + VIC_ITCR);
139 writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
140
141 /*
142 * Make sure we clear all existing interrupts
143 */
144 writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
145 for (i = 0; i < 19; i++) {
146 value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
147 writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
148 }
149
150 for (i = 0; i < 16; i++) {
151 value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
152 writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
153 }
154
155 writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
156
157 for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
158 if (i != IRQ_VICSOURCE31) {
159 set_irq_chip(i, &vic_chip);
160 set_irq_handler(i, do_level_IRQ);
161 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
162 }
163 }
164
165 set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
166 vic_unmask_irq(IRQ_VICSOURCE31);
167
168 /* Do second interrupt controller */
169 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
170
171 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
172 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
173 set_irq_chip(i, &sic_chip);
174 set_irq_handler(i, do_level_IRQ);
175 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
176 }
177 }
178
179 /*
180 * Interrupts on secondary controller from 0 to 8 are routed to
181 * source 31 on PIC.
182 * Interrupts from 21 to 31 are routed directly to the VIC on
183 * the corresponding number on primary controller. This is controlled
184 * by setting PIC_ENABLEx.
185 */
186 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
187}
188
189static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 190 {
191 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
192 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
193 .length = SZ_4K,
194 .type = MT_DEVICE
195 }, {
196 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
197 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
198 .length = SZ_4K,
199 .type = MT_DEVICE
200 }, {
201 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
202 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
203 .length = SZ_4K,
204 .type = MT_DEVICE
205 }, {
206 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
207 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
208 .length = SZ_4K * 9,
209 .type = MT_DEVICE
210 },
1da177e4 211#ifdef CONFIG_MACH_VERSATILE_AB
1311521f
DS		 212 {
213 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
214 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
215 .length = SZ_4K,
216 .type = MT_DEVICE
217 }, {
218 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
219 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
220 .length = SZ_64M,
221 .type = MT_DEVICE
222 },
1da177e4
LT		 223#endif
224#ifdef CONFIG_DEBUG_LL
1311521f
DS		 225 {
226 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
227 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
228 .length = SZ_4K,
229 .type = MT_DEVICE
230 },
1da177e4 231#endif
c0da085a 232#ifdef CONFIG_PCI
1311521f
DS		 233 {
234 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
235 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
236 .length = SZ_4K,
237 .type = MT_DEVICE
238 }, {
239 .virtual = VERSATILE_PCI_VIRT_BASE,
240 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
241 .length = VERSATILE_PCI_BASE_SIZE,
242 .type = MT_DEVICE
243 }, {
244 .virtual = VERSATILE_PCI_CFG_VIRT_BASE,
245 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
246 .length = VERSATILE_PCI_CFG_BASE_SIZE,
247 .type = MT_DEVICE
248 },
c0da085a 249#if 0
1311521f
DS		 250 {
251 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
252 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
253 .length = SZ_16M,
254 .type = MT_DEVICE
255 }, {
256 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
257 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
258 .length = SZ_16M,
259 .type = MT_DEVICE
260 }, {
261 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
262 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
263 .length = SZ_16M,
264 .type = MT_DEVICE
265 },
c0da085a 266#endif
1da177e4
LT		 267#endif
268};
269
270void __init versatile_map_io(void)
271{
272 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
273}
274
2ad4f86b 275#define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
1da177e4
LT		 276
277/*
278 * This is the Versatile sched_clock implementation. This has
279 * a resolution of 41.7ns, and a maximum value of about 179s.
280 */
281unsigned long long sched_clock(void)
282{
283 unsigned long long v;
284
285 v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
286 do_div(v, 3);
287
288 return v;
289}
290
291
2ad4f86b 292#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4
LT		 293
294static int versatile_flash_init(void)
295{
296 u32 val;
297
298 val = __raw_readl(VERSATILE_FLASHCTRL);
299 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
300 __raw_writel(val, VERSATILE_FLASHCTRL);
301
302 return 0;
303}
304
305static void versatile_flash_exit(void)
306{
307 u32 val;
308
309 val = __raw_readl(VERSATILE_FLASHCTRL);
310 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
311 __raw_writel(val, VERSATILE_FLASHCTRL);
312}
313
314static void versatile_flash_set_vpp(int on)
315{
316 u32 val;
317
318 val = __raw_readl(VERSATILE_FLASHCTRL);
319 if (on)
320 val |= VERSATILE_FLASHPROG_FLVPPEN;
321 else
322 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
323 __raw_writel(val, VERSATILE_FLASHCTRL);
324}
325
326static struct flash_platform_data versatile_flash_data = {
327 .map_name = "cfi_probe",
328 .width = 4,
329 .init = versatile_flash_init,
330 .exit = versatile_flash_exit,
331 .set_vpp = versatile_flash_set_vpp,
332};
333
334static struct resource versatile_flash_resource = {
335 .start = VERSATILE_FLASH_BASE,
336 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
337 .flags = IORESOURCE_MEM,
338};
339
340static struct platform_device versatile_flash_device = {
341 .name = "armflash",
342 .id = 0,
343 .dev = {
344 .platform_data = &versatile_flash_data,
345 },
346 .num_resources = 1,
347 .resource = &versatile_flash_resource,
348};
349
350static struct resource smc91x_resources[] = {
351 [0] = {
352 .start = VERSATILE_ETH_BASE,
353 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
354 .flags = IORESOURCE_MEM,
355 },
356 [1] = {
357 .start = IRQ_ETH,
358 .end = IRQ_ETH,
359 .flags = IORESOURCE_IRQ,
360 },
361};
362
363static struct platform_device smc91x_device = {
364 .name = "smc91x",
365 .id = 0,
366 .num_resources = ARRAY_SIZE(smc91x_resources),
367 .resource = smc91x_resources,
368};
369
2ad4f86b 370#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 371
372unsigned int mmc_status(struct device *dev)
373{
374 struct amba_device *adev = container_of(dev, struct amba_device, dev);
375 u32 mask;
376
377 if (adev->res.start == VERSATILE_MMCI0_BASE)
378 mask = 1;
379 else
380 mask = 2;
381
382 return readl(VERSATILE_SYSMCI) & mask;
383}
384
385static struct mmc_platform_data mmc0_plat_data = {
386 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
387 .status = mmc_status,
388};
389
390/*
391 * Clock handling
392 */
393static const struct icst307_params versatile_oscvco_params = {
394 .ref = 24000,
395 .vco_max = 200000,
396 .vd_min = 4 + 8,
397 .vd_max = 511 + 8,
398 .rd_min = 1 + 2,
399 .rd_max = 127 + 2,
400};
401
402static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
403{
2ad4f86b 404 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
1da177e4 405#if defined(CONFIG_ARCH_VERSATILE_PB)
2ad4f86b 406 void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
1da177e4 407#elif defined(CONFIG_MACH_VERSATILE_AB)
2ad4f86b 408 void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
1da177e4
LT		 409#endif
410 u32 val;
411
412 val = readl(sys_osc) & ~0x7ffff;
413 val |= vco.v | (vco.r << 9) | (vco.s << 16);
414
415 writel(0xa05f, sys_lock);
416 writel(val, sys_osc);
417 writel(0, sys_lock);
418}
419
420static struct clk versatile_clcd_clk = {
421 .name = "CLCDCLK",
422 .params = &versatile_oscvco_params,
423 .setvco = versatile_oscvco_set,
424};
425
426/*
427 * CLCD support.
428 */
429#define SYS_CLCD_MODE_MASK (3 << 0)
430#define SYS_CLCD_MODE_888 (0 << 0)
431#define SYS_CLCD_MODE_5551 (1 << 0)
432#define SYS_CLCD_MODE_565_RLSB (2 << 0)
433#define SYS_CLCD_MODE_565_BLSB (3 << 0)
434#define SYS_CLCD_NLCDIOON (1 << 2)
435#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
436#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
437#define SYS_CLCD_ID_MASK (0x1f << 8)
438#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
439#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
440#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
441#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
442#define SYS_CLCD_ID_VGA (0x1f << 8)
443
444static struct clcd_panel vga = {
445 .mode = {
446 .name = "VGA",
447 .refresh = 60,
448 .xres = 640,
449 .yres = 480,
450 .pixclock = 39721,
451 .left_margin = 40,
452 .right_margin = 24,
453 .upper_margin = 32,
454 .lower_margin = 11,
455 .hsync_len = 96,
456 .vsync_len = 2,
457 .sync = 0,
458 .vmode = FB_VMODE_NONINTERLACED,
459 },
460 .width = -1,
461 .height = -1,
462 .tim2 = TIM2_BCD | TIM2_IPC,
463 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
464 .bpp = 16,
465};
466
467static struct clcd_panel sanyo_3_8_in = {
468 .mode = {
469 .name = "Sanyo QVGA",
470 .refresh = 116,
471 .xres = 320,
472 .yres = 240,
473 .pixclock = 100000,
474 .left_margin = 6,
475 .right_margin = 6,
476 .upper_margin = 5,
477 .lower_margin = 5,
478 .hsync_len = 6,
479 .vsync_len = 6,
480 .sync = 0,
481 .vmode = FB_VMODE_NONINTERLACED,
482 },
483 .width = -1,
484 .height = -1,
485 .tim2 = TIM2_BCD,
486 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
487 .bpp = 16,
488};
489
490static struct clcd_panel sanyo_2_5_in = {
491 .mode = {
492 .name = "Sanyo QVGA Portrait",
493 .refresh = 116,
494 .xres = 240,
495 .yres = 320,
496 .pixclock = 100000,
497 .left_margin = 20,
498 .right_margin = 10,
499 .upper_margin = 2,
500 .lower_margin = 2,
501 .hsync_len = 10,
502 .vsync_len = 2,
503 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
504 .vmode = FB_VMODE_NONINTERLACED,
505 },
506 .width = -1,
507 .height = -1,
508 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
509 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
510 .bpp = 16,
511};
512
513static struct clcd_panel epson_2_2_in = {
514 .mode = {
515 .name = "Epson QCIF",
516 .refresh = 390,
517 .xres = 176,
518 .yres = 220,
519 .pixclock = 62500,
520 .left_margin = 3,
521 .right_margin = 2,
522 .upper_margin = 1,
523 .lower_margin = 0,
524 .hsync_len = 3,
525 .vsync_len = 2,
526 .sync = 0,
527 .vmode = FB_VMODE_NONINTERLACED,
528 },
529 .width = -1,
530 .height = -1,
531 .tim2 = TIM2_BCD | TIM2_IPC,
532 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
533 .bpp = 16,
534};
535
536/*
537 * Detect which LCD panel is connected, and return the appropriate
538 * clcd_panel structure. Note: we do not have any information on
539 * the required timings for the 8.4in panel, so we presently assume
540 * VGA timings.
541 */
542static struct clcd_panel *versatile_clcd_panel(void)
543{
2ad4f86b 544 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 545 struct clcd_panel *panel = &vga;
546 u32 val;
547
548 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
549 if (val == SYS_CLCD_ID_SANYO_3_8)
550 panel = &sanyo_3_8_in;
551 else if (val == SYS_CLCD_ID_SANYO_2_5)
552 panel = &sanyo_2_5_in;
553 else if (val == SYS_CLCD_ID_EPSON_2_2)
554 panel = &epson_2_2_in;
555 else if (val == SYS_CLCD_ID_VGA)
556 panel = &vga;
557 else {
558 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
559 val);
560 panel = &vga;
561 }
562
563 return panel;
564}
565
566/*
567 * Disable all display connectors on the interface module.
568 */
569static void versatile_clcd_disable(struct clcd_fb *fb)
570{
2ad4f86b 571 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 572 u32 val;
573
574 val = readl(sys_clcd);
575 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
576 writel(val, sys_clcd);
577
578#ifdef CONFIG_MACH_VERSATILE_AB
579 /*
580 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
581 */
582 if (fb->panel == &sanyo_2_5_in) {
2ad4f86b 583 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 584 unsigned long ctrl;
585
586 ctrl = readl(versatile_ib2_ctrl);
587 ctrl &= ~0x01;
588 writel(ctrl, versatile_ib2_ctrl);
589 }
590#endif
591}
592
593/*
594 * Enable the relevant connector on the interface module.
595 */
596static void versatile_clcd_enable(struct clcd_fb *fb)
597{
2ad4f86b 598 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 599 u32 val;
600
601 val = readl(sys_clcd);
602 val &= ~SYS_CLCD_MODE_MASK;
603
604 switch (fb->fb.var.green.length) {
605 case 5:
606 val |= SYS_CLCD_MODE_5551;
607 break;
608 case 6:
90ef713b 609 val |= SYS_CLCD_MODE_565_RLSB;
1da177e4
LT		 610 break;
611 case 8:
612 val |= SYS_CLCD_MODE_888;
613 break;
614 }
615
616 /*
617 * Set the MUX
618 */
619 writel(val, sys_clcd);
620
621 /*
622 * And now enable the PSUs
623 */
624 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
625 writel(val, sys_clcd);
626
627#ifdef CONFIG_MACH_VERSATILE_AB
628 /*
629 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
630 */
631 if (fb->panel == &sanyo_2_5_in) {
2ad4f86b 632 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 633 unsigned long ctrl;
634
635 ctrl = readl(versatile_ib2_ctrl);
636 ctrl |= 0x01;
637 writel(ctrl, versatile_ib2_ctrl);
638 }
639#endif
640}
641
642static unsigned long framesize = SZ_1M;
643
644static int versatile_clcd_setup(struct clcd_fb *fb)
645{
646 dma_addr_t dma;
647
648 fb->panel = versatile_clcd_panel();
649
650 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
651 &dma, GFP_KERNEL);
652 if (!fb->fb.screen_base) {
653 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
654 return -ENOMEM;
655 }
656
657 fb->fb.fix.smem_start = dma;
658 fb->fb.fix.smem_len = framesize;
659
660 return 0;
661}
662
663static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
664{
665 return dma_mmap_writecombine(&fb->dev->dev, vma,
666 fb->fb.screen_base,
667 fb->fb.fix.smem_start,
668 fb->fb.fix.smem_len);
669}
670
671static void versatile_clcd_remove(struct clcd_fb *fb)
672{
673 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
674 fb->fb.screen_base, fb->fb.fix.smem_start);
675}
676
677static struct clcd_board clcd_plat_data = {
678 .name = "Versatile",
679 .check = clcdfb_check,
680 .decode = clcdfb_decode,
681 .disable = versatile_clcd_disable,
682 .enable = versatile_clcd_enable,
683 .setup = versatile_clcd_setup,
684 .mmap = versatile_clcd_mmap,
685 .remove = versatile_clcd_remove,
686};
687
688#define AACI_IRQ { IRQ_AACI, NO_IRQ }
689#define AACI_DMA { 0x80, 0x81 }
690#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
691#define MMCI0_DMA { 0x84, 0 }
692#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
693#define KMI0_DMA { 0, 0 }
694#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
695#define KMI1_DMA { 0, 0 }
696
697/*
698 * These devices are connected directly to the multi-layer AHB switch
699 */
700#define SMC_IRQ { NO_IRQ, NO_IRQ }
701#define SMC_DMA { 0, 0 }
702#define MPMC_IRQ { NO_IRQ, NO_IRQ }
703#define MPMC_DMA { 0, 0 }
704#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
705#define CLCD_DMA { 0, 0 }
706#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
707#define DMAC_DMA { 0, 0 }
708
709/*
710 * These devices are connected via the core APB bridge
711 */
712#define SCTL_IRQ { NO_IRQ, NO_IRQ }
713#define SCTL_DMA { 0, 0 }
714#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
715#define WATCHDOG_DMA { 0, 0 }
716#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
717#define GPIO0_DMA { 0, 0 }
718#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
719#define GPIO1_DMA { 0, 0 }
720#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
721#define RTC_DMA { 0, 0 }
722
723/*
724 * These devices are connected via the DMA APB bridge
725 */
726#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
727#define SCI_DMA { 7, 6 }
728#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
729#define UART0_DMA { 15, 14 }
730#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
731#define UART1_DMA { 13, 12 }
732#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
733#define UART2_DMA { 11, 10 }
734#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
735#define SSP_DMA { 9, 8 }
736
737/* FPGA Primecells */
738AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
739AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
740AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
741AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
742
743/* DevChip Primecells */
744AMBA_DEVICE(smc, "dev:00", SMC, NULL);
745AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
746AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
747AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
748AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
749AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
750AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
751AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
752AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
753AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
754AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
755AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
756AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
757AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
758
759static struct amba_device *amba_devs[] __initdata = {
760 &dmac_device,
761 &uart0_device,
762 &uart1_device,
763 &uart2_device,
764 &smc_device,
765 &mpmc_device,
766 &clcd_device,
767 &sctl_device,
768 &wdog_device,
769 &gpio0_device,
770 &gpio1_device,
771 &rtc_device,
772 &sci0_device,
773 &ssp0_device,
774 &aaci_device,
775 &mmc0_device,
776 &kmi0_device,
777 &kmi1_device,
778};
779
780#ifdef CONFIG_LEDS
2ad4f86b 781#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 782
783static void versatile_leds_event(led_event_t ledevt)
784{
785 unsigned long flags;
786 u32 val;
787
788 local_irq_save(flags);
789 val = readl(VA_LEDS_BASE);
790
791 switch (ledevt) {
792 case led_idle_start:
793 val = val & ~VERSATILE_SYS_LED0;
794 break;
795
796 case led_idle_end:
797 val = val | VERSATILE_SYS_LED0;
798 break;
799
800 case led_timer:
801 val = val ^ VERSATILE_SYS_LED1;
802 break;
803
804 case led_halted:
805 val = 0;
806 break;
807
808 default:
809 break;
810 }
811
812 writel(val, VA_LEDS_BASE);
813 local_irq_restore(flags);
814}
815#endif /* CONFIG_LEDS */
816
817void __init versatile_init(void)
818{
819 int i;
820
821 clk_register(&versatile_clcd_clk);
822
823 platform_device_register(&versatile_flash_device);
824 platform_device_register(&smc91x_device);
825
826 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
827 struct amba_device *d = amba_devs[i];
828 amba_device_register(d, &iomem_resource);
829 }
830
831#ifdef CONFIG_LEDS
832 leds_event = versatile_leds_event;
833#endif
834}
835
836/*
837 * Where is the timer (VA)?
838 */
2ad4f86b
AV		 839#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
840#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
841#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
842#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
843#define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
1da177e4
LT		 844
845/*
846 * How long is the timer interval?
847 */
848#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
849#if TIMER_INTERVAL >= 0x100000
b720f732
RK		 850#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
851#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
1da177e4
LT		 852#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
853#elif TIMER_INTERVAL >= 0x10000
854#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
b720f732 855#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
1da177e4
LT		 856#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
857#else
858#define TIMER_RELOAD (TIMER_INTERVAL)
b720f732 859#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
1da177e4
LT		 860#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
861#endif
862
1da177e4
LT		 863/*
864 * Returns number of ms since last clock interrupt. Note that interrupts
865 * will have been disabled by do_gettimeoffset()
866 */
867static unsigned long versatile_gettimeoffset(void)
868{
1da177e4
LT		 869 unsigned long ticks1, ticks2, status;
870
871 /*
872 * Get the current number of ticks. Note that there is a race
873 * condition between us reading the timer and checking for
874 * an interrupt. We get around this by ensuring that the
875 * counter has not reloaded between our two reads.
876 */
b720f732 877 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
1da177e4
LT		 878 do {
879 ticks1 = ticks2;
880 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
b720f732 881 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
1da177e4
LT		 882 } while (ticks2 > ticks1);
883
884 /*
885 * Number of ticks since last interrupt.
886 */
887 ticks1 = TIMER_RELOAD - ticks2;
888
889 /*
890 * Interrupt pending? If so, we've reloaded once already.
891 *
892 * FIXME: Need to check this is effectively timer 0 that expires
893 */
894 if (status & IRQMASK_TIMERINT0_1)
895 ticks1 += TIMER_RELOAD;
896
897 /*
898 * Convert the ticks to usecs
899 */
900 return TICKS2USECS(ticks1);
901}
902
903/*
904 * IRQ handler for the timer
905 */
906static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
907{
1da177e4
LT		 908 write_seqlock(&xtime_lock);
909
910 // ...clear the interrupt
b720f732 911 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
1da177e4
LT		 912
913 timer_tick(regs);
914
915 write_sequnlock(&xtime_lock);
916
917 return IRQ_HANDLED;
918}
919
920static struct irqaction versatile_timer_irq = {
921 .name = "Versatile Timer Tick",
09b8b5f8
RK		 922 .flags = SA_INTERRUPT | SA_TIMER,
923 .handler = versatile_timer_interrupt,
1da177e4
LT		 924};
925
926/*
927 * Set up timer interrupt, and return the current time in seconds.
928 */
929static void __init versatile_timer_init(void)
930{
b720f732 931 u32 val;
1da177e4
LT		 932
933 /*
934 * set clock frequency:
935 * VERSATILE_REFCLK is 32KHz
936 * VERSATILE_TIMCLK is 1MHz
937 */
2ad4f86b 938 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 939 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
940 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
941 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
942 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 943 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 944
945 /*
946 * Initialise to a known state (all timers off)
947 */
b720f732
RK		 948 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
949 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
950 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
951 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
952
953 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
954 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
955 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
956 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
1da177e4
LT		 957
958 /*
959 * Make irqs happen for the system timer
960 */
961 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
962}
963
964struct sys_timer versatile_timer = {
965 .init = versatile_timer_init,
966 .offset = versatile_gettimeoffset,
967};
Linux kernel - Deliverables
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