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ARM: 6228/1: PL022 SSP platform data for the Versatile
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
1da177e4
LT		 21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
d052d1be 24#include <linux/platform_device.h>
1da177e4
LT		 25#include <linux/sysdev.h>
26#include <linux/interrupt.h>
a62c80e5
RK		 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h>
bbeddc43 29#include <linux/amba/pl061.h>
6ef297f8 30#include <linux/amba/mmci.h>
ef6f4b12 31#include <linux/amba/pl022.h>
fced80c7 32#include <linux/io.h>
5a0e3ad6 33#include <linux/gfp.h>
1da177e4 34
71a06da0 35#include <asm/clkdev.h>
1da177e4 36#include <asm/system.h>
1da177e4
LT		 37#include <asm/irq.h>
38#include <asm/leds.h>
b720f732 39#include <asm/hardware/arm_timer.h>
c5a0adb5 40#include <asm/hardware/icst.h>
fa0fe48f 41#include <asm/hardware/vic.h>
dc5bc8f1 42#include <asm/mach-types.h>
1da177e4
LT		 43
44#include <asm/mach/arch.h>
45#include <asm/mach/flash.h>
46#include <asm/mach/irq.h>
47#include <asm/mach/time.h>
48#include <asm/mach/map.h>
f4b8b319 49#include <mach/clkdev.h>
a285edcf
RK		 50#include <mach/hardware.h>
51#include <mach/platform.h>
e3887714 52#include <plat/timer-sp.h>
1da177e4
LT		 53
54#include "core.h"
1da177e4
LT		 55
56/*
57 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
58 * is the (PA >> 12).
59 *
60 * Setup a VA for the Versatile Vectored Interrupt Controller.
61 */
2ad4f86b
AV		 62#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
63#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4 64
1da177e4
LT		 65static void sic_mask_irq(unsigned int irq)
66{
67 irq -= IRQ_SIC_START;
68 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
69}
70
71static void sic_unmask_irq(unsigned int irq)
72{
73 irq -= IRQ_SIC_START;
74 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
75}
76
38c677cb
DB		 77static struct irq_chip sic_chip = {
78 .name = "SIC",
1da177e4
LT		 79 .ack = sic_mask_irq,
80 .mask = sic_mask_irq,
81 .unmask = sic_unmask_irq,
82};
83
84static void
10dd5ce2 85sic_handle_irq(unsigned int irq, struct irq_desc *desc)
1da177e4
LT		 86{
87 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
88
89 if (status == 0) {
0cd61b68 90 do_bad_IRQ(irq, desc);
1da177e4
LT		 91 return;
92 }
93
94 do {
95 irq = ffs(status) - 1;
96 status &= ~(1 << irq);
97
98 irq += IRQ_SIC_START;
99
d8aa0251 100 generic_handle_irq(irq);
1da177e4
LT		 101 } while (status);
102}
103
104#if 1
105#define IRQ_MMCI0A IRQ_VICSOURCE22
106#define IRQ_AACI IRQ_VICSOURCE24
107#define IRQ_ETH IRQ_VICSOURCE25
108#define PIC_MASK 0xFFD00000
109#else
110#define IRQ_MMCI0A IRQ_SIC_MMCI0A
111#define IRQ_AACI IRQ_SIC_AACI
112#define IRQ_ETH IRQ_SIC_ETH
113#define PIC_MASK 0
114#endif
115
116void __init versatile_init_irq(void)
117{
fa0fe48f 118 unsigned int i;
1da177e4 119
c07f87f2 120 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
1da177e4 121
56f1319e 122 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
1da177e4
LT		 123
124 /* Do second interrupt controller */
125 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
126
127 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
128 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
129 set_irq_chip(i, &sic_chip);
10dd5ce2 130 set_irq_handler(i, handle_level_irq);
1da177e4
LT		 131 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
132 }
133 }
134
135 /*
136 * Interrupts on secondary controller from 0 to 8 are routed to
137 * source 31 on PIC.
138 * Interrupts from 21 to 31 are routed directly to the VIC on
139 * the corresponding number on primary controller. This is controlled
140 * by setting PIC_ENABLEx.
141 */
142 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
143}
144
145static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 146 {
147 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
148 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
149 .length = SZ_4K,
150 .type = MT_DEVICE
151 }, {
152 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
153 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
154 .length = SZ_4K,
155 .type = MT_DEVICE
156 }, {
157 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
158 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
159 .length = SZ_4K,
160 .type = MT_DEVICE
161 }, {
162 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
163 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
164 .length = SZ_4K * 9,
165 .type = MT_DEVICE
166 },
1da177e4 167#ifdef CONFIG_MACH_VERSATILE_AB
1311521f
DS		 168 {
169 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
170 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
171 .length = SZ_4K,
172 .type = MT_DEVICE
173 }, {
174 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
175 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
176 .length = SZ_64M,
177 .type = MT_DEVICE
178 },
1da177e4
LT		 179#endif
180#ifdef CONFIG_DEBUG_LL
1311521f
DS		 181 {
182 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
183 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
184 .length = SZ_4K,
185 .type = MT_DEVICE
186 },
1da177e4 187#endif
c0da085a 188#ifdef CONFIG_PCI
1311521f
DS		 189 {
190 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
191 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
192 .length = SZ_4K,
193 .type = MT_DEVICE
194 }, {
399ad77b 195 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
1311521f
DS		 196 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
197 .length = VERSATILE_PCI_BASE_SIZE,
198 .type = MT_DEVICE
199 }, {
399ad77b 200 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
1311521f
DS		 201 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
202 .length = VERSATILE_PCI_CFG_BASE_SIZE,
203 .type = MT_DEVICE
204 },
c0da085a 205#if 0
1311521f
DS		 206 {
207 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
208 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
209 .length = SZ_16M,
210 .type = MT_DEVICE
211 }, {
212 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
213 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
214 .length = SZ_16M,
215 .type = MT_DEVICE
216 }, {
217 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
218 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
219 .length = SZ_16M,
220 .type = MT_DEVICE
221 },
c0da085a 222#endif
1da177e4
LT		 223#endif
224};
225
226void __init versatile_map_io(void)
227{
228 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
229}
230
1da177e4 231
2ad4f86b 232#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4
LT		 233
234static int versatile_flash_init(void)
235{
236 u32 val;
237
238 val = __raw_readl(VERSATILE_FLASHCTRL);
239 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
240 __raw_writel(val, VERSATILE_FLASHCTRL);
241
242 return 0;
243}
244
245static void versatile_flash_exit(void)
246{
247 u32 val;
248
249 val = __raw_readl(VERSATILE_FLASHCTRL);
250 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
251 __raw_writel(val, VERSATILE_FLASHCTRL);
252}
253
254static void versatile_flash_set_vpp(int on)
255{
256 u32 val;
257
258 val = __raw_readl(VERSATILE_FLASHCTRL);
259 if (on)
260 val |= VERSATILE_FLASHPROG_FLVPPEN;
261 else
262 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
263 __raw_writel(val, VERSATILE_FLASHCTRL);
264}
265
266static struct flash_platform_data versatile_flash_data = {
267 .map_name = "cfi_probe",
268 .width = 4,
269 .init = versatile_flash_init,
270 .exit = versatile_flash_exit,
271 .set_vpp = versatile_flash_set_vpp,
272};
273
274static struct resource versatile_flash_resource = {
275 .start = VERSATILE_FLASH_BASE,
a0c5a645 276 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
1da177e4
LT		 277 .flags = IORESOURCE_MEM,
278};
279
280static struct platform_device versatile_flash_device = {
281 .name = "armflash",
282 .id = 0,
283 .dev = {
284 .platform_data = &versatile_flash_data,
285 },
286 .num_resources = 1,
287 .resource = &versatile_flash_resource,
288};
289
290static struct resource smc91x_resources[] = {
291 [0] = {
292 .start = VERSATILE_ETH_BASE,
293 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
294 .flags = IORESOURCE_MEM,
295 },
296 [1] = {
297 .start = IRQ_ETH,
298 .end = IRQ_ETH,
299 .flags = IORESOURCE_IRQ,
300 },
301};
302
303static struct platform_device smc91x_device = {
304 .name = "smc91x",
305 .id = 0,
306 .num_resources = ARRAY_SIZE(smc91x_resources),
307 .resource = smc91x_resources,
308};
309
6b65cd74
RK		 310static struct resource versatile_i2c_resource = {
311 .start = VERSATILE_I2C_BASE,
312 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
313 .flags = IORESOURCE_MEM,
314};
315
316static struct platform_device versatile_i2c_device = {
317 .name = "versatile-i2c",
533ad5e6 318 .id = 0,
6b65cd74
RK		 319 .num_resources = 1,
320 .resource = &versatile_i2c_resource,
321};
322
533ad5e6
CM		 323static struct i2c_board_info versatile_i2c_board_info[] = {
324 {
64e8be6e 325 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6
CM		 326 },
327};
328
329static int __init versatile_i2c_init(void)
330{
331 return i2c_register_board_info(0, versatile_i2c_board_info,
332 ARRAY_SIZE(versatile_i2c_board_info));
333}
334arch_initcall(versatile_i2c_init);
335
2ad4f86b 336#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 337
338unsigned int mmc_status(struct device *dev)
339{
340 struct amba_device *adev = container_of(dev, struct amba_device, dev);
341 u32 mask;
342
343 if (adev->res.start == VERSATILE_MMCI0_BASE)
344 mask = 1;
345 else
346 mask = 2;
347
348 return readl(VERSATILE_SYSMCI) & mask;
349}
350
6ef297f8 351static struct mmci_platform_data mmc0_plat_data = {
1da177e4
LT		 352 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
353 .status = mmc_status,
7fb2bbf4
RK		 354 .gpio_wp = -1,
355 .gpio_cd = -1,
1da177e4
LT		 356};
357
358/*
359 * Clock handling
360 */
39c0cb02 361static const struct icst_params versatile_oscvco_params = {
64fceb1d 362 .ref = 24000000,
4de2edbd 363 .vco_max = ICST307_VCO_MAX,
e73a46a3 364 .vco_min = ICST307_VCO_MIN,
1da177e4
LT		 365 .vd_min = 4 + 8,
366 .vd_max = 511 + 8,
367 .rd_min = 1 + 2,
368 .rd_max = 127 + 2,
232eaf7f
RK		 369 .s2div = icst307_s2div,
370 .idx2s = icst307_idx2s,
1da177e4
LT		 371};
372
39c0cb02 373static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
1da177e4 374{
d1914c7e 375 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
1da177e4
LT		 376 u32 val;
377
d1914c7e 378 val = readl(clk->vcoreg) & ~0x7ffff;
1da177e4
LT		 379 val |= vco.v | (vco.r << 9) | (vco.s << 16);
380
381 writel(0xa05f, sys_lock);
d1914c7e 382 writel(val, clk->vcoreg);
1da177e4
LT		 383 writel(0, sys_lock);
384}
385
9bf5b2ef
RK		 386static const struct clk_ops osc4_clk_ops = {
387 .round = icst_clk_round,
388 .set = icst_clk_set,
389 .setvco = versatile_oscvco_set,
390};
391
71a06da0 392static struct clk osc4_clk = {
9bf5b2ef 393 .ops = &osc4_clk_ops,
1da177e4 394 .params = &versatile_oscvco_params,
71a06da0
RK		 395};
396
397/*
398 * These are fixed clocks.
399 */
400static struct clk ref24_clk = {
401 .rate = 24000000,
402};
403
982db663 404static struct clk_lookup lookups[] = {
71a06da0
RK		 405 { /* UART0 */
406 .dev_id = "dev:f1",
407 .clk = &ref24_clk,
408 }, { /* UART1 */
409 .dev_id = "dev:f2",
410 .clk = &ref24_clk,
411 }, { /* UART2 */
412 .dev_id = "dev:f3",
413 .clk = &ref24_clk,
414 }, { /* UART3 */
415 .dev_id = "fpga:09",
416 .clk = &ref24_clk,
417 }, { /* KMI0 */
418 .dev_id = "fpga:06",
419 .clk = &ref24_clk,
420 }, { /* KMI1 */
421 .dev_id = "fpga:07",
422 .clk = &ref24_clk,
423 }, { /* MMC0 */
424 .dev_id = "fpga:05",
425 .clk = &ref24_clk,
426 }, { /* MMC1 */
427 .dev_id = "fpga:0b",
428 .clk = &ref24_clk,
ef6f4b12
LW		 429 }, { /* SSP */
430 .dev_id = "dev:f4",
431 .clk = &ref24_clk,
71a06da0
RK		 432 }, { /* CLCD */
433 .dev_id = "dev:20",
434 .clk = &osc4_clk,
435 }
1da177e4
LT		 436};
437
438/*
439 * CLCD support.
440 */
441#define SYS_CLCD_MODE_MASK (3 << 0)
442#define SYS_CLCD_MODE_888 (0 << 0)
443#define SYS_CLCD_MODE_5551 (1 << 0)
444#define SYS_CLCD_MODE_565_RLSB (2 << 0)
445#define SYS_CLCD_MODE_565_BLSB (3 << 0)
446#define SYS_CLCD_NLCDIOON (1 << 2)
447#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
448#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
449#define SYS_CLCD_ID_MASK (0x1f << 8)
450#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
451#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
452#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
453#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
454#define SYS_CLCD_ID_VGA (0x1f << 8)
455
456static struct clcd_panel vga = {
457 .mode = {
458 .name = "VGA",
459 .refresh = 60,
460 .xres = 640,
461 .yres = 480,
462 .pixclock = 39721,
463 .left_margin = 40,
464 .right_margin = 24,
465 .upper_margin = 32,
466 .lower_margin = 11,
467 .hsync_len = 96,
468 .vsync_len = 2,
469 .sync = 0,
470 .vmode = FB_VMODE_NONINTERLACED,
471 },
472 .width = -1,
473 .height = -1,
474 .tim2 = TIM2_BCD | TIM2_IPC,
475 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
476 .bpp = 16,
477};
478
479static struct clcd_panel sanyo_3_8_in = {
480 .mode = {
481 .name = "Sanyo QVGA",
482 .refresh = 116,
483 .xres = 320,
484 .yres = 240,
485 .pixclock = 100000,
486 .left_margin = 6,
487 .right_margin = 6,
488 .upper_margin = 5,
489 .lower_margin = 5,
490 .hsync_len = 6,
491 .vsync_len = 6,
492 .sync = 0,
493 .vmode = FB_VMODE_NONINTERLACED,
494 },
495 .width = -1,
496 .height = -1,
497 .tim2 = TIM2_BCD,
498 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
499 .bpp = 16,
500};
501
502static struct clcd_panel sanyo_2_5_in = {
503 .mode = {
504 .name = "Sanyo QVGA Portrait",
505 .refresh = 116,
506 .xres = 240,
507 .yres = 320,
508 .pixclock = 100000,
509 .left_margin = 20,
510 .right_margin = 10,
511 .upper_margin = 2,
512 .lower_margin = 2,
513 .hsync_len = 10,
514 .vsync_len = 2,
515 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
516 .vmode = FB_VMODE_NONINTERLACED,
517 },
518 .width = -1,
519 .height = -1,
520 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
521 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
522 .bpp = 16,
523};
524
525static struct clcd_panel epson_2_2_in = {
526 .mode = {
527 .name = "Epson QCIF",
528 .refresh = 390,
529 .xres = 176,
530 .yres = 220,
531 .pixclock = 62500,
532 .left_margin = 3,
533 .right_margin = 2,
534 .upper_margin = 1,
535 .lower_margin = 0,
536 .hsync_len = 3,
537 .vsync_len = 2,
538 .sync = 0,
539 .vmode = FB_VMODE_NONINTERLACED,
540 },
541 .width = -1,
542 .height = -1,
543 .tim2 = TIM2_BCD | TIM2_IPC,
544 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
545 .bpp = 16,
546};
547
548/*
549 * Detect which LCD panel is connected, and return the appropriate
550 * clcd_panel structure. Note: we do not have any information on
551 * the required timings for the 8.4in panel, so we presently assume
552 * VGA timings.
553 */
554static struct clcd_panel *versatile_clcd_panel(void)
555{
2ad4f86b 556 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 557 struct clcd_panel *panel = &vga;
558 u32 val;
559
560 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
561 if (val == SYS_CLCD_ID_SANYO_3_8)
562 panel = &sanyo_3_8_in;
563 else if (val == SYS_CLCD_ID_SANYO_2_5)
564 panel = &sanyo_2_5_in;
565 else if (val == SYS_CLCD_ID_EPSON_2_2)
566 panel = &epson_2_2_in;
567 else if (val == SYS_CLCD_ID_VGA)
568 panel = &vga;
569 else {
570 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
571 val);
572 panel = &vga;
573 }
574
575 return panel;
576}
577
578/*
579 * Disable all display connectors on the interface module.
580 */
581static void versatile_clcd_disable(struct clcd_fb *fb)
582{
2ad4f86b 583 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 584 u32 val;
585
586 val = readl(sys_clcd);
587 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
588 writel(val, sys_clcd);
589
590#ifdef CONFIG_MACH_VERSATILE_AB
591 /*
592 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
593 */
dc5bc8f1 594 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 595 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 596 unsigned long ctrl;
597
598 ctrl = readl(versatile_ib2_ctrl);
599 ctrl &= ~0x01;
600 writel(ctrl, versatile_ib2_ctrl);
601 }
602#endif
603}
604
605/*
606 * Enable the relevant connector on the interface module.
607 */
608static void versatile_clcd_enable(struct clcd_fb *fb)
609{
2ad4f86b 610 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 611 u32 val;
612
613 val = readl(sys_clcd);
614 val &= ~SYS_CLCD_MODE_MASK;
615
616 switch (fb->fb.var.green.length) {
617 case 5:
618 val |= SYS_CLCD_MODE_5551;
619 break;
620 case 6:
90ef713b 621 val |= SYS_CLCD_MODE_565_RLSB;
1da177e4
LT		 622 break;
623 case 8:
624 val |= SYS_CLCD_MODE_888;
625 break;
626 }
627
628 /*
629 * Set the MUX
630 */
631 writel(val, sys_clcd);
632
633 /*
634 * And now enable the PSUs
635 */
636 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
637 writel(val, sys_clcd);
638
639#ifdef CONFIG_MACH_VERSATILE_AB
640 /*
641 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
642 */
dc5bc8f1 643 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 644 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 645 unsigned long ctrl;
646
647 ctrl = readl(versatile_ib2_ctrl);
648 ctrl |= 0x01;
649 writel(ctrl, versatile_ib2_ctrl);
650 }
651#endif
652}
653
654static unsigned long framesize = SZ_1M;
655
656static int versatile_clcd_setup(struct clcd_fb *fb)
657{
658 dma_addr_t dma;
659
660 fb->panel = versatile_clcd_panel();
661
662 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
663 &dma, GFP_KERNEL);
664 if (!fb->fb.screen_base) {
665 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
666 return -ENOMEM;
667 }
668
669 fb->fb.fix.smem_start = dma;
670 fb->fb.fix.smem_len = framesize;
671
672 return 0;
673}
674
675static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
676{
677 return dma_mmap_writecombine(&fb->dev->dev, vma,
678 fb->fb.screen_base,
679 fb->fb.fix.smem_start,
680 fb->fb.fix.smem_len);
681}
682
683static void versatile_clcd_remove(struct clcd_fb *fb)
684{
685 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
686 fb->fb.screen_base, fb->fb.fix.smem_start);
687}
688
689static struct clcd_board clcd_plat_data = {
690 .name = "Versatile",
691 .check = clcdfb_check,
692 .decode = clcdfb_decode,
693 .disable = versatile_clcd_disable,
694 .enable = versatile_clcd_enable,
695 .setup = versatile_clcd_setup,
696 .mmap = versatile_clcd_mmap,
697 .remove = versatile_clcd_remove,
698};
699
bbeddc43
RK		 700static struct pl061_platform_data gpio0_plat_data = {
701 .gpio_base = 0,
702 .irq_base = IRQ_GPIO0_START,
703};
704
705static struct pl061_platform_data gpio1_plat_data = {
706 .gpio_base = 8,
707 .irq_base = IRQ_GPIO1_START,
708};
709
ef6f4b12
LW		 710static struct pl022_ssp_controller ssp0_plat_data = {
711 .bus_id = 0,
712 .enable_dma = 0,
713 .num_chipselect = 1,
714};
715
1da177e4
LT		 716#define AACI_IRQ { IRQ_AACI, NO_IRQ }
717#define AACI_DMA { 0x80, 0x81 }
718#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
719#define MMCI0_DMA { 0x84, 0 }
720#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
721#define KMI0_DMA { 0, 0 }
722#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
723#define KMI1_DMA { 0, 0 }
724
725/*
726 * These devices are connected directly to the multi-layer AHB switch
727 */
728#define SMC_IRQ { NO_IRQ, NO_IRQ }
729#define SMC_DMA { 0, 0 }
730#define MPMC_IRQ { NO_IRQ, NO_IRQ }
731#define MPMC_DMA { 0, 0 }
732#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
733#define CLCD_DMA { 0, 0 }
734#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
735#define DMAC_DMA { 0, 0 }
736
737/*
738 * These devices are connected via the core APB bridge
739 */
740#define SCTL_IRQ { NO_IRQ, NO_IRQ }
741#define SCTL_DMA { 0, 0 }
742#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
743#define WATCHDOG_DMA { 0, 0 }
744#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
745#define GPIO0_DMA { 0, 0 }
746#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
747#define GPIO1_DMA { 0, 0 }
748#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
749#define RTC_DMA { 0, 0 }
750
751/*
752 * These devices are connected via the DMA APB bridge
753 */
754#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
755#define SCI_DMA { 7, 6 }
756#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
757#define UART0_DMA { 15, 14 }
758#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
759#define UART1_DMA { 13, 12 }
760#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
761#define UART2_DMA { 11, 10 }
762#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
763#define SSP_DMA { 9, 8 }
764
765/* FPGA Primecells */
766AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
767AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
768AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
769AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
770
771/* DevChip Primecells */
772AMBA_DEVICE(smc, "dev:00", SMC, NULL);
773AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
774AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
775AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
776AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
777AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
bbeddc43
RK		 778AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
779AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
1da177e4
LT		 780AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
781AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
782AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
783AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
784AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
ef6f4b12 785AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
1da177e4
LT		 786
787static struct amba_device *amba_devs[] __initdata = {
788 &dmac_device,
789 &uart0_device,
790 &uart1_device,
791 &uart2_device,
792 &smc_device,
793 &mpmc_device,
794 &clcd_device,
795 &sctl_device,
796 &wdog_device,
797 &gpio0_device,
798 &gpio1_device,
799 &rtc_device,
800 &sci0_device,
801 &ssp0_device,
802 &aaci_device,
803 &mmc0_device,
804 &kmi0_device,
805 &kmi1_device,
806};
807
808#ifdef CONFIG_LEDS
2ad4f86b 809#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 810
811static void versatile_leds_event(led_event_t ledevt)
812{
813 unsigned long flags;
814 u32 val;
815
816 local_irq_save(flags);
817 val = readl(VA_LEDS_BASE);
818
819 switch (ledevt) {
820 case led_idle_start:
821 val = val & ~VERSATILE_SYS_LED0;
822 break;
823
824 case led_idle_end:
825 val = val | VERSATILE_SYS_LED0;
826 break;
827
828 case led_timer:
829 val = val ^ VERSATILE_SYS_LED1;
830 break;
831
832 case led_halted:
833 val = 0;
834 break;
835
836 default:
837 break;
838 }
839
840 writel(val, VA_LEDS_BASE);
841 local_irq_restore(flags);
842}
843#endif /* CONFIG_LEDS */
844
845void __init versatile_init(void)
846{
847 int i;
848
d1914c7e
RK		 849 osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
850
0a0300dc 851 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1da177e4
LT		 852
853 platform_device_register(&versatile_flash_device);
6b65cd74 854 platform_device_register(&versatile_i2c_device);
1da177e4
LT		 855 platform_device_register(&smc91x_device);
856
857 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
858 struct amba_device *d = amba_devs[i];
859 amba_device_register(d, &iomem_resource);
860 }
861
862#ifdef CONFIG_LEDS
863 leds_event = versatile_leds_event;
864#endif
865}
866
867/*
868 * Where is the timer (VA)?
869 */
2ad4f86b
AV		 870#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
871#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
872#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
873#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
b49c87c2 874
1da177e4
LT		 875/*
876 * Set up timer interrupt, and return the current time in seconds.
877 */
878static void __init versatile_timer_init(void)
879{
b720f732 880 u32 val;
1da177e4
LT		 881
882 /*
883 * set clock frequency:
884 * VERSATILE_REFCLK is 32KHz
885 * VERSATILE_TIMCLK is 1MHz
886 */
2ad4f86b 887 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 888 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
889 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
890 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
891 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 892 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 893
894 /*
895 * Initialise to a known state (all timers off)
896 */
b720f732
RK		 897 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
898 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
899 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
900 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
901
e3887714
RK		 902 sp804_clocksource_init(TIMER3_VA_BASE);
903 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
1da177e4
LT		 904}
905
906struct sys_timer versatile_timer = {
907 .init = versatile_timer_init,
1da177e4 908};
b49c87c2 909
Linux kernel - Deliverables
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