[deliverable/linux.git] / arch / arm / mach-versatile / pci.c

/*
 *  linux/arch/arm/mach-versatile/pci.c
 *
 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
 * You can redistribute and/or modify this software under the terms of version 2
 * of the GNU General Public License as published by the Free Software Foundation.
 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
 *
 * ARM Versatile PCI driver.
 *
 * 14/04/2005 Initial version, colin.king@philips.com
 *
 */
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>

/*
 * these spaces are mapped using the following base registers:
 *
 * Usage Local Bus Memory         Base/Map registers used
 *
 * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0,  non prefetch
 * Mem   60000000 - 6FFFFFFF      LB_BASE1/LB_MAP1,  prefetch
 * IO    44000000 - 4FFFFFFF      LB_BASE2/LB_MAP2,  IO
 * Cfg   42000000 - 42FFFFFF	  PCI config
 *
 */
#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
#define SYS_PCICTL		__IO_ADDRESS(VERSATILE_SYS_PCICTL)
#define PCI_IMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
#define PCI_IMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
#define PCI_IMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
#define PCI_SMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
#define PCI_SMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
#define PCI_SMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
#define PCI_SELFID		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)

#define DEVICE_ID_OFFSET		0x00
#define CSR_OFFSET			0x04
#define CLASS_ID_OFFSET			0x08

#define VP_PCI_DEVICE_ID		0x030010ee
#define VP_PCI_CLASS_ID			0x0b400000

static unsigned long pci_slot_ignore = 0;

static int __init versatile_pci_slot_ignore(char *str)
{
	int retval;
	int slot;

	while ((retval = get_option(&str,&slot))) {
		if ((slot < 0) || (slot > 31)) {
			printk("Illegal slot value: %d\n",slot);
		} else {
			pci_slot_ignore |= (1 << slot);
		}
	}
	return 1;
}

__setup("pci_slot_ignore=", versatile_pci_slot_ignore);


static void __iomem *__pci_addr(struct pci_bus *bus,
				unsigned int devfn, int offset)
{
	unsigned int busnr = bus->number;

	/*
	 * Trap out illegal values
	 */
	if (offset > 255)
		BUG();
	if (busnr > 255)
		BUG();
	if (devfn > 255)
		BUG();

	return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
		(PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
}

static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
				 int size, u32 *val)
{
	void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
	u32 v;
	int slot = PCI_SLOT(devfn);

	if (pci_slot_ignore & (1 << slot)) {
		/* Ignore this slot */
		switch (size) {
		case 1:
			v = 0xff;
			break;
		case 2:
			v = 0xffff;
			break;
		default:
			v = 0xffffffff;
		}
	} else {
		switch (size) {
		case 1:
			v = __raw_readl(addr);
			if (where & 2) v >>= 16;
			if (where & 1) v >>= 8;
 			v &= 0xff;
			break;

		case 2:
			v = __raw_readl(addr);
			if (where & 2) v >>= 16;
 			v &= 0xffff;
			break;

		default:
			v = __raw_readl(addr);
			break;
		}
	}

	*val = v;
	return PCIBIOS_SUCCESSFUL;
}

static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
				  int size, u32 val)
{
	void __iomem *addr = __pci_addr(bus, devfn, where);
	int slot = PCI_SLOT(devfn);

	if (pci_slot_ignore & (1 << slot)) {
		return PCIBIOS_SUCCESSFUL;
	}

	switch (size) {
	case 1:
		__raw_writeb((u8)val, addr);
		break;

	case 2:
		__raw_writew((u16)val, addr);
		break;

	case 4:
		__raw_writel(val, addr);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pci_versatile_ops = {
	.read	= versatile_read_config,
	.write	= versatile_write_config,
};

static struct resource io_port = {
	.name	= "PCI",
	.start	= 0,
	.end	= IO_SPACE_LIMIT,
	.flags	= IORESOURCE_IO,
};

static struct resource io_mem = {
	.name	= "PCI I/O space",
	.start	= VERSATILE_PCI_MEM_BASE0,
	.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
	.flags	= IORESOURCE_MEM,
};

static struct resource non_mem = {
	.name	= "PCI non-prefetchable",
	.start	= VERSATILE_PCI_MEM_BASE1,
	.end	= VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
	.flags	= IORESOURCE_MEM,
};

static struct resource pre_mem = {
	.name	= "PCI prefetchable",
	.start	= VERSATILE_PCI_MEM_BASE2,
	.end	= VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
	.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
};

static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
{
	int ret = 0;

	ret = request_resource(&iomem_resource, &io_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate I/O "
		       "memory region (%d)\n", ret);
		goto out;
	}
	ret = request_resource(&ioport_resource, &io_port);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate I/O "
		       "port region (%d)\n", ret);
		goto out;
	}
	ret = request_resource(&iomem_resource, &non_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
		       "memory region (%d)\n", ret);
		goto release_io_mem;
	}
	ret = request_resource(&iomem_resource, &pre_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate prefetchable "
		       "memory region (%d)\n", ret);
		goto release_non_mem;
	}

	/*
	 * the IO resource for this bus
	 * the mem resource for this bus
	 * the prefetch mem resource for this bus
	 */
	pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset);
	pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
	pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);

	goto out;

 release_non_mem:
	release_resource(&non_mem);
 release_io_mem:
	release_resource(&io_mem);
 out:
	return ret;
}

int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;
        int i;
        int myslot = -1;
	unsigned long val;
	void __iomem *local_pci_cfg_base;

	val = __raw_readl(SYS_PCICTL);
	if (!(val & 1)) {
		printk("Not plugged into PCI backplane!\n");
		ret = -EIO;
		goto out;
	}

	if (nr == 0) {
		sys->mem_offset = 0;
		sys->io_offset = 0;
		ret = pci_versatile_setup_resources(sys);
		if (ret < 0) {
			printk("pci_versatile_setup: resources... oops?\n");
			goto out;
		}
	} else {
		printk("pci_versatile_setup: resources... nr == 0??\n");
		goto out;
	}

	/*
	 *  We need to discover the PCI core first to configure itself
	 *  before the main PCI probing is performed
	 */
	for (i=0; i<32; i++)
		if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
		    (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
			myslot = i;
			break;
		}

	if (myslot == -1) {
		printk("Cannot find PCI core!\n");
		ret = -EIO;
		goto out;
	}

	printk("PCI core found (slot %d)\n",myslot);

	__raw_writel(myslot, PCI_SELFID);
	local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);

	val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
	val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
	__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);

	/*
	 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	 */
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);

	/*
	 * Do not to map Versatile FPGA PCI device into memory space
	 */
	pci_slot_ignore |= (1 << myslot);
	ret = 1;

 out:
	return ret;
}


void __init pci_versatile_preinit(void)
{
	pcibios_min_io = 0x44000000;
	pcibios_min_mem = 0x50000000;

	__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
	__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
	__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);

	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);

	__raw_writel(1, SYS_PCICTL);
}

/*
 * map the specified device/slot/pin to an IRQ.   Different backplanes may need to modify this.
 */
static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	/* slot,  pin,	irq
	 *  24     1     27
	 *  25     1     28
	 *  26     1     29
	 *  27     1     30
	 */
	irq = 27 + ((slot - 24 + pin - 1) & 3);

	return irq;
}

static struct hw_pci versatile_pci __initdata = {
	.map_irq		= versatile_map_irq,
	.nr_controllers		= 1,
	.ops			= &pci_versatile_ops,
	.setup			= pci_versatile_setup,
	.preinit		= pci_versatile_preinit,
};

static int __init versatile_pci_init(void)
{
	pci_common_init(&versatile_pci);
	return 0;
}

subsys_initcall(versatile_pci_init);
Commit	Line	Data
c0da085a CM	1	/*
	2	* linux/arch/arm/mach-versatile/pci.c
	3	*
	4	* (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
	5	* You can redistribute and/or modify this software under the terms of version 2
	6	* of the GNU General Public License as published by the Free Software Foundation.
	7	* THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
	8	* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	9	* General Public License for more details.
	10	* Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
	11	*
	12	* ARM Versatile PCI driver.
	13	*
	14	* 14/04/2005 Initial version, colin.king@philips.com
	15	*
	16	*/
c0da085a CM	17	#include <linux/kernel.h>
c0da085a CM	18	#include <linux/pci.h>
c0da085a CM	19	#include <linux/ioport.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/init.h>
fced80c7	23	#include <linux/io.h>
c0da085a	24
a09e64fb	25	#include <mach/hardware.h>
c0da085a	26	#include <asm/irq.h>
c0da085a	27	#include <asm/mach/pci.h>
c0da085a CM	28
	29	/*
	30	* these spaces are mapped using the following base registers:
	31	*
	32	* Usage Local Bus Memory Base/Map registers used
	33	*
	34	* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
	35	* Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
	36	* IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
	37	* Cfg 42000000 - 42FFFFFF PCI config
	38	*
	39	*/
399ad77b AV	40	#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
	41	#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
	42	#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
	43	#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
	44	#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
	45	#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
	46	#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
	47	#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
	48	#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
c0da085a CM	49
	50	#define DEVICE_ID_OFFSET 0x00
	51	#define CSR_OFFSET 0x04
	52	#define CLASS_ID_OFFSET 0x08
	53
	54	#define VP_PCI_DEVICE_ID 0x030010ee
	55	#define VP_PCI_CLASS_ID 0x0b400000
	56
	57	static unsigned long pci_slot_ignore = 0;
	58
	59	static int __init versatile_pci_slot_ignore(char *str)
	60	{
	61	int retval;
	62	int slot;
	63
	64	while ((retval = get_option(&str,&slot))) {
	65	if ((slot < 0) \|\| (slot > 31)) {
	66	printk("Illegal slot value: %d\n",slot);
	67	} else {
	68	pci_slot_ignore \|= (1 << slot);
	69	}
	70	}
	71	return 1;
	72	}
	73
	74	__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
	75
	76
399ad77b	77	static void __iomem __pci_addr(struct pci_bus bus,
c0da085a CM	78	unsigned int devfn, int offset)
	79	{
	80	unsigned int busnr = bus->number;
	81
	82	/*
	83	* Trap out illegal values
	84	*/
	85	if (offset > 255)
	86	BUG();
	87	if (busnr > 255)
	88	BUG();
	89	if (devfn > 255)
	90	BUG();
	91
399ad77b	92	return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) \|
c0da085a CM	93	(PCI_SLOT(devfn) << 11) \| (PCI_FUNC(devfn) << 8) \| offset);
	94	}
	95
	96	static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
	97	int size, u32 *val)
	98	{
399ad77b	99	void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
c0da085a CM	100	u32 v;
	101	int slot = PCI_SLOT(devfn);
	102
	103	if (pci_slot_ignore & (1 << slot)) {
	104	/* Ignore this slot */
	105	switch (size) {
	106	case 1:
	107	v = 0xff;
	108	break;
	109	case 2:
	110	v = 0xffff;
	111	break;
	112	default:
	113	v = 0xffffffff;
	114	}
	115	} else {
	116	switch (size) {
	117	case 1:
756813ca AZ	118	v = __raw_readl(addr);
	119	if (where & 2) v >>= 16;
	120	if (where & 1) v >>= 8;
	121	v &= 0xff;
c0da085a CM	122	break;
	123
	124	case 2:
399ad77b AV	125	v = __raw_readl(addr);
399ad77b AV	126	if (where & 2) v >>= 16;
c0da085a CM	127	v &= 0xffff;
	128	break;
	129
	130	default:
c0da085a CM	131	v = __raw_readl(addr);
	132	break;
	133	}
	134	}
	135
	136	*val = v;
	137	return PCIBIOS_SUCCESSFUL;
	138	}
	139
	140	static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
	141	int size, u32 val)
	142	{
399ad77b	143	void __iomem *addr = __pci_addr(bus, devfn, where);
c0da085a CM	144	int slot = PCI_SLOT(devfn);
	145
	146	if (pci_slot_ignore & (1 << slot)) {
	147	return PCIBIOS_SUCCESSFUL;
	148	}
	149
	150	switch (size) {
	151	case 1:
	152	__raw_writeb((u8)val, addr);
	153	break;
	154
	155	case 2:
	156	__raw_writew((u16)val, addr);
	157	break;
	158
	159	case 4:
	160	__raw_writel(val, addr);
	161	break;
	162	}
	163
	164	return PCIBIOS_SUCCESSFUL;
	165	}
	166
	167	static struct pci_ops pci_versatile_ops = {
	168	.read = versatile_read_config,
	169	.write = versatile_write_config,
	170	};
	171
9b0f7e39 AB	172	static struct resource io_port = {
	173	.name = "PCI",
	174	.start = 0,
	175	.end = IO_SPACE_LIMIT,
	176	.flags = IORESOURCE_IO,
	177	};
	178
c0da085a CM	179	static struct resource io_mem = {
	180	.name = "PCI I/O space",
	181	.start = VERSATILE_PCI_MEM_BASE0,
	182	.end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
9b0f7e39	183	.flags = IORESOURCE_MEM,
c0da085a CM	184	};
	185
	186	static struct resource non_mem = {
	187	.name = "PCI non-prefetchable",
	188	.start = VERSATILE_PCI_MEM_BASE1,
	189	.end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
	190	.flags = IORESOURCE_MEM,
	191	};
	192
	193	static struct resource pre_mem = {
	194	.name = "PCI prefetchable",
	195	.start = VERSATILE_PCI_MEM_BASE2,
	196	.end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
	197	.flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH,
	198	};
	199
ee5324ea	200	static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
c0da085a CM	201	{
	202	int ret = 0;
	203
	204	ret = request_resource(&iomem_resource, &io_mem);
	205	if (ret) {
	206	printk(KERN_ERR "PCI: unable to allocate I/O "
	207	"memory region (%d)\n", ret);
	208	goto out;
	209	}
9b0f7e39 AB	210	ret = request_resource(&ioport_resource, &io_port);
	211	if (ret) {
	212	printk(KERN_ERR "PCI: unable to allocate I/O "
	213	"port region (%d)\n", ret);
	214	goto out;
	215	}
c0da085a CM	216	ret = request_resource(&iomem_resource, &non_mem);
	217	if (ret) {
	218	printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
	219	"memory region (%d)\n", ret);
	220	goto release_io_mem;
	221	}
	222	ret = request_resource(&iomem_resource, &pre_mem);
	223	if (ret) {
	224	printk(KERN_ERR "PCI: unable to allocate prefetchable "
	225	"memory region (%d)\n", ret);
	226	goto release_non_mem;
	227	}
	228
	229	/*
37d15909 BH	230	* the IO resource for this bus
	231	* the mem resource for this bus
	232	* the prefetch mem resource for this bus
c0da085a	233	*/
9b0f7e39	234	pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset);
ee5324ea PG	235	pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
ee5324ea PG	236	pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
c0da085a CM	237
	238	goto out;
	239
	240	release_non_mem:
	241	release_resource(&non_mem);
	242	release_io_mem:
	243	release_resource(&io_mem);
	244	out:
	245	return ret;
	246	}
	247
	248	int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
	249	{
	250	int ret = 0;
	251	int i;
	252	int myslot = -1;
	253	unsigned long val;
c27a2164 CM	254	void __iomem *local_pci_cfg_base;
	255
	256	val = __raw_readl(SYS_PCICTL);
	257	if (!(val & 1)) {
	258	printk("Not plugged into PCI backplane!\n");
	259	ret = -EIO;
	260	goto out;
	261	}
c0da085a CM	262
	263	if (nr == 0) {
	264	sys->mem_offset = 0;
9b0f7e39	265	sys->io_offset = 0;
ee5324ea	266	ret = pci_versatile_setup_resources(sys);
c0da085a CM	267	if (ret < 0) {
	268	printk("pci_versatile_setup: resources... oops?\n");
	269	goto out;
	270	}
	271	} else {
	272	printk("pci_versatile_setup: resources... nr == 0??\n");
	273	goto out;
	274	}
	275
c0da085a CM	276	/*
	277	* We need to discover the PCI core first to configure itself
	278	* before the main PCI probing is performed
	279	*/
c27a2164	280	for (i=0; i<32; i++)
c0da085a CM	281	if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
	282	(__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
	283	myslot = i;
c0da085a CM	284	break;
c0da085a CM	285	}
c0da085a CM	286
	287	if (myslot == -1) {
	288	printk("Cannot find PCI core!\n");
	289	ret = -EIO;
c27a2164	290	goto out;
c0da085a CM	291	}
c0da085a CM	292
c27a2164 CM	293	printk("PCI core found (slot %d)\n",myslot);
	294
	295	__raw_writel(myslot, PCI_SELFID);
399ad77b	296	local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
c27a2164 CM	297
	298	val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
	299	val \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \| PCI_COMMAND_INVALIDATE;
	300	__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
	301
	302	/*
	303	* Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	304	*/
	305	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	306	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	307	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
	308
	309	/*
	310	* Do not to map Versatile FPGA PCI device into memory space
	311	*/
	312	pci_slot_ignore \|= (1 << myslot);
	313	ret = 1;
	314
c0da085a CM	315	out:
	316	return ret;
	317	}
	318
	319
c0da085a CM	320	void __init pci_versatile_preinit(void)
c0da085a CM	321	{
c9d95fbe RH	322	pcibios_min_io = 0x44000000;
	323	pcibios_min_mem = 0x50000000;
	324
c27a2164 CM	325	__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
	326	__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
	327	__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
c0da085a	328
c27a2164 CM	329	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
	330	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
	331	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
c0da085a	332
c27a2164 CM	333	__raw_writel(1, SYS_PCICTL);
c27a2164 CM	334	}
c0da085a CM	335
	336	/*
	337	* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
	338	*/
d5341942	339	static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
c0da085a CM	340	{
c0da085a CM	341	int irq;
c0da085a	342
c27a2164 CM	343	/* slot, pin, irq
	344	* 24 1 27
	345	* 25 1 28
	346	* 26 1 29
	347	* 27 1 30
	348	*/
1bc39ac5	349	irq = 27 + ((slot - 24 + pin - 1) & 3);
c0da085a CM	350
	351	return irq;
	352	}
	353
	354	static struct hw_pci versatile_pci __initdata = {
c0da085a CM	355	.map_irq = versatile_map_irq,
c0da085a CM	356	.nr_controllers = 1,
c23bfc38	357	.ops = &pci_versatile_ops,
c0da085a	358	.setup = pci_versatile_setup,
c0da085a	359	.preinit = pci_versatile_preinit,
c0da085a CM	360	};
	361
	362	static int __init versatile_pci_init(void)
	363	{
	364	pci_common_init(&versatile_pci);
	365	return 0;
	366	}
	367
	368	subsys_initcall(versatile_pci_init);