[deliverable/linux.git] / arch / arm / mach-versatile / pci.c

/*
 *  linux/arch/arm/mach-versatile/pci.c
 *
 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
 * You can redistribute and/or modify this software under the terms of version 2
 * of the GNU General Public License as published by the Free Software Foundation.
 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
 *
 * ARM Versatile PCI driver.
 *
 * 14/04/2005 Initial version, colin.king@philips.com
 *
 */
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/init.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/mach/pci.h>

/*
 * these spaces are mapped using the following base registers:
 *
 * Usage Local Bus Memory         Base/Map registers used
 *
 * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0,  non prefetch
 * Mem   60000000 - 6FFFFFFF      LB_BASE1/LB_MAP1,  prefetch
 * IO    44000000 - 4FFFFFFF      LB_BASE2/LB_MAP2,  IO
 * Cfg   42000000 - 42FFFFFF	  PCI config
 *
 */
#define SYS_PCICTL			IO_ADDRESS(VERSATILE_SYS_PCICTL)
#define PCI_IMAP0			IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
#define PCI_IMAP1			IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
#define PCI_IMAP2			IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
#define PCI_SMAP0			IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
#define PCI_SMAP1			IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
#define PCI_SMAP2			IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
#define PCI_SELFID			IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)

#define DEVICE_ID_OFFSET		0x00
#define CSR_OFFSET			0x04
#define CLASS_ID_OFFSET			0x08

#define VP_PCI_DEVICE_ID		0x030010ee
#define VP_PCI_CLASS_ID			0x0b400000

static unsigned long pci_slot_ignore = 0;

static int __init versatile_pci_slot_ignore(char *str)
{
	int retval;
	int slot;

	while ((retval = get_option(&str,&slot))) {
		if ((slot < 0) || (slot > 31)) {
			printk("Illegal slot value: %d\n",slot);
		} else {
			pci_slot_ignore |= (1 << slot);
		}
	}
	return 1;
}

__setup("pci_slot_ignore=", versatile_pci_slot_ignore);


static unsigned long __pci_addr(struct pci_bus *bus,
				unsigned int devfn, int offset)
{
	unsigned int busnr = bus->number;

	/*
	 * Trap out illegal values
	 */
	if (offset > 255)
		BUG();
	if (busnr > 255)
		BUG();
	if (devfn > 255)
		BUG();

	return (VERSATILE_PCI_CFG_VIRT_BASE | (busnr << 16) |
		(PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
}

static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
				 int size, u32 *val)
{
	unsigned long addr = __pci_addr(bus, devfn, where);
	u32 v;
	int slot = PCI_SLOT(devfn);

	if (pci_slot_ignore & (1 << slot)) {
		/* Ignore this slot */
		switch (size) {
		case 1:
			v = 0xff;
			break;
		case 2:
			v = 0xffff;
			break;
		default:
			v = 0xffffffff;
		}
	} else {
		switch (size) {
		case 1:
			v = __raw_readb(addr);
			break;

		case 2:
			v = __raw_readl(addr & ~3);
			if (addr & 2) v >>= 16;
 			v &= 0xffff;
			break;

		default:
			addr &= ~3;
			v = __raw_readl(addr);
			break;
		}
	}

	*val = v;
	return PCIBIOS_SUCCESSFUL;
}

static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
				  int size, u32 val)
{
	unsigned long addr = __pci_addr(bus, devfn, where);
	int slot = PCI_SLOT(devfn);

	if (pci_slot_ignore & (1 << slot)) {
		return PCIBIOS_SUCCESSFUL;
	}

	switch (size) {
	case 1:
		__raw_writeb((u8)val, addr);
		break;

	case 2:
		__raw_writew((u16)val, addr);
		break;

	case 4:
		__raw_writel(val, addr);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pci_versatile_ops = {
	.read	= versatile_read_config,
	.write	= versatile_write_config,
};

static struct resource io_mem = {
	.name	= "PCI I/O space",
	.start	= VERSATILE_PCI_MEM_BASE0,
	.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
	.flags	= IORESOURCE_IO,
};

static struct resource non_mem = {
	.name	= "PCI non-prefetchable",
	.start	= VERSATILE_PCI_MEM_BASE1,
	.end	= VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
	.flags	= IORESOURCE_MEM,
};

static struct resource pre_mem = {
	.name	= "PCI prefetchable",
	.start	= VERSATILE_PCI_MEM_BASE2,
	.end	= VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
	.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
};

static int __init pci_versatile_setup_resources(struct resource **resource)
{
	int ret = 0;

	ret = request_resource(&iomem_resource, &io_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate I/O "
		       "memory region (%d)\n", ret);
		goto out;
	}
	ret = request_resource(&iomem_resource, &non_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
		       "memory region (%d)\n", ret);
		goto release_io_mem;
	}
	ret = request_resource(&iomem_resource, &pre_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate prefetchable "
		       "memory region (%d)\n", ret);
		goto release_non_mem;
	}

	/*
	 * bus->resource[0] is the IO resource for this bus
	 * bus->resource[1] is the mem resource for this bus
	 * bus->resource[2] is the prefetch mem resource for this bus
	 */
	resource[0] = &io_mem;
	resource[1] = &non_mem;
	resource[2] = &pre_mem;

	goto out;

 release_non_mem:
	release_resource(&non_mem);
 release_io_mem:
	release_resource(&io_mem);
 out:
	return ret;
}

int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;
        int i;
        int myslot = -1;
	unsigned long val;
	void __iomem *local_pci_cfg_base;

	val = __raw_readl(SYS_PCICTL);
	if (!(val & 1)) {
		printk("Not plugged into PCI backplane!\n");
		ret = -EIO;
		goto out;
	}

	if (nr == 0) {
		sys->mem_offset = 0;
		ret = pci_versatile_setup_resources(sys->resource);
		if (ret < 0) {
			printk("pci_versatile_setup: resources... oops?\n");
			goto out;
		}
	} else {
		printk("pci_versatile_setup: resources... nr == 0??\n");
		goto out;
	}

	/*
	 *  We need to discover the PCI core first to configure itself
	 *  before the main PCI probing is performed
	 */
	for (i=0; i<32; i++)
		if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
		    (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
			myslot = i;
			break;
		}

	if (myslot == -1) {
		printk("Cannot find PCI core!\n");
		ret = -EIO;
		goto out;
	}

	printk("PCI core found (slot %d)\n",myslot);

	__raw_writel(myslot, PCI_SELFID);
	local_pci_cfg_base = (void *) VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);

	val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
	val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
	__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);

	/*
	 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	 */
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);

	/*
	 * Do not to map Versatile FPGA PCI device into memory space
	 */
	pci_slot_ignore |= (1 << myslot);
	ret = 1;

 out:
	return ret;
}


struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
{
	return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
}

void __init pci_versatile_preinit(void)
{
	__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
	__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
	__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);

	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);

	__raw_writel(1, SYS_PCICTL);
}

/*
 * map the specified device/slot/pin to an IRQ.   Different backplanes may need to modify this.
 */
static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;
	int devslot = PCI_SLOT(dev->devfn);

	/* slot,  pin,	irq
	 *  24     1     27
	 *  25     1     28
	 *  26     1     29
	 *  27     1     30
	 */
	irq = 27 + ((slot + pin - 1) & 3);

	printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);

	return irq;
}

static struct hw_pci versatile_pci __initdata = {
	.swizzle		= NULL,
	.map_irq		= versatile_map_irq,
	.nr_controllers		= 1,
	.setup			= pci_versatile_setup,
	.scan			= pci_versatile_scan_bus,
	.preinit		= pci_versatile_preinit,
};

static int __init versatile_pci_init(void)
{
	pci_common_init(&versatile_pci);
	return 0;
}

subsys_initcall(versatile_pci_init);
Commit	Line	Data
c0da085a CM	1	/*
	2	* linux/arch/arm/mach-versatile/pci.c
	3	*
	4	* (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
	5	* You can redistribute and/or modify this software under the terms of version 2
	6	* of the GNU General Public License as published by the Free Software Foundation.
	7	* THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
	8	* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	9	* General Public License for more details.
	10	* Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
	11	*
	12	* ARM Versatile PCI driver.
	13	*
	14	* 14/04/2005 Initial version, colin.king@philips.com
	15	*
	16	*/
c0da085a CM	17	#include <linux/kernel.h>
	18	#include <linux/pci.h>
	19	#include <linux/ptrace.h>
	20	#include <linux/slab.h>
	21	#include <linux/ioport.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/init.h>
	25
	26	#include <asm/hardware.h>
	27	#include <asm/io.h>
	28	#include <asm/irq.h>
	29	#include <asm/system.h>
	30	#include <asm/mach/pci.h>
c0da085a CM	31
	32	/*
	33	* these spaces are mapped using the following base registers:
	34	*
	35	* Usage Local Bus Memory Base/Map registers used
	36	*
	37	* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
	38	* Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
	39	* IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
	40	* Cfg 42000000 - 42FFFFFF PCI config
	41	*
	42	*/
	43	#define SYS_PCICTL IO_ADDRESS(VERSATILE_SYS_PCICTL)
	44	#define PCI_IMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
	45	#define PCI_IMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
	46	#define PCI_IMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
	47	#define PCI_SMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
	48	#define PCI_SMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
	49	#define PCI_SMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
	50	#define PCI_SELFID IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
	51
	52	#define DEVICE_ID_OFFSET 0x00
	53	#define CSR_OFFSET 0x04
	54	#define CLASS_ID_OFFSET 0x08
	55
	56	#define VP_PCI_DEVICE_ID 0x030010ee
	57	#define VP_PCI_CLASS_ID 0x0b400000
	58
	59	static unsigned long pci_slot_ignore = 0;
	60
	61	static int __init versatile_pci_slot_ignore(char *str)
	62	{
	63	int retval;
	64	int slot;
	65
	66	while ((retval = get_option(&str,&slot))) {
	67	if ((slot < 0) \|\| (slot > 31)) {
	68	printk("Illegal slot value: %d\n",slot);
	69	} else {
	70	pci_slot_ignore \|= (1 << slot);
	71	}
	72	}
	73	return 1;
	74	}
	75
	76	__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
	77
	78
	79	static unsigned long __pci_addr(struct pci_bus *bus,
	80	unsigned int devfn, int offset)
	81	{
	82	unsigned int busnr = bus->number;
	83
	84	/*
	85	* Trap out illegal values
	86	*/
	87	if (offset > 255)
	88	BUG();
	89	if (busnr > 255)
	90	BUG();
	91	if (devfn > 255)
	92	BUG();
	93
	94	return (VERSATILE_PCI_CFG_VIRT_BASE \| (busnr << 16) \|
95	(PCI_SLOT(devfn) << 11) \| (PCI_FUNC(devfn) << 8) \| offset);
96	}
97
98	static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
99	int size, u32 *val)
100	{
101	unsigned long addr = __pci_addr(bus, devfn, where);
102	u32 v;
103	int slot = PCI_SLOT(devfn);
104
105	if (pci_slot_ignore & (1 << slot)) {
106	/* Ignore this slot */
107	switch (size) {
108	case 1:
109	v = 0xff;
110	break;
111	case 2:
112	v = 0xffff;
113	break;
114	default:
115	v = 0xffffffff;
116	}
117	} else {
118	switch (size) {
119	case 1:
c0da085a CM	120	v = __raw_readb(addr);
	121	break;
	122
	123	case 2:
	124	v = __raw_readl(addr & ~3);
	125	if (addr & 2) v >>= 16;
	126	v &= 0xffff;
	127	break;
	128
	129	default:
	130	addr &= ~3;
	131	v = __raw_readl(addr);
	132	break;
	133	}
	134	}
	135
	136	*val = v;
	137	return PCIBIOS_SUCCESSFUL;
	138	}
	139
	140	static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
	141	int size, u32 val)
	142	{
	143	unsigned long addr = __pci_addr(bus, devfn, where);
	144	int slot = PCI_SLOT(devfn);
	145
	146	if (pci_slot_ignore & (1 << slot)) {
	147	return PCIBIOS_SUCCESSFUL;
	148	}
	149
	150	switch (size) {
	151	case 1:
	152	__raw_writeb((u8)val, addr);
	153	break;
	154
	155	case 2:
	156	__raw_writew((u16)val, addr);
	157	break;
	158
	159	case 4:
	160	__raw_writel(val, addr);
	161	break;
	162	}
	163
	164	return PCIBIOS_SUCCESSFUL;
	165	}
	166
	167	static struct pci_ops pci_versatile_ops = {
	168	.read = versatile_read_config,
	169	.write = versatile_write_config,
	170	};
	171
	172	static struct resource io_mem = {
	173	.name = "PCI I/O space",
	174	.start = VERSATILE_PCI_MEM_BASE0,
	175	.end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
	176	.flags = IORESOURCE_IO,
	177	};
	178
	179	static struct resource non_mem = {
	180	.name = "PCI non-prefetchable",
	181	.start = VERSATILE_PCI_MEM_BASE1,
	182	.end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
	183	.flags = IORESOURCE_MEM,
184	};
185
186	static struct resource pre_mem = {
187	.name = "PCI prefetchable",
188	.start = VERSATILE_PCI_MEM_BASE2,
189	.end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
190	.flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH,
191	};
192
193	static int __init pci_versatile_setup_resources(struct resource **resource)
194	{
195	int ret = 0;
196
197	ret = request_resource(&iomem_resource, &io_mem);
198	if (ret) {
199	printk(KERN_ERR "PCI: unable to allocate I/O "
200	"memory region (%d)\n", ret);
201	goto out;
202	}
203	ret = request_resource(&iomem_resource, &non_mem);
204	if (ret) {
205	printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
206	"memory region (%d)\n", ret);
207	goto release_io_mem;
208	}
209	ret = request_resource(&iomem_resource, &pre_mem);
210	if (ret) {
211	printk(KERN_ERR "PCI: unable to allocate prefetchable "
212	"memory region (%d)\n", ret);
213	goto release_non_mem;
214	}
215
216	/*
217	* bus->resource[0] is the IO resource for this bus
218	* bus->resource[1] is the mem resource for this bus
219	* bus->resource[2] is the prefetch mem resource for this bus
220	*/
221	resource[0] = &io_mem;
222	resource[1] = &non_mem;
223	resource[2] = &pre_mem;
224
225	goto out;
226
227	release_non_mem:
228	release_resource(&non_mem);
229	release_io_mem:
230	release_resource(&io_mem);
231	out:
232	return ret;
233	}
234
235	int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
236	{
237	int ret = 0;
238	int i;
239	int myslot = -1;
240	unsigned long val;
c27a2164 CM	241	void __iomem *local_pci_cfg_base;
	242
	243	val = __raw_readl(SYS_PCICTL);
	244	if (!(val & 1)) {
	245	printk("Not plugged into PCI backplane!\n");
	246	ret = -EIO;
	247	goto out;
	248	}
c0da085a CM	249
	250	if (nr == 0) {
	251	sys->mem_offset = 0;
	252	ret = pci_versatile_setup_resources(sys->resource);
	253	if (ret < 0) {
	254	printk("pci_versatile_setup: resources... oops?\n");
	255	goto out;
	256	}
	257	} else {
	258	printk("pci_versatile_setup: resources... nr == 0??\n");
	259	goto out;
	260	}
	261
c0da085a CM	262	/*
	263	* We need to discover the PCI core first to configure itself
	264	* before the main PCI probing is performed
	265	*/
c27a2164	266	for (i=0; i<32; i++)
c0da085a CM	267	if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
	268	(__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
	269	myslot = i;
c0da085a CM	270	break;
c0da085a CM	271	}
c0da085a CM	272
	273	if (myslot == -1) {
	274	printk("Cannot find PCI core!\n");
	275	ret = -EIO;
c27a2164	276	goto out;
c0da085a CM	277	}
c0da085a CM	278
c27a2164 CM	279	printk("PCI core found (slot %d)\n",myslot);
	280
	281	__raw_writel(myslot, PCI_SELFID);
	282	local_pci_cfg_base = (void *) VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
	283
	284	val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
	285	val \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \| PCI_COMMAND_INVALIDATE;
	286	__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
	287
	288	/*
	289	* Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	290	*/
	291	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	292	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	293	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
	294
	295	/*
	296	* Do not to map Versatile FPGA PCI device into memory space
	297	*/
	298	pci_slot_ignore \|= (1 << myslot);
	299	ret = 1;
	300
c0da085a CM	301	out:
	302	return ret;
	303	}
	304
	305
	306	struct pci_bus pci_versatile_scan_bus(int nr, struct pci_sys_data sys)
	307	{
	308	return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
	309	}
	310
c0da085a CM	311	void __init pci_versatile_preinit(void)
c0da085a CM	312	{
c27a2164 CM	313	__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
	314	__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
	315	__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
c0da085a	316
c27a2164 CM	317	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
	318	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
	319	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
c0da085a	320
c27a2164 CM	321	__raw_writel(1, SYS_PCICTL);
c27a2164 CM	322	}
c0da085a CM	323
	324	/*
	325	* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
	326	*/
	327	static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	328	{
	329	int irq;
	330	int devslot = PCI_SLOT(dev->devfn);
	331
c27a2164 CM	332	/* slot, pin, irq
	333	* 24 1 27
	334	* 25 1 28
	335	* 26 1 29
	336	* 27 1 30
	337	*/
	338	irq = 27 + ((slot + pin - 1) & 3);
c0da085a	339
c27a2164	340	printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
c0da085a CM	341
	342	return irq;
	343	}
	344
	345	static struct hw_pci versatile_pci __initdata = {
	346	.swizzle = NULL,
	347	.map_irq = versatile_map_irq,
	348	.nr_controllers = 1,
	349	.setup = pci_versatile_setup,
	350	.scan = pci_versatile_scan_bus,
	351	.preinit = pci_versatile_preinit,
c0da085a CM	352	};
	353
	354	static int __init versatile_pci_init(void)
	355	{
	356	pci_common_init(&versatile_pci);
	357	return 0;
	358	}
	359
	360	subsys_initcall(versatile_pci_init);