[deliverable/linux.git] / arch / arm / mach-vexpress / ct-ca9x4.c

/*
 * Versatile Express Core Tile Cortex A9x4 Support
 */
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>

#include <asm/clkdev.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>

#include <mach/clkdev.h>
#include <mach/ct-ca9x4.h>

#include <plat/timer-sp.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "core.h"

#include <mach/motherboard.h>

#define V2M_PA_CS7	0x10000000

static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	{
		.virtual	= __MMIO_P2V(CT_CA9X4_MPIC),
		.pfn		= __phys_to_pfn(CT_CA9X4_MPIC),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
		.pfn		= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_L2CC),
		.pfn		= __phys_to_pfn(CT_CA9X4_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static void __init ct_ca9x4_map_io(void)
{
	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}

void __iomem *gic_cpu_base_addr;

static void __init ct_ca9x4_init_irq(void)
{
	gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
	gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
	gic_cpu_init(0, gic_cpu_base_addr);
}

#if 0
static void ct_ca9x4_timer_init(void)
{
	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);

	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
}

static struct sys_timer ct_ca9x4_timer = {
	.init	= ct_ca9x4_timer_init,
};
#endif

static struct clcd_panel xvga_panel = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15384,
		.left_margin	= 168,
		.right_margin	= 8,
		.upper_margin	= 29,
		.lower_margin	= 3,
		.hsync_len	= 144,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
}

static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize = 1024 * 768 * 2;
	dma_addr_t dma;

	fb->panel = &xvga_panel;

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
				&dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map frame buffer\n");
		return -ENOMEM;
	}
	fb->fb.fix.smem_start = dma;
	fb->fb.fix.smem_len = framesize;

	return 0;
}

static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
		fb->fb.fix.smem_start, fb->fb.fix.smem_len);
}

static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
		fb->fb.screen_base, fb->fb.fix.smem_start);
}

static struct clcd_board ct_ca9x4_clcd_data = {
	.name		= "CT-CA9X4",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= ct_ca9x4_clcd_enable,
	.setup		= ct_ca9x4_clcd_setup,
	.mmap		= ct_ca9x4_clcd_mmap,
	.remove		= ct_ca9x4_clcd_remove,
};

static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);

static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
	&clcd_device,
	&dmc_device,
	&smc_device,
	&gpio_device,
};


static long ct_round(struct clk *clk, unsigned long rate)
{
	return rate;
}

static int ct_set(struct clk *clk, unsigned long rate)
{
	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
}

static const struct clk_ops osc1_clk_ops = {
	.round	= ct_round,
	.set	= ct_set,
};

static struct clk osc1_clk = {
	.ops	= &osc1_clk_ops,
	.rate	= 24000000,
};

static struct clk_lookup lookups[] = {
	{	/* CLCD */
		.dev_id		= "ct:clcd",
		.clk		= &osc1_clk,
	},
};

static struct resource pmu_resources[] = {
	[0] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU0,
		.end	= IRQ_CT_CA9X4_PMU_CPU0,
		.flags	= IORESOURCE_IRQ,
	},
	[1] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU1,
		.end	= IRQ_CT_CA9X4_PMU_CPU1,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU2,
		.end	= IRQ_CT_CA9X4_PMU_CPU2,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU3,
		.end	= IRQ_CT_CA9X4_PMU_CPU3,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device pmu_device = {
	.name		= "arm-pmu",
	.id		= ARM_PMU_DEVICE_CPU,
	.num_resources	= ARRAY_SIZE(pmu_resources),
	.resource	= pmu_resources,
};

static void ct_ca9x4_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
#endif

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);

	platform_device_register(&pmu_device);
}

MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
	.phys_io	= V2M_UART0,
	.io_pg_offst	= (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
	.boot_params	= PHYS_OFFSET + 0x00000100,
	.map_io		= ct_ca9x4_map_io,
	.init_irq	= ct_ca9x4_init_irq,
#if 0
	.timer		= &ct_ca9x4_timer,
#else
	.timer		= &v2m_timer,
#endif
	.init_machine	= ct_ca9x4_init,
MACHINE_END
Commit	Line	Data
fef88f10 RK	1	/*
	2	* Versatile Express Core Tile Cortex A9x4 Support
	3	*/
	4	#include <linux/init.h>
	5	#include <linux/device.h>
	6	#include <linux/dma-mapping.h>
f417cbad	7	#include <linux/platform_device.h>
fef88f10 RK	8	#include <linux/amba/bus.h>
	9	#include <linux/amba/clcd.h>
	10
	11	#include <asm/clkdev.h>
	12	#include <asm/hardware/arm_timer.h>
	13	#include <asm/hardware/cache-l2x0.h>
	14	#include <asm/hardware/gic.h>
	15	#include <asm/mach-types.h>
f417cbad	16	#include <asm/pmu.h>
fef88f10 RK	17
	18	#include <mach/clkdev.h>
	19	#include <mach/ct-ca9x4.h>
	20
	21	#include <plat/timer-sp.h>
	22
	23	#include <asm/mach/arch.h>
	24	#include <asm/mach/map.h>
	25	#include <asm/mach/time.h>
	26
	27	#include "core.h"
	28
	29	#include <mach/motherboard.h>
	30
	31	#define V2M_PA_CS7 0x10000000
	32
	33	static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	34	{
	35	.virtual = __MMIO_P2V(CT_CA9X4_MPIC),
	36	.pfn = __phys_to_pfn(CT_CA9X4_MPIC),
	37	.length = SZ_16K,
	38	.type = MT_DEVICE,
	39	}, {
	40	.virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
	41	.pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
	42	.length = SZ_4K,
	43	.type = MT_DEVICE,
	44	}, {
	45	.virtual = __MMIO_P2V(CT_CA9X4_L2CC),
	46	.pfn = __phys_to_pfn(CT_CA9X4_L2CC),
	47	.length = SZ_4K,
	48	.type = MT_DEVICE,
	49	},
	50	};
	51
	52	static void __init ct_ca9x4_map_io(void)
	53	{
	54	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
	55	}
	56
	57	void __iomem *gic_cpu_base_addr;
	58
	59	static void __init ct_ca9x4_init_irq(void)
	60	{
	61	gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
	62	gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
	63	gic_cpu_init(0, gic_cpu_base_addr);
	64	}
	65
	66	#if 0
	67	static void ct_ca9x4_timer_init(void)
	68	{
	69	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	70	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
	71
	72	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	73	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
	74	}
	75
	76	static struct sys_timer ct_ca9x4_timer = {
	77	.init = ct_ca9x4_timer_init,
	78	};
	79	#endif
	80
81	static struct clcd_panel xvga_panel = {
82	.mode = {
83	.name = "XVGA",
84	.refresh = 60,
85	.xres = 1024,
86	.yres = 768,
87	.pixclock = 15384,
88	.left_margin = 168,
89	.right_margin = 8,
90	.upper_margin = 29,
91	.lower_margin = 3,
92	.hsync_len = 144,
93	.vsync_len = 6,
94	.sync = 0,
95	.vmode = FB_VMODE_NONINTERLACED,
96	},
97	.width = -1,
98	.height = -1,
99	.tim2 = TIM2_BCD \| TIM2_IPC,
100	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
101	.bpp = 16,
102	};
103
104	static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
105	{
106	v2m_cfg_write(SYS_CFG_MUXFPGA \| SYS_CFG_SITE_DB1, 0);
107	v2m_cfg_write(SYS_CFG_DVIMODE \| SYS_CFG_SITE_DB1, 2);
108	}
109
110	static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
111	{
112	unsigned long framesize = 1024 * 768 * 2;
113	dma_addr_t dma;
114
115	fb->panel = &xvga_panel;
116
117	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
118	&dma, GFP_KERNEL);
119	if (!fb->fb.screen_base) {
120	printk(KERN_ERR "CLCD: unable to map frame buffer\n");
121	return -ENOMEM;
122	}
123	fb->fb.fix.smem_start = dma;
124	fb->fb.fix.smem_len = framesize;
125
126	return 0;
127	}
128
129	static int ct_ca9x4_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
130	{
131	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
132	fb->fb.fix.smem_start, fb->fb.fix.smem_len);
133	}
134
135	static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
136	{
137	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
138	fb->fb.screen_base, fb->fb.fix.smem_start);
139	}
140
141	static struct clcd_board ct_ca9x4_clcd_data = {
142	.name = "CT-CA9X4",
143	.check = clcdfb_check,
144	.decode = clcdfb_decode,
145	.enable = ct_ca9x4_clcd_enable,
146	.setup = ct_ca9x4_clcd_setup,
147	.mmap = ct_ca9x4_clcd_mmap,
148	.remove = ct_ca9x4_clcd_remove,
149	};
150
151	static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
152	static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
153	static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
154	static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
155
156	static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
157	&clcd_device,
158	&dmc_device,
159	&smc_device,
160	&gpio_device,
161	};
162
163
164	static long ct_round(struct clk *clk, unsigned long rate)
165	{
166	return rate;
167	}
168
169	static int ct_set(struct clk *clk, unsigned long rate)
170	{
171	return v2m_cfg_write(SYS_CFG_OSC \| SYS_CFG_SITE_DB1 \| 1, rate);
172	}
173
174	static const struct clk_ops osc1_clk_ops = {
175	.round = ct_round,
176	.set = ct_set,
177	};
178
179	static struct clk osc1_clk = {
180	.ops = &osc1_clk_ops,
181	.rate = 24000000,
182	};
183
184	static struct clk_lookup lookups[] = {
185	{ /* CLCD */
186	.dev_id = "ct:clcd",
187	.clk = &osc1_clk,
188	},
189	};
190
f417cbad WD	191	static struct resource pmu_resources[] = {
	192	[0] = {
	193	.start = IRQ_CT_CA9X4_PMU_CPU0,
	194	.end = IRQ_CT_CA9X4_PMU_CPU0,
	195	.flags = IORESOURCE_IRQ,
	196	},
	197	[1] = {
	198	.start = IRQ_CT_CA9X4_PMU_CPU1,
	199	.end = IRQ_CT_CA9X4_PMU_CPU1,
	200	.flags = IORESOURCE_IRQ,
	201	},
	202	[2] = {
	203	.start = IRQ_CT_CA9X4_PMU_CPU2,
	204	.end = IRQ_CT_CA9X4_PMU_CPU2,
	205	.flags = IORESOURCE_IRQ,
	206	},
	207	[3] = {
	208	.start = IRQ_CT_CA9X4_PMU_CPU3,
	209	.end = IRQ_CT_CA9X4_PMU_CPU3,
	210	.flags = IORESOURCE_IRQ,
	211	},
	212	};
	213
	214	static struct platform_device pmu_device = {
	215	.name = "arm-pmu",
	216	.id = ARM_PMU_DEVICE_CPU,
	217	.num_resources = ARRAY_SIZE(pmu_resources),
	218	.resource = pmu_resources,
	219	};
	220
fef88f10 RK	221	static void ct_ca9x4_init(void)
	222	{
	223	int i;
	224
	225	#ifdef CONFIG_CACHE_L2X0
	226	l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
	227	#endif
	228
	229	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	230
	231	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
	232	amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
f417cbad WD	233
f417cbad WD	234	platform_device_register(&pmu_device);
fef88f10 RK	235	}
	236
	237	MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
	238	.phys_io = V2M_UART0,
	239	.io_pg_offst = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
	240	.boot_params = PHYS_OFFSET + 0x00000100,
	241	.map_io = ct_ca9x4_map_io,
	242	.init_irq = ct_ca9x4_init_irq,
	243	#if 0
	244	.timer = &ct_ca9x4_timer,
	245	#else
	246	.timer = &v2m_timer,
	247	#endif
	248	.init_machine = ct_ca9x4_init,
	249	MACHINE_END