projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
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1 | #ifndef __MACH_CT_CA9X4_H |
| 2 | #define __MACH_CT_CA9X4_H | |
| 3 | ||
| 4 | /* | |
| 5 | * Physical base addresses | |
| 6 | */ | |
| 7 | #define CT_CA9X4_CLCDC (0x10020000) | |
| 8 | #define CT_CA9X4_AXIRAM (0x10060000) | |
| 9 | #define CT_CA9X4_DMC (0x100e0000) | |
| 10 | #define CT_CA9X4_SMC (0x100e1000) | |
| 11 | #define CT_CA9X4_SCC (0x100e2000) | |
| 12 | #define CT_CA9X4_SP804_TIMER (0x100e4000) | |
| 13 | #define CT_CA9X4_SP805_WDT (0x100e5000) | |
| 14 | #define CT_CA9X4_TZPC (0x100e6000) | |
| 15 | #define CT_CA9X4_GPIO (0x100e8000) | |
| 16 | #define CT_CA9X4_FASTAXI (0x100e9000) | |
| 17 | #define CT_CA9X4_SLOWAXI (0x100ea000) | |
| 18 | #define CT_CA9X4_TZASC (0x100ec000) | |
| 19 | #define CT_CA9X4_CORESIGHT (0x10200000) | |
| 20 | #define CT_CA9X4_MPIC (0x1e000000) | |
| 21 | #define CT_CA9X4_SYSTIMER (0x1e004000) | |
| 22 | #define CT_CA9X4_SYSWDT (0x1e007000) | |
| 23 | #define CT_CA9X4_L2CC (0x1e00a000) | |
| 24 | ||
| 25 | #define CT_CA9X4_TIMER0 (CT_CA9X4_SP804_TIMER + 0x000) | |
| 26 | #define CT_CA9X4_TIMER1 (CT_CA9X4_SP804_TIMER + 0x020) | |
| 27 | ||
| 28 | #define A9_MPCORE_SCU (CT_CA9X4_MPIC + 0x0000) | |
| 29 | #define A9_MPCORE_GIC_CPU (CT_CA9X4_MPIC + 0x0100) | |
| 30 | #define A9_MPCORE_GIT (CT_CA9X4_MPIC + 0x0200) | |
| bde28b84 | 31 | #define A9_MPCORE_TWD (CT_CA9X4_MPIC + 0x0600) |
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32 | #define A9_MPCORE_GIC_DIST (CT_CA9X4_MPIC + 0x1000) |
| 33 | ||
| 34 | /* | |
| 35 | * Interrupts. Those in {} are for AMBA devices | |
| 36 | */ | |
| 37 | #define IRQ_CT_CA9X4_CLCDC { 76 } | |
| 38 | #define IRQ_CT_CA9X4_DMC { -1 } | |
| 39 | #define IRQ_CT_CA9X4_SMC { 77, 78 } | |
| 40 | #define IRQ_CT_CA9X4_TIMER0 80 | |
| 41 | #define IRQ_CT_CA9X4_TIMER1 81 | |
| 42 | #define IRQ_CT_CA9X4_GPIO { 82 } | |
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43 | #define IRQ_CT_CA9X4_PMU_CPU0 92 |
| 44 | #define IRQ_CT_CA9X4_PMU_CPU1 93 | |
| 45 | #define IRQ_CT_CA9X4_PMU_CPU2 94 | |
| 46 | #define IRQ_CT_CA9X4_PMU_CPU3 95 | |
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47 | |
| 48 | #endif |