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59ac59f6 RK |
1 | /* |
2 | * linux/arch/arm/mach-vexpress/platsmp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/io.h> | |
18 | ||
19 | #include <asm/cacheflush.h> | |
59ac59f6 RK |
20 | #include <asm/smp_scu.h> |
21 | #include <asm/unified.h> | |
22 | ||
23 | #include <mach/ct-ca9x4.h> | |
24 | #include <mach/motherboard.h> | |
25 | #define V2M_PA_CS7 0x10000000 | |
26 | ||
27 | #include "core.h" | |
28 | ||
29 | extern void vexpress_secondary_startup(void); | |
30 | ||
31 | /* | |
32 | * control for which core is the next to come out of the secondary | |
33 | * boot "holding pen" | |
34 | */ | |
35 | volatile int __cpuinitdata pen_release = -1; | |
36 | ||
37 | static void __iomem *scu_base_addr(void) | |
38 | { | |
39 | return MMIO_P2V(A9_MPCORE_SCU); | |
40 | } | |
41 | ||
42 | static DEFINE_SPINLOCK(boot_lock); | |
43 | ||
44 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
45 | { | |
46 | trace_hardirqs_off(); | |
47 | ||
48 | /* | |
49 | * if any interrupts are already enabled for the primary | |
50 | * core (e.g. timer irq), then they will not have been enabled | |
51 | * for us: do so | |
52 | */ | |
53 | gic_cpu_init(0, gic_cpu_base_addr); | |
54 | ||
55 | /* | |
56 | * let the primary processor know we're out of the | |
57 | * pen, then head off into the C entry point | |
58 | */ | |
59 | pen_release = -1; | |
60 | smp_wmb(); | |
61 | ||
62 | /* | |
63 | * Synchronise with the boot thread. | |
64 | */ | |
65 | spin_lock(&boot_lock); | |
66 | spin_unlock(&boot_lock); | |
67 | } | |
68 | ||
69 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
70 | { | |
71 | unsigned long timeout; | |
72 | ||
73 | /* | |
74 | * Set synchronisation state between this boot processor | |
75 | * and the secondary one | |
76 | */ | |
77 | spin_lock(&boot_lock); | |
78 | ||
79 | /* | |
80 | * This is really belt and braces; we hold unintended secondary | |
81 | * CPUs in the holding pen until we're ready for them. However, | |
82 | * since we haven't sent them a soft interrupt, they shouldn't | |
83 | * be there. | |
84 | */ | |
85 | pen_release = cpu; | |
86 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
87 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
88 | ||
89 | /* | |
90 | * Send the secondary CPU a soft interrupt, thereby causing | |
91 | * the boot monitor to read the system wide flags register, | |
92 | * and branch to the address found there. | |
93 | */ | |
ad3b6993 | 94 | smp_cross_call(cpumask_of(cpu), 1); |
59ac59f6 RK |
95 | |
96 | timeout = jiffies + (1 * HZ); | |
97 | while (time_before(jiffies, timeout)) { | |
98 | smp_rmb(); | |
99 | if (pen_release == -1) | |
100 | break; | |
101 | ||
102 | udelay(10); | |
103 | } | |
104 | ||
105 | /* | |
106 | * now the secondary core is starting up let it run its | |
107 | * calibrations, then wait for it to finish | |
108 | */ | |
109 | spin_unlock(&boot_lock); | |
110 | ||
111 | return pen_release != -1 ? -ENOSYS : 0; | |
112 | } | |
113 | ||
114 | /* | |
115 | * Initialise the CPU possible map early - this describes the CPUs | |
116 | * which may be present or become present in the system. | |
117 | */ | |
118 | void __init smp_init_cpus(void) | |
119 | { | |
120 | void __iomem *scu_base = scu_base_addr(); | |
121 | unsigned int i, ncores; | |
122 | ||
123 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | |
124 | ||
125 | /* sanity check */ | |
59ac59f6 RK |
126 | if (ncores > NR_CPUS) { |
127 | printk(KERN_WARNING | |
128 | "vexpress: no. of cores (%d) greater than configured " | |
129 | "maximum of %d - clipping\n", | |
130 | ncores, NR_CPUS); | |
131 | ncores = NR_CPUS; | |
132 | } | |
133 | ||
134 | for (i = 0; i < ncores; i++) | |
135 | set_cpu_possible(i, true); | |
136 | } | |
137 | ||
05c74a6c | 138 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
59ac59f6 | 139 | { |
59ac59f6 RK |
140 | int i; |
141 | ||
59ac59f6 RK |
142 | /* |
143 | * Initialise the present map, which describes the set of CPUs | |
144 | * actually populated at the present time. | |
145 | */ | |
146 | for (i = 0; i < max_cpus; i++) | |
147 | set_cpu_present(i, true); | |
148 | ||
05c74a6c RK |
149 | scu_enable(scu_base_addr()); |
150 | ||
59ac59f6 | 151 | /* |
05c74a6c RK |
152 | * Write the address of secondary startup into the |
153 | * system-wide flags register. The boot monitor waits | |
154 | * until it receives a soft interrupt, and then the | |
155 | * secondary CPU branches to this address. | |
59ac59f6 | 156 | */ |
05c74a6c RK |
157 | writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); |
158 | writel(BSYM(virt_to_phys(vexpress_secondary_startup)), | |
159 | MMIO_P2V(V2M_SYS_FLAGSSET)); | |
59ac59f6 | 160 | } |