[deliverable/linux.git] / arch / arm / mach-vexpress / v2m.c

/*
 * Versatile Express V2M Motherboard Support
 */
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/smsc911x.h>
#include <linux/spinlock.h>
#include <linux/usb/isp1760.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/mtd/physmap.h>

#include <asm/arch_timer.h>
#include <asm/mach-types.h>
#include <asm/sizes.h>
#include <asm/smp_twd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/timer-sp.h>
#include <asm/hardware/sp810.h>

#include <mach/ct-ca9x4.h>
#include <mach/motherboard.h>

#include <plat/sched_clock.h>

#include "core.h"

#define V2M_PA_CS0	0x40000000
#define V2M_PA_CS1	0x44000000
#define V2M_PA_CS2	0x48000000
#define V2M_PA_CS3	0x4c000000
#define V2M_PA_CS7	0x10000000

static struct map_desc v2m_io_desc[] __initdata = {
	{
		.virtual	= V2M_PERIPH,
		.pfn		= __phys_to_pfn(V2M_PA_CS7),
		.length		= SZ_128K,
		.type		= MT_DEVICE,
	},
};

static void __iomem *v2m_sysreg_base;

static void __init v2m_sysctl_init(void __iomem *base)
{
	u32 scctrl;

	if (WARN_ON(!base))
		return;

	/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
	scctrl = readl(base + SCCTRL);
	scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
	scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
	writel(scctrl, base + SCCTRL);
}

static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
{
	if (WARN_ON(!base || irq == NO_IRQ))
		return;

	writel(0, base + TIMER_1_BASE + TIMER_CTRL);
	writel(0, base + TIMER_2_BASE + TIMER_CTRL);

	sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
	sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
}


static DEFINE_SPINLOCK(v2m_cfg_lock);

int v2m_cfg_write(u32 devfn, u32 data)
{
	/* Configuration interface broken? */
	u32 val;

	printk("%s: writing %08x to %08x\n", __func__, data, devfn);

	devfn |= SYS_CFG_START | SYS_CFG_WRITE;

	spin_lock(&v2m_cfg_lock);
	val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
	writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);

	writel(data, v2m_sysreg_base +  V2M_SYS_CFGDATA);
	writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);

	do {
		val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
	} while (val == 0);
	spin_unlock(&v2m_cfg_lock);

	return !!(val & SYS_CFG_ERR);
}

int v2m_cfg_read(u32 devfn, u32 *data)
{
	u32 val;

	devfn |= SYS_CFG_START;

	spin_lock(&v2m_cfg_lock);
	writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
	writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);

	mb();

	do {
		cpu_relax();
		val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
	} while (val == 0);

	*data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
	spin_unlock(&v2m_cfg_lock);

	return !!(val & SYS_CFG_ERR);
}

void __init v2m_flags_set(u32 data)
{
	writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
	writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
}

int v2m_get_master_site(void)
{
	u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);

	return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
}


static struct resource v2m_pcie_i2c_resource = {
	.start	= V2M_SERIAL_BUS_PCI,
	.end	= V2M_SERIAL_BUS_PCI + SZ_4K - 1,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device v2m_pcie_i2c_device = {
	.name		= "versatile-i2c",
	.id		= 0,
	.num_resources	= 1,
	.resource	= &v2m_pcie_i2c_resource,
};

static struct resource v2m_ddc_i2c_resource = {
	.start	= V2M_SERIAL_BUS_DVI,
	.end	= V2M_SERIAL_BUS_DVI + SZ_4K - 1,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device v2m_ddc_i2c_device = {
	.name		= "versatile-i2c",
	.id		= 1,
	.num_resources	= 1,
	.resource	= &v2m_ddc_i2c_resource,
};

static struct resource v2m_eth_resources[] = {
	{
		.start	= V2M_LAN9118,
		.end	= V2M_LAN9118 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_V2M_LAN9118,
		.end	= IRQ_V2M_LAN9118,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct smsc911x_platform_config v2m_eth_config = {
	.flags		= SMSC911X_USE_32BIT,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct platform_device v2m_eth_device = {
	.name		= "smsc911x",
	.id		= -1,
	.resource	= v2m_eth_resources,
	.num_resources	= ARRAY_SIZE(v2m_eth_resources),
	.dev.platform_data = &v2m_eth_config,
};

static struct resource v2m_usb_resources[] = {
	{
		.start	= V2M_ISP1761,
		.end	= V2M_ISP1761 + SZ_128K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_V2M_ISP1761,
		.end	= IRQ_V2M_ISP1761,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct isp1760_platform_data v2m_usb_config = {
	.is_isp1761		= true,
	.bus_width_16		= false,
	.port1_otg		= true,
	.analog_oc		= false,
	.dack_polarity_high	= false,
	.dreq_polarity_high	= false,
};

static struct platform_device v2m_usb_device = {
	.name		= "isp1760",
	.id		= -1,
	.resource	= v2m_usb_resources,
	.num_resources	= ARRAY_SIZE(v2m_usb_resources),
	.dev.platform_data = &v2m_usb_config,
};

static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
{
	writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
}

static struct physmap_flash_data v2m_flash_data = {
	.width		= 4,
	.set_vpp	= v2m_flash_set_vpp,
};

static struct resource v2m_flash_resources[] = {
	{
		.start	= V2M_NOR0,
		.end	= V2M_NOR0 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= V2M_NOR1,
		.end	= V2M_NOR1 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device v2m_flash_device = {
	.name		= "physmap-flash",
	.id		= -1,
	.resource	= v2m_flash_resources,
	.num_resources	= ARRAY_SIZE(v2m_flash_resources),
	.dev.platform_data = &v2m_flash_data,
};

static struct pata_platform_info v2m_pata_data = {
	.ioport_shift	= 2,
};

static struct resource v2m_pata_resources[] = {
	{
		.start	= V2M_CF,
		.end	= V2M_CF + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= V2M_CF + 0x100,
		.end	= V2M_CF + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device v2m_cf_device = {
	.name		= "pata_platform",
	.id		= -1,
	.resource	= v2m_pata_resources,
	.num_resources	= ARRAY_SIZE(v2m_pata_resources),
	.dev.platform_data = &v2m_pata_data,
};

static unsigned int v2m_mmci_status(struct device *dev)
{
	return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
}

static struct mmci_platform_data v2m_mmci_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= v2m_mmci_status,
};

static AMBA_APB_DEVICE(aaci,  "mb:aaci",  0, V2M_AACI, IRQ_V2M_AACI, NULL);
static AMBA_APB_DEVICE(mmci,  "mb:mmci",  0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
static AMBA_APB_DEVICE(kmi0,  "mb:kmi0",  0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
static AMBA_APB_DEVICE(kmi1,  "mb:kmi1",  0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
static AMBA_APB_DEVICE(wdt,   "mb:wdt",   0, V2M_WDT, IRQ_V2M_WDT, NULL);
static AMBA_APB_DEVICE(rtc,   "mb:rtc",   0, V2M_RTC, IRQ_V2M_RTC, NULL);

static struct amba_device *v2m_amba_devs[] __initdata = {
	&aaci_device,
	&mmci_device,
	&kmi0_device,
	&kmi1_device,
	&uart0_device,
	&uart1_device,
	&uart2_device,
	&uart3_device,
	&wdt_device,
	&rtc_device,
};


static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct v2m_osc *osc = to_v2m_osc(hw);

	return !parent_rate ? osc->rate_default : parent_rate;
}

static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
{
	struct v2m_osc *osc = to_v2m_osc(hw);

	if (WARN_ON(rate < osc->rate_min))
		rate = osc->rate_min;

	if (WARN_ON(rate > osc->rate_max))
		rate = osc->rate_max;

	return rate;
}

static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct v2m_osc *osc = to_v2m_osc(hw);

	v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
			SYS_CFG_STACK(osc->stack) | osc->osc, rate);

	return 0;
}

static struct clk_ops v2m_osc_ops = {
	.recalc_rate = v2m_osc_recalc_rate,
	.round_rate = v2m_osc_round_rate,
	.set_rate = v2m_osc_set_rate,
};

struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
{
	struct clk_init_data init;

	WARN_ON(osc->site > 2);
	WARN_ON(osc->stack > 15);
	WARN_ON(osc->osc > 4095);

	init.name = name;
	init.ops = &v2m_osc_ops;
	init.flags = CLK_IS_ROOT;
	init.num_parents = 0;

	osc->hw.init = &init;

	return clk_register(NULL, &osc->hw);
}

static struct v2m_osc v2m_mb_osc1 = {
	.site = SYS_CFG_SITE_MB,
	.osc = 1,
	.rate_min = 23750000,
	.rate_max = 63500000,
	.rate_default = 23750000,
};

static const char *v2m_ref_clk_periphs[] __initconst = {
	"mb:wdt",   "1000f000.wdt",  "1c0f0000.wdt",	/* SP805 WDT */
};

static const char *v2m_osc1_periphs[] __initconst = {
	"mb:clcd",  "1001f000.clcd", "1c1f0000.clcd",	/* PL111 CLCD */
};

static const char *v2m_osc2_periphs[] __initconst = {
	"mb:mmci",  "10005000.mmci", "1c050000.mmci",	/* PL180 MMCI */
	"mb:kmi0",  "10006000.kmi",  "1c060000.kmi",	/* PL050 KMI0 */
	"mb:kmi1",  "10007000.kmi",  "1c070000.kmi",	/* PL050 KMI1 */
	"mb:uart0", "10009000.uart", "1c090000.uart",	/* PL011 UART0 */
	"mb:uart1", "1000a000.uart", "1c0a0000.uart",	/* PL011 UART1 */
	"mb:uart2", "1000b000.uart", "1c0b0000.uart",	/* PL011 UART2 */
	"mb:uart3", "1000c000.uart", "1c0c0000.uart",	/* PL011 UART3 */
};

static void __init v2m_clk_init(void)
{
	struct clk *clk;
	int i;

	clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
			CLK_IS_ROOT, 0);
	WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));

	clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
			CLK_IS_ROOT, 32768);
	for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
		WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));

	clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
			CLK_IS_ROOT, 1000000);
	WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
	WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));

	clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
	for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
		WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));

	clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
			CLK_IS_ROOT, 24000000);
	for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
		WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
}

static void __init v2m_timer_init(void)
{
	v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
	v2m_clk_init();
	v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
}

static struct sys_timer v2m_timer = {
	.init	= v2m_timer_init,
};

static void __init v2m_init_early(void)
{
	if (ct_desc->init_early)
		ct_desc->init_early();
	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}

static void v2m_power_off(void)
{
	if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
		printk(KERN_EMERG "Unable to shutdown\n");
}

static void v2m_restart(char str, const char *cmd)
{
	if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
		printk(KERN_EMERG "Unable to reboot\n");
}

struct ct_desc *ct_desc;

static struct ct_desc *ct_descs[] __initdata = {
#ifdef CONFIG_ARCH_VEXPRESS_CA9X4
	&ct_ca9x4_desc,
#endif
};

static void __init v2m_populate_ct_desc(void)
{
	int i;
	u32 current_tile_id;

	ct_desc = NULL;
	current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
				& V2M_CT_ID_MASK;

	for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
		if (ct_descs[i]->id == current_tile_id)
			ct_desc = ct_descs[i];

	if (!ct_desc)
		panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
		      "You may need a device tree blob or a different kernel to boot on this board.\n",
		      current_tile_id);
}

static void __init v2m_map_io(void)
{
	iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
	v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
	v2m_populate_ct_desc();
	ct_desc->map_io();
}

static void __init v2m_init_irq(void)
{
	ct_desc->init_irq();
}

static void __init v2m_init(void)
{
	int i;

	platform_device_register(&v2m_pcie_i2c_device);
	platform_device_register(&v2m_ddc_i2c_device);
	platform_device_register(&v2m_flash_device);
	platform_device_register(&v2m_cf_device);
	platform_device_register(&v2m_eth_device);
	platform_device_register(&v2m_usb_device);

	for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
		amba_device_register(v2m_amba_devs[i], &iomem_resource);

	pm_power_off = v2m_power_off;

	ct_desc->init_tile();
}

MACHINE_START(VEXPRESS, "ARM-Versatile Express")
	.atag_offset	= 0x100,
	.map_io		= v2m_map_io,
	.init_early	= v2m_init_early,
	.init_irq	= v2m_init_irq,
	.timer		= &v2m_timer,
	.handle_irq	= gic_handle_irq,
	.init_machine	= v2m_init,
	.restart	= v2m_restart,
MACHINE_END

#if defined(CONFIG_ARCH_VEXPRESS_DT)

static struct map_desc v2m_rs1_io_desc __initdata = {
	.virtual	= V2M_PERIPH,
	.pfn		= __phys_to_pfn(0x1c000000),
	.length		= SZ_2M,
	.type		= MT_DEVICE,
};

static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
		int depth, void *data)
{
	const char **map = data;

	if (strcmp(uname, "motherboard") != 0)
		return 0;

	*map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);

	return 1;
}

void __init v2m_dt_map_io(void)
{
	const char *map = NULL;

	of_scan_flat_dt(v2m_dt_scan_memory_map, &map);

	if (map && strcmp(map, "rs1") == 0)
		iotable_init(&v2m_rs1_io_desc, 1);
	else
		iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));

#if defined(CONFIG_SMP)
	vexpress_dt_smp_map_io();
#endif
}

void __init v2m_dt_init_early(void)
{
	struct device_node *node;
	u32 dt_hbi;

	node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
	v2m_sysreg_base = of_iomap(node, 0);
	if (WARN_ON(!v2m_sysreg_base))
		return;

	/* Confirm board type against DT property, if available */
	if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
		int site = v2m_get_master_site();
		u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
				V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
		u32 hbi = id & SYS_PROCIDx_HBI_MASK;

		if (WARN_ON(dt_hbi != hbi))
			pr_warning("vexpress: DT HBI (%x) is not matching "
					"hardware (%x)!\n", dt_hbi, hbi);
	}
}

static  struct of_device_id vexpress_irq_match[] __initdata = {
	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	{}
};

static void __init v2m_dt_init_irq(void)
{
	of_irq_init(vexpress_irq_match);
}

static void __init v2m_dt_timer_init(void)
{
	struct device_node *node;
	const char *path;
	int err;

	node = of_find_compatible_node(NULL, NULL, "arm,sp810");
	v2m_sysctl_init(of_iomap(node, 0));

	v2m_clk_init();

	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
	if (WARN_ON(err))
		return;
	node = of_find_node_by_path(path);
	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
	if (arch_timer_of_register() != 0)
		twd_local_timer_of_register();

	if (arch_timer_sched_clock_init() != 0)
		versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}

static struct sys_timer v2m_dt_timer = {
	.init = v2m_dt_timer_init,
};

static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
	OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
			&v2m_flash_data),
	OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
	/* RS1 memory map */
	OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
			&v2m_flash_data),
	OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
	{}
};

static void __init v2m_dt_init(void)
{
	l2x0_of_init(0x00400000, 0xfe0fffff);
	of_platform_populate(NULL, of_default_bus_match_table,
			v2m_dt_auxdata_lookup, NULL);
	pm_power_off = v2m_power_off;
}

const static char *v2m_dt_match[] __initconst = {
	"arm,vexpress",
	NULL,
};

DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
	.dt_compat	= v2m_dt_match,
	.map_io		= v2m_dt_map_io,
	.init_early	= v2m_dt_init_early,
	.init_irq	= v2m_dt_init_irq,
	.timer		= &v2m_dt_timer,
	.init_machine	= v2m_dt_init,
	.handle_irq	= gic_handle_irq,
	.restart	= v2m_restart,
MACHINE_END

#endif
Commit	Line	Data
ceade897 RK	1	/*
	2	* Versatile Express V2M Motherboard Support
	3	*/
	4	#include <linux/device.h>
	5	#include <linux/amba/bus.h>
	6	#include <linux/amba/mmci.h>
	7	#include <linux/io.h>
	8	#include <linux/init.h>
8deed178 PM	9	#include <linux/of_address.h>
	10	#include <linux/of_fdt.h>
	11	#include <linux/of_irq.h>
	12	#include <linux/of_platform.h>
ceade897	13	#include <linux/platform_device.h>
95c34f83	14	#include <linux/ata_platform.h>
ceade897 RK	15	#include <linux/smsc911x.h>
ceade897 RK	16	#include <linux/spinlock.h>
ceade897	17	#include <linux/usb/isp1760.h>
6d803ba7	18	#include <linux/clkdev.h>
d1b8a775	19	#include <linux/clk-provider.h>
0f71fd49	20	#include <linux/mtd/physmap.h>
ceade897	21
120f3d6c	22	#include <asm/arch_timer.h>
80b5efbd	23	#include <asm/mach-types.h>
ceade897	24	#include <asm/sizes.h>
120f3d6c	25	#include <asm/smp_twd.h>
80b5efbd	26	#include <asm/mach/arch.h>
ceade897 RK	27	#include <asm/mach/map.h>
	28	#include <asm/mach/time.h>
	29	#include <asm/hardware/arm_timer.h>
8deed178 PM	30	#include <asm/hardware/cache-l2x0.h>
8deed178 PM	31	#include <asm/hardware/gic.h>
58daf18c	32	#include <asm/hardware/timer-sp.h>
baaece22	33	#include <asm/hardware/sp810.h>
ceade897	34
80b5efbd	35	#include <mach/ct-ca9x4.h>
ceade897 RK	36	#include <mach/motherboard.h>
ceade897 RK	37
0af85dda	38	#include <plat/sched_clock.h>
ceade897 RK	39
	40	#include "core.h"
	41
	42	#define V2M_PA_CS0 0x40000000
	43	#define V2M_PA_CS1 0x44000000
	44	#define V2M_PA_CS2 0x48000000
	45	#define V2M_PA_CS3 0x4c000000
	46	#define V2M_PA_CS7 0x10000000
	47
	48	static struct map_desc v2m_io_desc[] __initdata = {
	49	{
98ed4ceb	50	.virtual = V2M_PERIPH,
ceade897 RK	51	.pfn = __phys_to_pfn(V2M_PA_CS7),
	52	.length = SZ_128K,
	53	.type = MT_DEVICE,
	54	},
	55	};
	56
98ed4ceb PM	57	static void __iomem *v2m_sysreg_base;
	58
	59	static void __init v2m_sysctl_init(void __iomem *base)
ceade897	60	{
baaece22 PM	61	u32 scctrl;
baaece22 PM	62
98ed4ceb PM	63	if (WARN_ON(!base))
	64	return;
	65
baaece22	66	/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
98ed4ceb	67	scctrl = readl(base + SCCTRL);
baaece22 PM	68	scctrl \|= SCCTRL_TIMEREN0SEL_TIMCLK;
baaece22 PM	69	scctrl \|= SCCTRL_TIMEREN1SEL_TIMCLK;
98ed4ceb PM	70	writel(scctrl, base + SCCTRL);
98ed4ceb PM	71	}
baaece22	72
98ed4ceb PM	73	static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
	74	{
	75	if (WARN_ON(!base \|\| irq == NO_IRQ))
	76	return;
	77
	78	writel(0, base + TIMER_1_BASE + TIMER_CTRL);
	79	writel(0, base + TIMER_2_BASE + TIMER_CTRL);
baaece22	80
98ed4ceb PM	81	sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
	82	sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
	83	}
ceade897	84
ceade897 RK	85
	86	static DEFINE_SPINLOCK(v2m_cfg_lock);
	87
	88	int v2m_cfg_write(u32 devfn, u32 data)
	89	{
	90	/* Configuration interface broken? */
	91	u32 val;
	92
	93	printk("%s: writing %08x to %08x\n", __func__, data, devfn);
	94
	95	devfn \|= SYS_CFG_START \| SYS_CFG_WRITE;
	96
	97	spin_lock(&v2m_cfg_lock);
98ed4ceb PM	98	val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
98ed4ceb PM	99	writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
ceade897	100
98ed4ceb PM	101	writel(data, v2m_sysreg_base + V2M_SYS_CFGDATA);
98ed4ceb PM	102	writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
ceade897 RK	103
ceade897 RK	104	do {
98ed4ceb	105	val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
ceade897 RK	106	} while (val == 0);
	107	spin_unlock(&v2m_cfg_lock);
	108
	109	return !!(val & SYS_CFG_ERR);
	110	}
	111
	112	int v2m_cfg_read(u32 devfn, u32 *data)
	113	{
	114	u32 val;
	115
	116	devfn \|= SYS_CFG_START;
	117
	118	spin_lock(&v2m_cfg_lock);
98ed4ceb PM	119	writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
98ed4ceb PM	120	writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
ceade897 RK	121
	122	mb();
	123
	124	do {
	125	cpu_relax();
98ed4ceb	126	val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
ceade897 RK	127	} while (val == 0);
ceade897 RK	128
98ed4ceb	129	*data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
ceade897 RK	130	spin_unlock(&v2m_cfg_lock);
	131
	132	return !!(val & SYS_CFG_ERR);
	133	}
	134
98ed4ceb PM	135	void __init v2m_flags_set(u32 data)
	136	{
	137	writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
	138	writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
	139	}
	140
d927daf5 PM	141	int v2m_get_master_site(void)
	142	{
	143	u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
	144
	145	return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
	146	}
	147
ceade897 RK	148
	149	static struct resource v2m_pcie_i2c_resource = {
	150	.start = V2M_SERIAL_BUS_PCI,
	151	.end = V2M_SERIAL_BUS_PCI + SZ_4K - 1,
	152	.flags = IORESOURCE_MEM,
	153	};
	154
	155	static struct platform_device v2m_pcie_i2c_device = {
	156	.name = "versatile-i2c",
	157	.id = 0,
	158	.num_resources = 1,
	159	.resource = &v2m_pcie_i2c_resource,
	160	};
	161
	162	static struct resource v2m_ddc_i2c_resource = {
	163	.start = V2M_SERIAL_BUS_DVI,
	164	.end = V2M_SERIAL_BUS_DVI + SZ_4K - 1,
	165	.flags = IORESOURCE_MEM,
	166	};
	167
	168	static struct platform_device v2m_ddc_i2c_device = {
	169	.name = "versatile-i2c",
	170	.id = 1,
	171	.num_resources = 1,
	172	.resource = &v2m_ddc_i2c_resource,
	173	};
	174
	175	static struct resource v2m_eth_resources[] = {
	176	{
	177	.start = V2M_LAN9118,
	178	.end = V2M_LAN9118 + SZ_64K - 1,
	179	.flags = IORESOURCE_MEM,
	180	}, {
	181	.start = IRQ_V2M_LAN9118,
	182	.end = IRQ_V2M_LAN9118,
	183	.flags = IORESOURCE_IRQ,
	184	},
	185	};
	186
	187	static struct smsc911x_platform_config v2m_eth_config = {
	188	.flags = SMSC911X_USE_32BIT,
	189	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	190	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	191	.phy_interface = PHY_INTERFACE_MODE_MII,
	192	};
	193
	194	static struct platform_device v2m_eth_device = {
	195	.name = "smsc911x",
	196	.id = -1,
	197	.resource = v2m_eth_resources,
	198	.num_resources = ARRAY_SIZE(v2m_eth_resources),
	199	.dev.platform_data = &v2m_eth_config,
	200	};
	201
	202	static struct resource v2m_usb_resources[] = {
	203	{
	204	.start = V2M_ISP1761,
	205	.end = V2M_ISP1761 + SZ_128K - 1,
	206	.flags = IORESOURCE_MEM,
	207	}, {
	208	.start = IRQ_V2M_ISP1761,
	209	.end = IRQ_V2M_ISP1761,
	210	.flags = IORESOURCE_IRQ,
	211	},
212	};
213
214	static struct isp1760_platform_data v2m_usb_config = {
215	.is_isp1761 = true,
216	.bus_width_16 = false,
217	.port1_otg = true,
218	.analog_oc = false,
219	.dack_polarity_high = false,
220	.dreq_polarity_high = false,
221	};
222
223	static struct platform_device v2m_usb_device = {
224	.name = "isp1760",
225	.id = -1,
226	.resource = v2m_usb_resources,
227	.num_resources = ARRAY_SIZE(v2m_usb_resources),
228	.dev.platform_data = &v2m_usb_config,
229	};
230
667f390b	231	static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
ceade897	232	{
98ed4ceb	233	writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
ceade897 RK	234	}
ceade897 RK	235
0f71fd49	236	static struct physmap_flash_data v2m_flash_data = {
ceade897	237	.width = 4,
ceade897 RK	238	.set_vpp = v2m_flash_set_vpp,
	239	};
	240
	241	static struct resource v2m_flash_resources[] = {
	242	{
	243	.start = V2M_NOR0,
	244	.end = V2M_NOR0 + SZ_64M - 1,
	245	.flags = IORESOURCE_MEM,
	246	}, {
	247	.start = V2M_NOR1,
	248	.end = V2M_NOR1 + SZ_64M - 1,
	249	.flags = IORESOURCE_MEM,
	250	},
	251	};
	252
	253	static struct platform_device v2m_flash_device = {
0f71fd49	254	.name = "physmap-flash",
ceade897 RK	255	.id = -1,
	256	.resource = v2m_flash_resources,
	257	.num_resources = ARRAY_SIZE(v2m_flash_resources),
	258	.dev.platform_data = &v2m_flash_data,
	259	};
	260
95c34f83 NB	261	static struct pata_platform_info v2m_pata_data = {
	262	.ioport_shift = 2,
	263	};
	264
	265	static struct resource v2m_pata_resources[] = {
	266	{
	267	.start = V2M_CF,
	268	.end = V2M_CF + 0xff,
	269	.flags = IORESOURCE_MEM,
	270	}, {
	271	.start = V2M_CF + 0x100,
	272	.end = V2M_CF + SZ_4K - 1,
	273	.flags = IORESOURCE_MEM,
	274	},
	275	};
	276
	277	static struct platform_device v2m_cf_device = {
	278	.name = "pata_platform",
	279	.id = -1,
	280	.resource = v2m_pata_resources,
	281	.num_resources = ARRAY_SIZE(v2m_pata_resources),
	282	.dev.platform_data = &v2m_pata_data,
	283	};
ceade897 RK	284
	285	static unsigned int v2m_mmci_status(struct device *dev)
	286	{
98ed4ceb	287	return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
ceade897 RK	288	}
	289
	290	static struct mmci_platform_data v2m_mmci_data = {
	291	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	292	.status = v2m_mmci_status,
	293	};
	294
cdd4e1a7 RK	295	static AMBA_APB_DEVICE(aaci, "mb:aaci", 0, V2M_AACI, IRQ_V2M_AACI, NULL);
	296	static AMBA_APB_DEVICE(mmci, "mb:mmci", 0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
	297	static AMBA_APB_DEVICE(kmi0, "mb:kmi0", 0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
	298	static AMBA_APB_DEVICE(kmi1, "mb:kmi1", 0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
	299	static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
	300	static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
	301	static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
	302	static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
	303	static AMBA_APB_DEVICE(wdt, "mb:wdt", 0, V2M_WDT, IRQ_V2M_WDT, NULL);
	304	static AMBA_APB_DEVICE(rtc, "mb:rtc", 0, V2M_RTC, IRQ_V2M_RTC, NULL);
ceade897 RK	305
	306	static struct amba_device *v2m_amba_devs[] __initdata = {
	307	&aaci_device,
	308	&mmci_device,
	309	&kmi0_device,
	310	&kmi1_device,
	311	&uart0_device,
	312	&uart1_device,
	313	&uart2_device,
	314	&uart3_device,
	315	&wdt_device,
	316	&rtc_device,
	317	};
	318
	319
d1b8a775 PM	320	static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
d1b8a775 PM	321	unsigned long parent_rate)
ceade897	322	{
d1b8a775 PM	323	struct v2m_osc *osc = to_v2m_osc(hw);
	324
	325	return !parent_rate ? osc->rate_default : parent_rate;
	326	}
	327
	328	static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
	329	unsigned long *parent_rate)
	330	{
	331	struct v2m_osc *osc = to_v2m_osc(hw);
	332
	333	if (WARN_ON(rate < osc->rate_min))
	334	rate = osc->rate_min;
	335
	336	if (WARN_ON(rate > osc->rate_max))
	337	rate = osc->rate_max;
	338
ceade897 RK	339	return rate;
	340	}
	341
d1b8a775 PM	342	static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
d1b8a775 PM	343	unsigned long parent_rate)
ceade897	344	{
d1b8a775 PM	345	struct v2m_osc *osc = to_v2m_osc(hw);
	346
	347	v2m_cfg_write(SYS_CFG_OSC \| SYS_CFG_SITE(osc->site) \|
	348	SYS_CFG_STACK(osc->stack) \| osc->osc, rate);
	349
	350	return 0;
ceade897 RK	351	}
ceade897 RK	352
d1b8a775 PM	353	static struct clk_ops v2m_osc_ops = {
	354	.recalc_rate = v2m_osc_recalc_rate,
	355	.round_rate = v2m_osc_round_rate,
	356	.set_rate = v2m_osc_set_rate,
ceade897 RK	357	};
ceade897 RK	358
d1b8a775 PM	359	struct clk * __init v2m_osc_register(const char name, struct v2m_osc osc)
	360	{
	361	struct clk_init_data init;
	362
	363	WARN_ON(osc->site > 2);
	364	WARN_ON(osc->stack > 15);
	365	WARN_ON(osc->osc > 4095);
	366
	367	init.name = name;
	368	init.ops = &v2m_osc_ops;
	369	init.flags = CLK_IS_ROOT;
	370	init.num_parents = 0;
	371
	372	osc->hw.init = &init;
	373
	374	return clk_register(NULL, &osc->hw);
	375	}
	376
	377	static struct v2m_osc v2m_mb_osc1 = {
	378	.site = SYS_CFG_SITE_MB,
	379	.osc = 1,
	380	.rate_min = 23750000,
	381	.rate_max = 63500000,
	382	.rate_default = 23750000,
ceade897 RK	383	};
ceade897 RK	384
d1b8a775 PM	385	static const char *v2m_ref_clk_periphs[] __initconst = {
d1b8a775 PM	386	"mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */
ceade897 RK	387	};
ceade897 RK	388
d1b8a775 PM	389	static const char *v2m_osc1_periphs[] __initconst = {
d1b8a775 PM	390	"mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */
7ff550de RK	391	};
7ff550de RK	392
d1b8a775 PM	393	static const char *v2m_osc2_periphs[] __initconst = {
	394	"mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */
	395	"mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */
	396	"mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */
	397	"mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */
	398	"mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */
	399	"mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */
	400	"mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */
0ebb962e NB	401	};
0ebb962e NB	402
d1b8a775 PM	403	static void __init v2m_clk_init(void)
	404	{
	405	struct clk *clk;
	406	int i;
	407
	408	clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
	409	CLK_IS_ROOT, 0);
	410	WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
	411
	412	clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
	413	CLK_IS_ROOT, 32768);
	414	for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
	415	WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
	416
	417	clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
	418	CLK_IS_ROOT, 1000000);
	419	WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
	420	WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
	421
	422	clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
	423	for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
	424	WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
	425
	426	clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
	427	CLK_IS_ROOT, 24000000);
	428	for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
	429	WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
	430	}
	431
	432	static void __init v2m_timer_init(void)
	433	{
	434	v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
	435	v2m_clk_init();
	436	v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
	437	}
	438
	439	static struct sys_timer v2m_timer = {
	440	.init = v2m_timer_init,
ceade897 RK	441	};
ceade897 RK	442
2fdf9993 RH	443	static void __init v2m_init_early(void)
2fdf9993 RH	444	{
d1b8a775 PM	445	if (ct_desc->init_early)
d1b8a775 PM	446	ct_desc->init_early();
98ed4ceb	447	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
2fdf9993 RH	448	}
2fdf9993 RH	449
ceade897 RK	450	static void v2m_power_off(void)
ceade897 RK	451	{
d927daf5	452	if (v2m_cfg_write(SYS_CFG_SHUTDOWN \| SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
ceade897 RK	453	printk(KERN_EMERG "Unable to shutdown\n");
	454	}
	455
	456	static void v2m_restart(char str, const char *cmd)
	457	{
d927daf5	458	if (v2m_cfg_write(SYS_CFG_REBOOT \| SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
ceade897 RK	459	printk(KERN_EMERG "Unable to reboot\n");
	460	}
	461
80b5efbd WD	462	struct ct_desc *ct_desc;
	463
	464	static struct ct_desc *ct_descs[] __initdata = {
	465	#ifdef CONFIG_ARCH_VEXPRESS_CA9X4
	466	&ct_ca9x4_desc,
	467	#endif
	468	};
	469
	470	static void __init v2m_populate_ct_desc(void)
	471	{
	472	int i;
	473	u32 current_tile_id;
	474
	475	ct_desc = NULL;
98ed4ceb PM	476	current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
98ed4ceb PM	477	& V2M_CT_ID_MASK;
80b5efbd WD	478
	479	for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
	480	if (ct_descs[i]->id == current_tile_id)
	481	ct_desc = ct_descs[i];
	482
	483	if (!ct_desc)
8deed178 PM	484	panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
	485	"You may need a device tree blob or a different kernel to boot on this board.\n",
	486	current_tile_id);
80b5efbd WD	487	}
	488
	489	static void __init v2m_map_io(void)
	490	{
	491	iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
98ed4ceb	492	v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
80b5efbd WD	493	v2m_populate_ct_desc();
	494	ct_desc->map_io();
	495	}
	496
	497	static void __init v2m_init_irq(void)
	498	{
	499	ct_desc->init_irq();
	500	}
	501
	502	static void __init v2m_init(void)
ceade897 RK	503	{
	504	int i;
	505
ceade897 RK	506	platform_device_register(&v2m_pcie_i2c_device);
	507	platform_device_register(&v2m_ddc_i2c_device);
	508	platform_device_register(&v2m_flash_device);
95c34f83	509	platform_device_register(&v2m_cf_device);
ceade897 RK	510	platform_device_register(&v2m_eth_device);
	511	platform_device_register(&v2m_usb_device);
	512
	513	for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
	514	amba_device_register(v2m_amba_devs[i], &iomem_resource);
	515
	516	pm_power_off = v2m_power_off;
ceade897	517
80b5efbd	518	ct_desc->init_tile();
ceade897	519	}
80b5efbd WD	520
80b5efbd WD	521	MACHINE_START(VEXPRESS, "ARM-Versatile Express")
e9ce8e5b	522	.atag_offset = 0x100,
80b5efbd WD	523	.map_io = v2m_map_io,
	524	.init_early = v2m_init_early,
	525	.init_irq = v2m_init_irq,
	526	.timer = &v2m_timer,
abd3ca51	527	.handle_irq = gic_handle_irq,
80b5efbd	528	.init_machine = v2m_init,
f5733a1e	529	.restart = v2m_restart,
80b5efbd	530	MACHINE_END
8deed178 PM	531
	532	#if defined(CONFIG_ARCH_VEXPRESS_DT)
	533
6a371956 PM	534	static struct map_desc v2m_rs1_io_desc __initdata = {
	535	.virtual = V2M_PERIPH,
	536	.pfn = __phys_to_pfn(0x1c000000),
	537	.length = SZ_2M,
	538	.type = MT_DEVICE,
	539	};
	540
	541	static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
	542	int depth, void *data)
	543	{
	544	const char **map = data;
	545
	546	if (strcmp(uname, "motherboard") != 0)
	547	return 0;
	548
	549	*map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
	550
	551	return 1;
	552	}
	553
8deed178 PM	554	void __init v2m_dt_map_io(void)
8deed178 PM	555	{
6a371956 PM	556	const char *map = NULL;
	557
	558	of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
	559
	560	if (map && strcmp(map, "rs1") == 0)
	561	iotable_init(&v2m_rs1_io_desc, 1);
	562	else
	563	iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
8deed178 PM	564
	565	#if defined(CONFIG_SMP)
	566	vexpress_dt_smp_map_io();
	567	#endif
	568	}
	569
8deed178 PM	570	void __init v2m_dt_init_early(void)
	571	{
	572	struct device_node *node;
	573	u32 dt_hbi;
	574
	575	node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
	576	v2m_sysreg_base = of_iomap(node, 0);
	577	if (WARN_ON(!v2m_sysreg_base))
	578	return;
	579
	580	/* Confirm board type against DT property, if available */
	581	if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
d927daf5 PM	582	int site = v2m_get_master_site();
d927daf5 PM	583	u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
8deed178 PM	584	V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
	585	u32 hbi = id & SYS_PROCIDx_HBI_MASK;
	586
	587	if (WARN_ON(dt_hbi != hbi))
	588	pr_warning("vexpress: DT HBI (%x) is not matching "
	589	"hardware (%x)!\n", dt_hbi, hbi);
	590	}
8deed178 PM	591	}
	592
	593	static struct of_device_id vexpress_irq_match[] __initdata = {
	594	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	595	{}
	596	};
	597
	598	static void __init v2m_dt_init_irq(void)
	599	{
	600	of_irq_init(vexpress_irq_match);
	601	}
	602
	603	static void __init v2m_dt_timer_init(void)
	604	{
	605	struct device_node *node;
	606	const char *path;
	607	int err;
	608
	609	node = of_find_compatible_node(NULL, NULL, "arm,sp810");
	610	v2m_sysctl_init(of_iomap(node, 0));
	611
d1b8a775 PM	612	v2m_clk_init();
d1b8a775 PM	613
8deed178 PM	614	err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
	615	if (WARN_ON(err))
	616	return;
	617	node = of_find_node_by_path(path);
	618	v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
120f3d6c MZ	619	if (arch_timer_of_register() != 0)
	620	twd_local_timer_of_register();
	621
	622	if (arch_timer_sched_clock_init() != 0)
	623	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
8deed178 PM	624	}
	625
	626	static struct sys_timer v2m_dt_timer = {
	627	.init = v2m_dt_timer_init,
	628	};
	629
	630	static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
	631	OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
	632	&v2m_flash_data),
	633	OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
6a371956 PM	634	/* RS1 memory map */
	635	OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
	636	&v2m_flash_data),
	637	OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
8deed178 PM	638	{}
	639	};
	640
	641	static void __init v2m_dt_init(void)
	642	{
	643	l2x0_of_init(0x00400000, 0xfe0fffff);
	644	of_platform_populate(NULL, of_default_bus_match_table,
	645	v2m_dt_auxdata_lookup, NULL);
	646	pm_power_off = v2m_power_off;
	647	}
	648
	649	const static char *v2m_dt_match[] __initconst = {
	650	"arm,vexpress",
	651	NULL,
	652	};
	653
	654	DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
	655	.dt_compat = v2m_dt_match,
	656	.map_io = v2m_dt_map_io,
	657	.init_early = v2m_dt_init_early,
	658	.init_irq = v2m_dt_init_irq,
	659	.timer = &v2m_dt_timer,
	660	.init_machine = v2m_dt_init,
	661	.handle_irq = gic_handle_irq,
	662	.restart = v2m_restart,
	663	MACHINE_END
	664
	665	#endif