projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 21f47fbc AC |
1 | /* |
| 2 | * arch/arm/mach-vt8500/include/mach/vt8500_irqs.h | |
| 3 | * | |
| 4 | * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License as published by | |
| 8 | * the Free Software Foundation; either version 2 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 19 | */ | |
| 20 | ||
| 21 | /* VT8500 Interrupt Sources */ | |
| 22 | ||
| 23 | #define IRQ_JPEGENC 0 /* JPEG Encoder */ | |
| 24 | #define IRQ_JPEGDEC 1 /* JPEG Decoder */ | |
| 25 | /* Reserved */ | |
| 26 | #define IRQ_PATA 3 /* PATA Controller */ | |
| 27 | /* Reserved */ | |
| 28 | #define IRQ_DMA 5 /* DMA Controller */ | |
| 29 | #define IRQ_EXT0 6 /* External Interrupt 0 */ | |
| 30 | #define IRQ_EXT1 7 /* External Interrupt 1 */ | |
| 31 | #define IRQ_GE 8 /* Graphic Engine */ | |
| 32 | #define IRQ_GOV 9 /* Graphic Overlay Engine */ | |
| 33 | #define IRQ_ETHER 10 /* Ethernet MAC */ | |
| 34 | #define IRQ_MPEGTS 11 /* Transport Stream Interface */ | |
| 35 | #define IRQ_LCDC 12 /* LCD Controller */ | |
| 36 | #define IRQ_EXT2 13 /* External Interrupt 2 */ | |
| 37 | #define IRQ_EXT3 14 /* External Interrupt 3 */ | |
| 38 | #define IRQ_EXT4 15 /* External Interrupt 4 */ | |
| 39 | #define IRQ_CIPHER 16 /* Cipher */ | |
| 40 | #define IRQ_VPP 17 /* Video Post-Processor */ | |
| 41 | #define IRQ_I2C1 18 /* I2C 1 */ | |
| 42 | #define IRQ_I2C0 19 /* I2C 0 */ | |
| 43 | #define IRQ_SDMMC 20 /* SD/MMC Controller */ | |
| 44 | #define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */ | |
| 45 | #define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */ | |
| 46 | /* Reserved */ | |
| 47 | #define IRQ_SPI0 24 /* SPI 0 */ | |
| 48 | #define IRQ_SPI1 25 /* SPI 1 */ | |
| 49 | #define IRQ_SPI2 26 /* SPI 2 */ | |
| 50 | #define IRQ_LCDDF 27 /* LCD Data Formatter */ | |
| 51 | #define IRQ_NAND 28 /* NAND Flash Controller */ | |
| 52 | #define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */ | |
| 53 | #define IRQ_MS 30 /* MemoryStick Controller */ | |
| 54 | #define IRQ_MS_DMA 31 /* MemoryStick Controller DMA */ | |
| 55 | #define IRQ_UART0 32 /* UART 0 */ | |
| 56 | #define IRQ_UART1 33 /* UART 1 */ | |
| 57 | #define IRQ_I2S 34 /* I2S */ | |
| 58 | #define IRQ_PCM 35 /* PCM */ | |
| 59 | #define IRQ_PMCOS0 36 /* PMC OS Timer 0 */ | |
| 60 | #define IRQ_PMCOS1 37 /* PMC OS Timer 1 */ | |
| 61 | #define IRQ_PMCOS2 38 /* PMC OS Timer 2 */ | |
| 62 | #define IRQ_PMCOS3 39 /* PMC OS Timer 3 */ | |
| 63 | #define IRQ_VPU 40 /* Video Processing Unit */ | |
| 64 | #define IRQ_VID 41 /* Video Digital Input Interface */ | |
| 65 | #define IRQ_AC97 42 /* AC97 Interface */ | |
| 66 | #define IRQ_EHCI 43 /* USB */ | |
| 67 | #define IRQ_NOR 44 /* NOR Flash Controller */ | |
| 68 | #define IRQ_PS2MOUSE 45 /* PS/2 Mouse */ | |
| 69 | #define IRQ_PS2KBD 46 /* PS/2 Keyboard */ | |
| 70 | #define IRQ_UART2 47 /* UART 2 */ | |
| 71 | #define IRQ_RTC 48 /* RTC Interrupt */ | |
| 72 | #define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */ | |
| 73 | #define IRQ_UART3 50 /* UART 3 */ | |
| 74 | #define IRQ_ADC 51 /* ADC */ | |
| 75 | #define IRQ_EXT5 52 /* External Interrupt 5 */ | |
| 76 | #define IRQ_EXT6 53 /* External Interrupt 6 */ | |
| 77 | #define IRQ_EXT7 54 /* External Interrupt 7 */ | |
| 78 | #define IRQ_CIR 55 /* CIR */ | |
| 79 | #define IRQ_DMA0 56 /* DMA Channel 0 */ | |
| 80 | #define IRQ_DMA1 57 /* DMA Channel 1 */ | |
| 81 | #define IRQ_DMA2 58 /* DMA Channel 2 */ | |
| 82 | #define IRQ_DMA3 59 /* DMA Channel 3 */ | |
| 83 | #define IRQ_DMA4 60 /* DMA Channel 4 */ | |
| 84 | #define IRQ_DMA5 61 /* DMA Channel 5 */ | |
| 85 | #define IRQ_DMA6 62 /* DMA Channel 6 */ | |
| 86 | #define IRQ_DMA7 63 /* DMA Channel 7 */ | |
| 87 | ||
| 88 | #define VT8500_NR_IRQS 64 |