Commit | Line | Data |
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7ec80ddf | 1 | /* |
35c9221a | 2 | * linux/arch/arm/mach-w90x900/cpu.c |
7ec80ddf | 3 | * |
35c9221a | 4 | * Copyright (c) 2009 Nuvoton corporation. |
7ec80ddf | 5 | * |
6 | * Wan ZongShun <mcuos.com@gmail.com> | |
7 | * | |
35c9221a | 8 | * NUC900 series cpu common support |
7ec80ddf | 9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
604f766f | 12 | * the Free Software Foundation;version 2 of the License. |
7ec80ddf | 13 | * |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/timer.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/io.h> | |
17198f2d | 24 | #include <linux/serial_8250.h> |
ae45b1c6 | 25 | #include <linux/delay.h> |
7ec80ddf | 26 | |
27 | #include <asm/mach/arch.h> | |
28 | #include <asm/mach/map.h> | |
29 | #include <asm/mach/irq.h> | |
30 | #include <asm/irq.h> | |
9f97da78 | 31 | #include <asm/system_misc.h> |
7ec80ddf | 32 | |
33 | #include <mach/hardware.h> | |
34 | #include <mach/regs-serial.h> | |
ae45b1c6 | 35 | #include <mach/regs-clock.h> |
36 | #include <mach/regs-ebi.h> | |
fe76daea | 37 | #include <mach/regs-timer.h> |
7ec80ddf | 38 | |
39 | #include "cpu.h" | |
0e4a34bb | 40 | #include "clock.h" |
fe76daea | 41 | #include "nuc9xx.h" |
7ec80ddf | 42 | |
7ec80ddf | 43 | /* Initial IO mappings */ |
44 | ||
35c9221a | 45 | static struct map_desc nuc900_iodesc[] __initdata = { |
7ec80ddf | 46 | IODESC_ENT(IRQ), |
47 | IODESC_ENT(GCR), | |
48 | IODESC_ENT(UART), | |
49 | IODESC_ENT(TIMER), | |
50 | IODESC_ENT(EBI), | |
6d636c68 | 51 | IODESC_ENT(GPIO), |
7ec80ddf | 52 | }; |
53 | ||
0e4a34bb | 54 | /* Initial clock declarations. */ |
55 | static DEFINE_CLK(lcd, 0); | |
56 | static DEFINE_CLK(audio, 1); | |
57 | static DEFINE_CLK(fmi, 4); | |
db58e90f | 58 | static DEFINE_SUBCLK(ms, 0); |
59 | static DEFINE_SUBCLK(sd, 1); | |
0e4a34bb | 60 | static DEFINE_CLK(dmac, 5); |
61 | static DEFINE_CLK(atapi, 6); | |
62 | static DEFINE_CLK(emc, 7); | |
db58e90f | 63 | static DEFINE_SUBCLK(rmii, 2); |
0e4a34bb | 64 | static DEFINE_CLK(usbd, 8); |
65 | static DEFINE_CLK(usbh, 9); | |
69932487 | 66 | static DEFINE_CLK(g2d, 10); |
0e4a34bb | 67 | static DEFINE_CLK(pwm, 18); |
68 | static DEFINE_CLK(ps2, 24); | |
69 | static DEFINE_CLK(kpi, 25); | |
70 | static DEFINE_CLK(wdt, 26); | |
71 | static DEFINE_CLK(gdma, 27); | |
72 | static DEFINE_CLK(adc, 28); | |
73 | static DEFINE_CLK(usi, 29); | |
58b5369e | 74 | static DEFINE_CLK(ext, 0); |
ce746e47 | 75 | static DEFINE_CLK(timer0, 19); |
76 | static DEFINE_CLK(timer1, 20); | |
77 | static DEFINE_CLK(timer2, 21); | |
78 | static DEFINE_CLK(timer3, 22); | |
79 | static DEFINE_CLK(timer4, 23); | |
0e4a34bb | 80 | |
35c9221a | 81 | static struct clk_lookup nuc900_clkregs[] = { |
82 | DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL), | |
e37051dc | 83 | DEF_CLKLOOK(&clk_audio, "nuc900-ac97", NULL), |
35c9221a | 84 | DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL), |
85 | DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"), | |
86 | DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"), | |
87 | DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL), | |
88 | DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL), | |
89 | DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL), | |
90 | DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"), | |
91 | DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL), | |
92 | DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL), | |
93 | DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL), | |
94 | DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL), | |
95 | DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL), | |
96 | DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL), | |
97 | DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL), | |
98 | DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL), | |
a7029c82 | 99 | DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL), |
35c9221a | 100 | DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL), |
58b5369e | 101 | DEF_CLKLOOK(&clk_ext, NULL, "ext"), |
ce746e47 | 102 | DEF_CLKLOOK(&clk_timer0, NULL, "timer0"), |
103 | DEF_CLKLOOK(&clk_timer1, NULL, "timer1"), | |
104 | DEF_CLKLOOK(&clk_timer2, NULL, "timer2"), | |
105 | DEF_CLKLOOK(&clk_timer3, NULL, "timer3"), | |
106 | DEF_CLKLOOK(&clk_timer4, NULL, "timer4"), | |
0e4a34bb | 107 | }; |
108 | ||
17198f2d | 109 | /* Initial serial platform data */ |
7ec80ddf | 110 | |
35c9221a | 111 | struct plat_serial8250_port nuc900_uart_data[] = { |
112 | NUC900_8250PORT(UART0), | |
db93dd1a | 113 | {}, |
17198f2d | 114 | }; |
7ec80ddf | 115 | |
35c9221a | 116 | struct platform_device nuc900_serial_device = { |
17198f2d | 117 | .name = "serial8250", |
118 | .id = PLAT8250_DEV_PLATFORM, | |
119 | .dev = { | |
35c9221a | 120 | .platform_data = nuc900_uart_data, |
17198f2d | 121 | }, |
122 | }; | |
7ec80ddf | 123 | |
35c9221a | 124 | /*Set NUC900 series cpu frequence*/ |
125 | static int __init nuc900_set_clkval(unsigned int cpufreq) | |
ae45b1c6 | 126 | { |
127 | unsigned int pllclk, ahbclk, apbclk, val; | |
128 | ||
129 | pllclk = 0; | |
130 | ahbclk = 0; | |
131 | apbclk = 0; | |
132 | ||
133 | switch (cpufreq) { | |
134 | case 66: | |
135 | pllclk = PLL_66MHZ; | |
136 | ahbclk = AHB_CPUCLK_1_1; | |
137 | apbclk = APB_AHB_1_2; | |
138 | break; | |
139 | ||
140 | case 100: | |
141 | pllclk = PLL_100MHZ; | |
142 | ahbclk = AHB_CPUCLK_1_1; | |
143 | apbclk = APB_AHB_1_2; | |
144 | break; | |
145 | ||
146 | case 120: | |
147 | pllclk = PLL_120MHZ; | |
148 | ahbclk = AHB_CPUCLK_1_2; | |
149 | apbclk = APB_AHB_1_2; | |
150 | break; | |
151 | ||
152 | case 166: | |
153 | pllclk = PLL_166MHZ; | |
154 | ahbclk = AHB_CPUCLK_1_2; | |
155 | apbclk = APB_AHB_1_2; | |
156 | break; | |
157 | ||
158 | case 200: | |
159 | pllclk = PLL_200MHZ; | |
160 | ahbclk = AHB_CPUCLK_1_2; | |
161 | apbclk = APB_AHB_1_2; | |
162 | break; | |
163 | } | |
164 | ||
165 | __raw_writel(pllclk, REG_PLLCON0); | |
166 | ||
167 | val = __raw_readl(REG_CLKDIV); | |
168 | val &= ~(0x03 << 24 | 0x03 << 26); | |
169 | val |= (ahbclk << 24 | apbclk << 26); | |
170 | __raw_writel(val, REG_CLKDIV); | |
171 | ||
172 | return 0; | |
173 | } | |
35c9221a | 174 | static int __init nuc900_set_cpufreq(char *str) |
ae45b1c6 | 175 | { |
176 | unsigned long cpufreq, val; | |
177 | ||
178 | if (!*str) | |
179 | return 0; | |
180 | ||
181 | strict_strtoul(str, 0, &cpufreq); | |
182 | ||
35c9221a | 183 | nuc900_clock_source(NULL, "ext"); |
ae45b1c6 | 184 | |
35c9221a | 185 | nuc900_set_clkval(cpufreq); |
ae45b1c6 | 186 | |
187 | mdelay(1); | |
188 | ||
189 | val = __raw_readl(REG_CKSKEW); | |
190 | val &= ~0xff; | |
191 | val |= DEFAULTSKEW; | |
192 | __raw_writel(val, REG_CKSKEW); | |
193 | ||
35c9221a | 194 | nuc900_clock_source(NULL, "pll0"); |
ae45b1c6 | 195 | |
196 | return 1; | |
197 | } | |
198 | ||
35c9221a | 199 | __setup("cpufreq=", nuc900_set_cpufreq); |
ae45b1c6 | 200 | |
35c9221a | 201 | /*Init NUC900 evb io*/ |
7ec80ddf | 202 | |
35c9221a | 203 | void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size) |
7ec80ddf | 204 | { |
35c9221a | 205 | unsigned long idcode = 0x0; |
7ec80ddf | 206 | |
35c9221a | 207 | iotable_init(mach_desc, mach_size); |
208 | iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc)); | |
209 | ||
210 | idcode = __raw_readl(NUC900PDID); | |
211 | if (idcode == NUC910_CPUID) | |
212 | printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode); | |
213 | else if (idcode == NUC920_CPUID) | |
214 | printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode); | |
215 | else if (idcode == NUC950_CPUID) | |
216 | printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode); | |
217 | else if (idcode == NUC960_CPUID) | |
218 | printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode); | |
7ec80ddf | 219 | } |
220 | ||
35c9221a | 221 | /*Init NUC900 clock*/ |
222 | ||
223 | void __init nuc900_init_clocks(void) | |
7ec80ddf | 224 | { |
0a0300dc | 225 | clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs)); |
7ec80ddf | 226 | } |
35c9221a | 227 | |
fe76daea RK |
228 | #define WTCR (TMR_BA + 0x1C) |
229 | #define WTCLK (1 << 10) | |
230 | #define WTE (1 << 7) | |
231 | #define WTRE (1 << 1) | |
232 | ||
7b6d864b | 233 | void nuc9xx_restart(enum reboot_mode mode, const char *cmd) |
fe76daea | 234 | { |
7b6d864b | 235 | if (mode == REBOOT_SOFT) { |
fe76daea RK |
236 | /* Jump into ROM at address 0 */ |
237 | soft_restart(0); | |
238 | } else { | |
239 | __raw_writel(WTE | WTRE | WTCLK, WTCR); | |
240 | } | |
241 | } |