[deliverable/linux.git] / arch / arm / mach-w90x900 / time.c

/*
 * linux/arch/arm/mach-w90x900/time.c
 *
 * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
 *
 * Copyright (c) 2009 Nuvoton technology corporation
 * All rights reserved.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/leds.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>

#include <asm/mach-types.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>

#include <mach/map.h>
#include <mach/regs-timer.h>

#define RESETINT	0x1f
#define PERIOD		(0x01 << 27)
#define ONESHOT		(0x00 << 27)
#define COUNTEN		(0x01 << 30)
#define INTEN		(0x01 << 29)

#define TICKS_PER_SEC	100
#define PRESCALE	0x63 /* Divider = prescale + 1 */

unsigned int timer0_load;

static void nuc900_clockevent_setmode(enum clock_event_mode mode,
		struct clock_event_device *clk)
{
	unsigned int val;

	val = __raw_readl(REG_TCSR0);
	val &= ~(0x03 << 27);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		__raw_writel(timer0_load, REG_TICR0);
		val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}

	__raw_writel(val, REG_TCSR0);
}

static int nuc900_clockevent_setnextevent(unsigned long evt,
		struct clock_event_device *clk)
{
	unsigned int val;

	__raw_writel(evt, REG_TICR0);

	val = __raw_readl(REG_TCSR0);
	val |= (COUNTEN | INTEN | PRESCALE);
	__raw_writel(val, REG_TCSR0);

	return 0;
}

static struct clock_event_device nuc900_clockevent_device = {
	.name		= "nuc900-timer0",
	.shift		= 32,
	.features	= CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= nuc900_clockevent_setmode,
	.set_next_event	= nuc900_clockevent_setnextevent,
	.rating		= 300,
};

/*IRQ handler for the timer*/

static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &nuc900_clockevent_device;

	__raw_writel(0x01, REG_TISR); /* clear TIF0 */

	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction nuc900_timer0_irq = {
	.name		= "nuc900-timer0",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= nuc900_timer0_interrupt,
};

static void __init nuc900_clockevents_init(unsigned int rate)
{
	nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
					nuc900_clockevent_device.shift);
	nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
					&nuc900_clockevent_device);
	nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
					&nuc900_clockevent_device);
	nuc900_clockevent_device.cpumask = cpumask_of(0);

	clockevents_register_device(&nuc900_clockevent_device);
}

static cycle_t nuc900_get_cycles(struct clocksource *cs)
{
	return ~__raw_readl(REG_TDR1);
}

static struct clocksource clocksource_nuc900 = {
	.name	= "nuc900-timer1",
	.rating	= 200,
	.read	= nuc900_get_cycles,
	.mask	= CLOCKSOURCE_MASK(32),
	.shift	= 20,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init nuc900_clocksource_init(unsigned int rate)
{
	unsigned int val;

	__raw_writel(0xffffffff, REG_TICR1);

	val = __raw_readl(REG_TCSR1);
	val |= (COUNTEN | PERIOD);
	__raw_writel(val, REG_TCSR1);

	clocksource_nuc900.mult =
		clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
	clocksource_register(&clocksource_nuc900);
}

static void __init nuc900_timer_init(void)
{
	struct clk *ck_ext = clk_get(NULL, "ext");
	unsigned int	rate;

	BUG_ON(IS_ERR(ck_ext));

	rate = clk_get_rate(ck_ext);
	clk_put(ck_ext);
	rate = rate / (PRESCALE + 0x01);

	 /* set a known state */
	__raw_writel(0x00, REG_TCSR0);
	__raw_writel(0x00, REG_TCSR1);
	__raw_writel(RESETINT, REG_TISR);
	timer0_load = (rate / TICKS_PER_SEC);

	setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);

	nuc900_clocksource_init(rate);
	nuc900_clockevents_init(rate);
}

struct sys_timer nuc900_timer = {
	.init		= nuc900_timer_init,
};
Commit	Line	Data
7ec80ddf	1	/*
	2	* linux/arch/arm/mach-w90x900/time.c
	3	*
	4	* Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
	5	*
58b5369e	6	* Copyright (c) 2009 Nuvoton technology corporation
7ec80ddf	7	* All rights reserved.
	8	*
	9	* Wan ZongShun <mcuos.com@gmail.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/sched.h>
	20	#include <linux/init.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/err.h>
	23	#include <linux/clk.h>
	24	#include <linux/io.h>
	25	#include <linux/leds.h>
58b5369e	26	#include <linux/clocksource.h>
58b5369e	27	#include <linux/clockchips.h>
7ec80ddf	28
	29	#include <asm/mach-types.h>
	30	#include <asm/mach/irq.h>
	31	#include <asm/mach/time.h>
	32
7ec80ddf	33	#include <mach/map.h>
	34	#include <mach/regs-timer.h>
	35
58b5369e	36	#define RESETINT 0x1f
	37	#define PERIOD (0x01 << 27)
	38	#define ONESHOT (0x00 << 27)
	39	#define COUNTEN (0x01 << 30)
	40	#define INTEN (0x01 << 29)
	41
	42	#define TICKS_PER_SEC 100
	43	#define PRESCALE 0x63 /* Divider = prescale + 1 */
	44
	45	unsigned int timer0_load;
	46
35c9221a	47	static void nuc900_clockevent_setmode(enum clock_event_mode mode,
58b5369e	48	struct clock_event_device *clk)
7ec80ddf	49	{
58b5369e	50	unsigned int val;
	51
	52	val = __raw_readl(REG_TCSR0);
	53	val &= ~(0x03 << 27);
	54
	55	switch (mode) {
	56	case CLOCK_EVT_MODE_PERIODIC:
	57	__raw_writel(timer0_load, REG_TICR0);
	58	val \|= (PERIOD \| COUNTEN \| INTEN \| PRESCALE);
	59	break;
	60
	61	case CLOCK_EVT_MODE_ONESHOT:
	62	val \|= (ONESHOT \| COUNTEN \| INTEN \| PRESCALE);
	63	break;
	64
	65	case CLOCK_EVT_MODE_UNUSED:
	66	case CLOCK_EVT_MODE_SHUTDOWN:
	67	case CLOCK_EVT_MODE_RESUME:
	68	break;
	69	}
	70
	71	__raw_writel(val, REG_TCSR0);
	72	}
	73
35c9221a	74	static int nuc900_clockevent_setnextevent(unsigned long evt,
58b5369e	75	struct clock_event_device *clk)
	76	{
	77	unsigned int val;
	78
	79	__raw_writel(evt, REG_TICR0);
	80
	81	val = __raw_readl(REG_TCSR0);
	82	val \|= (COUNTEN \| INTEN \| PRESCALE);
	83	__raw_writel(val, REG_TCSR0);
	84
7ec80ddf	85	return 0;
	86	}
	87
35c9221a	88	static struct clock_event_device nuc900_clockevent_device = {
35c9221a	89	.name = "nuc900-timer0",
58b5369e	90	.shift = 32,
58b5369e	91	.features = CLOCK_EVT_MODE_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
35c9221a	92	.set_mode = nuc900_clockevent_setmode,
35c9221a	93	.set_next_event = nuc900_clockevent_setnextevent,
58b5369e	94	.rating = 300,
	95	};
	96
7ec80ddf	97	/IRQ handler for the timer/
7ec80ddf	98
35c9221a	99	static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
7ec80ddf	100	{
35c9221a	101	struct clock_event_device *evt = &nuc900_clockevent_device;
58b5369e	102
7ec80ddf	103	__raw_writel(0x01, REG_TISR); /* clear TIF0 */
58b5369e	104
58b5369e	105	evt->event_handler(evt);
7ec80ddf	106	return IRQ_HANDLED;
	107	}
	108
35c9221a	109	static struct irqaction nuc900_timer0_irq = {
35c9221a	110	.name = "nuc900-timer0",
7ec80ddf	111	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
35c9221a	112	.handler = nuc900_timer0_interrupt,
7ec80ddf	113	};
7ec80ddf	114
35c9221a	115	static void __init nuc900_clockevents_init(unsigned int rate)
58b5369e	116	{
35c9221a	117	nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
	118	nuc900_clockevent_device.shift);
	119	nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
	120	&nuc900_clockevent_device);
	121	nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
	122	&nuc900_clockevent_device);
	123	nuc900_clockevent_device.cpumask = cpumask_of(0);
	124
	125	clockevents_register_device(&nuc900_clockevent_device);
58b5369e	126	}
58b5369e	127
35c9221a	128	static cycle_t nuc900_get_cycles(struct clocksource *cs)
7ec80ddf	129	{
58b5369e	130	return ~__raw_readl(REG_TDR1);
7ec80ddf	131	}
7ec80ddf	132
35c9221a	133	static struct clocksource clocksource_nuc900 = {
35c9221a	134	.name = "nuc900-timer1",
58b5369e	135	.rating = 200,
35c9221a	136	.read = nuc900_get_cycles,
58b5369e	137	.mask = CLOCKSOURCE_MASK(32),
	138	.shift = 20,
	139	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	140	};
	141
35c9221a	142	static void __init nuc900_clocksource_init(unsigned int rate)
7ec80ddf	143	{
58b5369e	144	unsigned int val;
	145
	146	__raw_writel(0xffffffff, REG_TICR1);
	147
	148	val = __raw_readl(REG_TCSR1);
	149	val \|= (COUNTEN \| PERIOD);
	150	__raw_writel(val, REG_TCSR1);
	151
35c9221a	152	clocksource_nuc900.mult =
	153	clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
	154	clocksource_register(&clocksource_nuc900);
58b5369e	155	}
58b5369e	156
35c9221a	157	static void __init nuc900_timer_init(void)
58b5369e	158	{
	159	struct clk *ck_ext = clk_get(NULL, "ext");
	160	unsigned int rate;
	161
	162	BUG_ON(IS_ERR(ck_ext));
	163
	164	rate = clk_get_rate(ck_ext);
	165	clk_put(ck_ext);
	166	rate = rate / (PRESCALE + 0x01);
	167
	168	/* set a known state */
	169	__raw_writel(0x00, REG_TCSR0);
	170	__raw_writel(0x00, REG_TCSR1);
	171	__raw_writel(RESETINT, REG_TISR);
	172	timer0_load = (rate / TICKS_PER_SEC);
	173
35c9221a	174	setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
58b5369e	175
35c9221a	176	nuc900_clocksource_init(rate);
35c9221a	177	nuc900_clockevents_init(rate);
7ec80ddf	178	}
7ec80ddf	179
35c9221a	180	struct sys_timer nuc900_timer = {
35c9221a	181	.init = nuc900_timer_init,
7ec80ddf	182	};