Commit | Line | Data |
---|---|---|
b85a3ef4 JL |
1 | /* |
2 | * This file contains common code that is intended to be used across | |
3 | * boards so that it's not replicated. | |
4 | * | |
5 | * Copyright (C) 2011 Xilinx | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/cpumask.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/clk.h> | |
4a32c74e | 22 | #include <linux/clk-provider.h> |
0f586fbf | 23 | #include <linux/clk/zynq.h> |
e932900a | 24 | #include <linux/clocksource.h> |
0f586fbf | 25 | #include <linux/of_address.h> |
b85a3ef4 JL |
26 | #include <linux/of_irq.h> |
27 | #include <linux/of_platform.h> | |
3d64b449 | 28 | #include <linux/of.h> |
46f5b960 | 29 | #include <linux/memblock.h> |
9f4f5d26 SB |
30 | #include <linux/irqchip.h> |
31 | #include <linux/irqchip/arm-gic.h> | |
b85a3ef4 | 32 | |
3d64b449 | 33 | #include <asm/mach/arch.h> |
b85a3ef4 | 34 | #include <asm/mach/map.h> |
03e07595 | 35 | #include <asm/mach/time.h> |
3d64b449 | 36 | #include <asm/mach-types.h> |
b85a3ef4 | 37 | #include <asm/page.h> |
9a45eb69 | 38 | #include <asm/pgtable.h> |
732078c3 | 39 | #include <asm/smp_scu.h> |
b85a3ef4 JL |
40 | #include <asm/hardware/cache-l2x0.h> |
41 | ||
b85a3ef4 JL |
42 | #include "common.h" |
43 | ||
732078c3 MS |
44 | void __iomem *zynq_scu_base; |
45 | ||
46f5b960 MS |
46 | /** |
47 | * zynq_memory_init - Initialize special memory | |
48 | * | |
49 | * We need to stop things allocating the low memory as DMA can't work in | |
50 | * the 1st 512K of memory. | |
51 | */ | |
52 | static void __init zynq_memory_init(void) | |
53 | { | |
54 | if (!__pa(PAGE_OFFSET)) | |
55 | memblock_reserve(__pa(PAGE_OFFSET), __pa(swapper_pg_dir)); | |
56 | } | |
57 | ||
3e8ceca6 DL |
58 | static struct platform_device zynq_cpuidle_device = { |
59 | .name = "cpuidle-zynq", | |
60 | }; | |
61 | ||
b85a3ef4 | 62 | /** |
889faa88 MS |
63 | * zynq_init_machine - System specific initialization, intended to be |
64 | * called from board specific initialization. | |
b85a3ef4 | 65 | */ |
889faa88 | 66 | static void __init zynq_init_machine(void) |
b85a3ef4 | 67 | { |
cd325295 SB |
68 | struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; |
69 | ||
b85a3ef4 JL |
70 | /* |
71 | * 64KB way size, 8-way associativity, parity disabled | |
72 | */ | |
0fcfdbca | 73 | l2x0_of_init(0x02060000, 0xF0F0FFFF); |
b85a3ef4 | 74 | |
f4d5d7b7 | 75 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
3e8ceca6 DL |
76 | |
77 | platform_device_register(&zynq_cpuidle_device); | |
cd325295 | 78 | platform_device_register_full(&devinfo); |
016f4dca MS |
79 | |
80 | zynq_slcr_init(); | |
b85a3ef4 JL |
81 | } |
82 | ||
889faa88 | 83 | static void __init zynq_timer_init(void) |
03e07595 | 84 | { |
016f4dca | 85 | zynq_early_slcr_init(); |
6f69c7f2 | 86 | |
b0504e39 | 87 | zynq_clock_init(); |
4a32c74e | 88 | of_clk_init(NULL); |
c5263bb8 | 89 | clocksource_of_init(); |
03e07595 JC |
90 | } |
91 | ||
732078c3 MS |
92 | static struct map_desc zynq_cortex_a9_scu_map __initdata = { |
93 | .length = SZ_256, | |
94 | .type = MT_DEVICE, | |
95 | }; | |
96 | ||
97 | static void __init zynq_scu_map_io(void) | |
98 | { | |
99 | unsigned long base; | |
100 | ||
101 | base = scu_a9_get_base(); | |
102 | zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base); | |
103 | /* Expected address is in vmalloc area that's why simple assign here */ | |
104 | zynq_cortex_a9_scu_map.virtual = base; | |
105 | iotable_init(&zynq_cortex_a9_scu_map, 1); | |
106 | zynq_scu_base = (void __iomem *)base; | |
107 | BUG_ON(!zynq_scu_base); | |
108 | } | |
109 | ||
b85a3ef4 | 110 | /** |
889faa88 | 111 | * zynq_map_io - Create memory mappings needed for early I/O. |
b85a3ef4 | 112 | */ |
889faa88 | 113 | static void __init zynq_map_io(void) |
b85a3ef4 | 114 | { |
385f02b1 | 115 | debug_ll_io_init(); |
732078c3 | 116 | zynq_scu_map_io(); |
b85a3ef4 | 117 | } |
3d64b449 | 118 | |
9f4f5d26 SB |
119 | static void __init zynq_irq_init(void) |
120 | { | |
121 | gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; | |
122 | irqchip_init(); | |
123 | } | |
124 | ||
fe08bf9f | 125 | static void zynq_system_reset(enum reboot_mode mode, const char *cmd) |
96790f0a MS |
126 | { |
127 | zynq_slcr_system_reset(); | |
128 | } | |
129 | ||
889faa88 | 130 | static const char * const zynq_dt_match[] = { |
e06f1a9e | 131 | "xlnx,zynq-7000", |
3d64b449 AB |
132 | NULL |
133 | }; | |
134 | ||
514a5908 | 135 | DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") |
aa7eb2bb | 136 | .smp = smp_ops(zynq_smp_ops), |
889faa88 | 137 | .map_io = zynq_map_io, |
9f4f5d26 | 138 | .init_irq = zynq_irq_init, |
889faa88 MS |
139 | .init_machine = zynq_init_machine, |
140 | .init_time = zynq_timer_init, | |
141 | .dt_compat = zynq_dt_match, | |
46f5b960 | 142 | .reserve = zynq_memory_init, |
96790f0a | 143 | .restart = zynq_system_reset, |
3d64b449 | 144 | MACHINE_END |