Commit | Line | Data |
---|---|---|
64b889b3 MS |
1 | /* |
2 | * Xilinx SLCR driver | |
3 | * | |
4 | * Copyright (c) 2011-2013 Xilinx Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public | |
12 | * License along with this program; if not, write to the Free | |
13 | * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA | |
14 | * 02139, USA. | |
15 | */ | |
16 | ||
64b889b3 | 17 | #include <linux/io.h> |
64e68617 | 18 | #include <linux/reboot.h> |
016f4dca | 19 | #include <linux/mfd/syscon.h> |
64b889b3 | 20 | #include <linux/of_address.h> |
016f4dca | 21 | #include <linux/regmap.h> |
64b889b3 MS |
22 | #include <linux/clk/zynq.h> |
23 | #include "common.h" | |
24 | ||
b5f177ff SB |
25 | /* register offsets */ |
26 | #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ | |
96790f0a | 27 | #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ |
b5f177ff SB |
28 | #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ |
29 | #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ | |
00f7dc63 | 30 | #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */ |
6ded93a1 | 31 | #define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */ |
aa7eb2bb | 32 | |
b5f177ff | 33 | #define SLCR_UNLOCK_MAGIC 0xDF0D |
aa7eb2bb MS |
34 | #define SLCR_A9_CPU_CLKSTOP 0x10 |
35 | #define SLCR_A9_CPU_RST 0x1 | |
00f7dc63 MS |
36 | #define SLCR_PSS_IDCODE_DEVICE_SHIFT 12 |
37 | #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F | |
aa7eb2bb | 38 | |
7b274efe | 39 | static void __iomem *zynq_slcr_base; |
016f4dca | 40 | static struct regmap *zynq_slcr_regmap; |
64b889b3 | 41 | |
871c6971 MS |
42 | /** |
43 | * zynq_slcr_write - Write to a register in SLCR block | |
44 | * | |
45 | * @val: Value to write to the register | |
46 | * @offset: Register offset in SLCR block | |
47 | * | |
48 | * Return: a negative value on error, 0 on success | |
49 | */ | |
50 | static int zynq_slcr_write(u32 val, u32 offset) | |
51 | { | |
871c6971 MS |
52 | return regmap_write(zynq_slcr_regmap, offset, val); |
53 | } | |
54 | ||
55 | /** | |
56 | * zynq_slcr_read - Read a register in SLCR block | |
57 | * | |
58 | * @val: Pointer to value to be read from SLCR | |
59 | * @offset: Register offset in SLCR block | |
60 | * | |
61 | * Return: a negative value on error, 0 on success | |
62 | */ | |
63 | static int zynq_slcr_read(u32 *val, u32 offset) | |
64 | { | |
3329659d | 65 | return regmap_read(zynq_slcr_regmap, offset, val); |
871c6971 MS |
66 | } |
67 | ||
56880073 MS |
68 | /** |
69 | * zynq_slcr_unlock - Unlock SLCR registers | |
70 | * | |
71 | * Return: a negative value on error, 0 on success | |
72 | */ | |
73 | static inline int zynq_slcr_unlock(void) | |
74 | { | |
75 | zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
00f7dc63 MS |
80 | /** |
81 | * zynq_slcr_get_device_id - Read device code id | |
82 | * | |
83 | * Return: Device code id | |
84 | */ | |
85 | u32 zynq_slcr_get_device_id(void) | |
86 | { | |
87 | u32 val; | |
88 | ||
89 | zynq_slcr_read(&val, SLCR_PSS_IDCODE); | |
90 | val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT; | |
91 | val &= SLCR_PSS_IDCODE_DEVICE_MASK; | |
92 | ||
93 | return val; | |
94 | } | |
95 | ||
96790f0a | 96 | /** |
64e68617 JC |
97 | * zynq_slcr_system_restart - Restart the entire system. |
98 | * | |
99 | * @nb: Pointer to restart notifier block (unused) | |
100 | * @action: Reboot mode (unused) | |
101 | * @data: Restart handler private data (unused) | |
102 | * | |
103 | * Return: 0 always | |
96790f0a | 104 | */ |
64e68617 JC |
105 | static |
106 | int zynq_slcr_system_restart(struct notifier_block *nb, | |
107 | unsigned long action, void *data) | |
96790f0a MS |
108 | { |
109 | u32 reboot; | |
110 | ||
96790f0a MS |
111 | /* |
112 | * Clear 0x0F000000 bits of reboot status register to workaround | |
113 | * the FSBL not loading the bitstream after soft-reboot | |
114 | * This is a temporary solution until we know more. | |
115 | */ | |
871c6971 MS |
116 | zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET); |
117 | zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); | |
118 | zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); | |
64e68617 | 119 | return 0; |
96790f0a MS |
120 | } |
121 | ||
64e68617 JC |
122 | static struct notifier_block zynq_slcr_restart_nb = { |
123 | .notifier_call = zynq_slcr_system_restart, | |
124 | .priority = 192, | |
125 | }; | |
126 | ||
aa7eb2bb MS |
127 | /** |
128 | * zynq_slcr_cpu_start - Start cpu | |
129 | * @cpu: cpu number | |
130 | */ | |
131 | void zynq_slcr_cpu_start(int cpu) | |
132 | { | |
871c6971 MS |
133 | u32 reg; |
134 | ||
135 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); | |
3db9e860 | 136 | reg &= ~(SLCR_A9_CPU_RST << cpu); |
871c6971 | 137 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
3db9e860 | 138 | reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); |
871c6971 | 139 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
50c7960a SB |
140 | |
141 | zynq_slcr_cpu_state_write(cpu, false); | |
aa7eb2bb MS |
142 | } |
143 | ||
144 | /** | |
145 | * zynq_slcr_cpu_stop - Stop cpu | |
146 | * @cpu: cpu number | |
147 | */ | |
148 | void zynq_slcr_cpu_stop(int cpu) | |
149 | { | |
871c6971 MS |
150 | u32 reg; |
151 | ||
152 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); | |
3db9e860 | 153 | reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; |
871c6971 | 154 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
aa7eb2bb MS |
155 | } |
156 | ||
64b889b3 | 157 | /** |
50c7960a SB |
158 | * zynq_slcr_cpu_state - Read/write cpu state |
159 | * @cpu: cpu number | |
016f4dca | 160 | * |
50c7960a SB |
161 | * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1) |
162 | * 0 means cpu is running, 1 cpu is going to die. | |
163 | * | |
164 | * Return: true if cpu is running, false if cpu is going to die | |
165 | */ | |
166 | bool zynq_slcr_cpu_state_read(int cpu) | |
167 | { | |
168 | u32 state; | |
169 | ||
170 | state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | |
171 | state &= 1 << (31 - cpu); | |
172 | ||
173 | return !state; | |
174 | } | |
175 | ||
176 | /** | |
177 | * zynq_slcr_cpu_state - Read/write cpu state | |
178 | * @cpu: cpu number | |
179 | * @die: cpu state - true if cpu is going to die | |
180 | * | |
181 | * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1) | |
182 | * 0 means cpu is running, 1 cpu is going to die. | |
183 | */ | |
184 | void zynq_slcr_cpu_state_write(int cpu, bool die) | |
185 | { | |
186 | u32 state, mask; | |
187 | ||
188 | state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | |
189 | mask = 1 << (31 - cpu); | |
190 | if (die) | |
191 | state |= mask; | |
192 | else | |
193 | state &= ~mask; | |
194 | writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | |
195 | } | |
196 | ||
016f4dca MS |
197 | /** |
198 | * zynq_early_slcr_init - Early slcr init function | |
199 | * | |
200 | * Return: 0 on success, negative errno otherwise. | |
201 | * | |
202 | * Called very early during boot from platform code to unlock SLCR. | |
203 | */ | |
204 | int __init zynq_early_slcr_init(void) | |
64b889b3 MS |
205 | { |
206 | struct device_node *np; | |
207 | ||
208 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); | |
209 | if (!np) { | |
210 | pr_err("%s: no slcr node found\n", __func__); | |
211 | BUG(); | |
212 | } | |
213 | ||
214 | zynq_slcr_base = of_iomap(np, 0); | |
215 | if (!zynq_slcr_base) { | |
216 | pr_err("%s: Unable to map I/O memory\n", __func__); | |
217 | BUG(); | |
218 | } | |
219 | ||
5e218280 ST |
220 | np->data = (__force void *)zynq_slcr_base; |
221 | ||
3329659d MS |
222 | zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); |
223 | if (IS_ERR(zynq_slcr_regmap)) { | |
224 | pr_err("%s: failed to find zynq-slcr\n", __func__); | |
225 | return -ENODEV; | |
226 | } | |
227 | ||
64b889b3 | 228 | /* unlock the SLCR so that registers can be changed */ |
56880073 | 229 | zynq_slcr_unlock(); |
64b889b3 | 230 | |
6ded93a1 JC |
231 | /* See AR#54190 design advisory */ |
232 | regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202); | |
233 | ||
64e68617 JC |
234 | register_restart_handler(&zynq_slcr_restart_nb); |
235 | ||
64b889b3 MS |
236 | pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); |
237 | ||
64b889b3 MS |
238 | of_node_put(np); |
239 | ||
240 | return 0; | |
241 | } |