[deliverable/linux.git] / arch / arm / mach-zynq / timer.c

/*
 * This file contains driver for the Xilinx PS Timer Counter IP.
 *
 *  Copyright (C) 2011 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include "common.h"

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define XTTCPS_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define XTTCPS_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define XTTCPS_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define XTTCPS_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define XTTCPS_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define XTTCPS_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define XTTCPS_CNT_CNTRL_DISABLE_MASK	0x1

/*
 * Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1<<4)

/**
 * struct xttcps_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 **/
struct xttcps_timer {
	void __iomem	*base_addr;
};

struct xttcps_timer_clocksource {
	struct xttcps_timer	xttc;
	struct clocksource	cs;
};

#define to_xttcps_timer_clksrc(x) \
		container_of(x, struct xttcps_timer_clocksource, cs)

struct xttcps_timer_clockevent {
	struct xttcps_timer		xttc;
	struct clock_event_device	ce;
	struct clk			*clk;
};

#define to_xttcps_timer_clkevent(x) \
		container_of(x, struct xttcps_timer_clockevent, ce)

/**
 * xttcps_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void xttcps_set_interval(struct xttcps_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
	ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);

	__raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);

	/*
	 * Reset the counter (0x10) so that it starts from 0, one-shot
	 * mode makes this needed for timing to be right.
	 */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
}

/**
 * xttcps_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the xttcps_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
{
	struct xttcps_timer_clockevent *xttce = dev_id;
	struct xttcps_timer *timer = &xttce->xttc;

	/* Acknowledge the interrupt and call event handler */
	__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);

	xttce->ce.event_handler(&xttce->ce);

	return IRQ_HANDLED;
}

/**
 * __xttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static cycle_t __xttc_clocksource_read(struct clocksource *cs)
{
	struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;

	return (cycle_t)__raw_readl(timer->base_addr +
				XTTCPS_COUNT_VAL_OFFSET);
}

/**
 * xttcps_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int xttcps_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
	struct xttcps_timer *timer = &xttce->xttc;

	xttcps_set_interval(timer, cycles);
	return 0;
}

/**
 * xttcps_set_mode - Sets the mode of timer
 *
 * @mode:	Mode to be set
 * @evt:	Address of clock event instance
 **/
static void xttcps_set_mode(enum clock_event_mode mode,
					struct clock_event_device *evt)
{
	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
	struct xttcps_timer *timer = &xttce->xttc;
	u32 ctrl_reg;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		xttcps_set_interval(timer,
				     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
						       PRESCALE * HZ));
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl_reg = __raw_readl(timer->base_addr +
					XTTCPS_CNT_CNTRL_OFFSET);
		ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
		break;
	case CLOCK_EVT_MODE_RESUME:
		ctrl_reg = __raw_readl(timer->base_addr +
					XTTCPS_CNT_CNTRL_OFFSET);
		ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
		break;
	}
}

static void __init zynq_ttc_setup_clocksource(struct device_node *np,
					     void __iomem *base)
{
	struct xttcps_timer_clocksource *ttccs;
	struct clk *clk;
	int err;
	u32 reg;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (WARN_ON(!ttccs))
		return;

	err = of_property_read_u32(np, "reg", &reg);
	if (WARN_ON(err))
		return;

	clk = of_clk_get_by_name(np, "cpu_1x");
	if (WARN_ON(IS_ERR(clk)))
		return;

	err = clk_prepare_enable(clk);
	if (WARN_ON(err))
		return;

	ttccs->xttc.base_addr = base + reg * 4;

	ttccs->cs.name = np->name;
	ttccs->cs.rating = 200;
	ttccs->cs.read = __xttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	__raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
	__raw_writel(CNT_CNTRL_RESET,
		     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
	if (WARN_ON(err))
		return;
}

static void __init zynq_ttc_setup_clockevent(struct device_node *np,
					    void __iomem *base)
{
	struct xttcps_timer_clockevent *ttcce;
	int err, irq;
	u32 reg;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (WARN_ON(!ttcce))
		return;

	err = of_property_read_u32(np, "reg", &reg);
	if (WARN_ON(err))
		return;

	ttcce->xttc.base_addr = base + reg * 4;

	ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
	if (WARN_ON(IS_ERR(ttcce->clk)))
		return;

	err = clk_prepare_enable(ttcce->clk);
	if (WARN_ON(err))
		return;

	irq = irq_of_parse_and_map(np, 0);
	if (WARN_ON(!irq))
		return;

	ttcce->ce.name = np->name;
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = xttcps_set_next_event;
	ttcce->ce.set_mode = xttcps_set_mode;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;
	ttcce->ce.cpumask = cpu_possible_mask;

	__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
	__raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);

	err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
			  np->name, ttcce);
	if (WARN_ON(err))
		return;

	clockevents_config_and_register(&ttcce->ce,
					clk_get_rate(ttcce->clk) / PRESCALE,
					1, 0xfffe);
}

static const __initconst struct of_device_id zynq_ttc_match[] = {
	{ .compatible = "xlnx,ttc-counter-clocksource",
		.data = zynq_ttc_setup_clocksource, },
	{ .compatible = "xlnx,ttc-counter-clockevent",
		.data = zynq_ttc_setup_clockevent, },
	{}
};

/**
 * xttcps_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 **/
void __init xttcps_timer_init(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "xlnx,ttc") {
		struct device_node *np_chld;
		void __iomem *base;

		base = of_iomap(np, 0);
		if (WARN_ON(!base))
			return;

		for_each_available_child_of_node(np, np_chld) {
			int (*cb)(struct device_node *np, void __iomem *base);
			const struct of_device_id *match;

			match = of_match_node(zynq_ttc_match, np_chld);
			if (match) {
				cb = match->data;
				cb(np_chld, base);
			}
		}
	}
}
Commit	Line	Data
b85a3ef4 JL	1	/*
	2	* This file contains driver for the Xilinx PS Timer Counter IP.
	3	*
	4	* Copyright (C) 2011 Xilinx
	5	*
	6	* based on arch/mips/kernel/time.c timer driver
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
b85a3ef4	18	#include <linux/interrupt.h>
b85a3ef4	19	#include <linux/clockchips.h>
91dc985c JC	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/slab.h>
	23	#include <linux/clk-provider.h>
b85a3ef4 JL	24	#include "common.h"
b85a3ef4 JL	25
b85a3ef4 JL	26	/*
	27	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	28	* and use same offsets for Timer 2
	29	*/
d16aaf47 SB	30	#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	31	#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	32	#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
f184c5ca	33	#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
f184c5ca SB	34	#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	35	#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
	36
	37	#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1
b85a3ef4	38
03377e58 SB	39	/*
03377e58 SB	40	* Setup the timers to use pre-scaling, using a fixed value for now that will
91dc985c JC	41	* work across most input frequency, but it may need to be more dynamic
	42	*/
	43	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	44	#define PRESCALE 2048 /* The exponent must match this */
	45	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	46	#define CLK_CNTRL_PRESCALE_EN 1
	47	#define CNT_CNTRL_RESET (1<<4)
b85a3ef4 JL	48
b85a3ef4 JL	49	/**
f184c5ca	50	* struct xttcps_timer - This definition defines local timer structure
b85a3ef4 JL	51	*
	52	* @base_addr: Base address of timer
	53	**/
f184c5ca	54	struct xttcps_timer {
91dc985c JC	55	void __iomem *base_addr;
	56	};
	57
f184c5ca SB	58	struct xttcps_timer_clocksource {
f184c5ca SB	59	struct xttcps_timer xttc;
91dc985c	60	struct clocksource cs;
b85a3ef4 JL	61	};
b85a3ef4 JL	62
f184c5ca SB	63	#define to_xttcps_timer_clksrc(x) \
f184c5ca SB	64	container_of(x, struct xttcps_timer_clocksource, cs)
91dc985c	65
f184c5ca SB	66	struct xttcps_timer_clockevent {
f184c5ca SB	67	struct xttcps_timer xttc;
91dc985c JC	68	struct clock_event_device ce;
	69	struct clk *clk;
	70	};
	71
f184c5ca SB	72	#define to_xttcps_timer_clkevent(x) \
f184c5ca SB	73	container_of(x, struct xttcps_timer_clockevent, ce)
b85a3ef4 JL	74
b85a3ef4 JL	75	/**
f184c5ca	76	* xttcps_set_interval - Set the timer interval value
b85a3ef4 JL	77	*
	78	* @timer: Pointer to the timer instance
	79	* @cycles: Timer interval ticks
	80	**/
f184c5ca	81	static void xttcps_set_interval(struct xttcps_timer *timer,
b85a3ef4 JL	82	unsigned long cycles)
	83	{
	84	u32 ctrl_reg;
	85
	86	/* Disable the counter, set the counter value and re-enable counter */
f184c5ca SB	87	ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
	88	ctrl_reg \|= XTTCPS_CNT_CNTRL_DISABLE_MASK;
	89	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4	90
f184c5ca	91	__raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
b85a3ef4	92
03377e58 SB	93	/*
	94	* Reset the counter (0x10) so that it starts from 0, one-shot
	95	* mode makes this needed for timing to be right.
	96	*/
91dc985c	97	ctrl_reg \|= CNT_CNTRL_RESET;
f184c5ca SB	98	ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
f184c5ca SB	99	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4 JL	100	}
	101
	102	/**
f184c5ca	103	* xttcps_clock_event_interrupt - Clock event timer interrupt handler
b85a3ef4 JL	104	*
b85a3ef4 JL	105	* @irq: IRQ number of the Timer
f184c5ca	106	* @dev_id: void pointer to the xttcps_timer instance
b85a3ef4 JL	107	*
	108	* returns: Always IRQ_HANDLED - success
	109	**/
f184c5ca	110	static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
b85a3ef4	111	{
f184c5ca SB	112	struct xttcps_timer_clockevent *xttce = dev_id;
f184c5ca SB	113	struct xttcps_timer *timer = &xttce->xttc;
b85a3ef4 JL	114
b85a3ef4 JL	115	/* Acknowledge the interrupt and call event handler */
af7f032d	116	__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
b85a3ef4	117
91dc985c	118	xttce->ce.event_handler(&xttce->ce);
b85a3ef4 JL	119
	120	return IRQ_HANDLED;
	121	}
	122
b85a3ef4	123	/**
91dc985c	124	* __xttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	125	*
	126	* returns: Current timer counter register value
	127	**/
91dc985c	128	static cycle_t __xttc_clocksource_read(struct clocksource *cs)
b85a3ef4	129	{
f184c5ca	130	struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
b85a3ef4 JL	131
b85a3ef4 JL	132	return (cycle_t)__raw_readl(timer->base_addr +
f184c5ca	133	XTTCPS_COUNT_VAL_OFFSET);
b85a3ef4 JL	134	}
b85a3ef4 JL	135
b85a3ef4	136	/**
f184c5ca	137	* xttcps_set_next_event - Sets the time interval for next event
b85a3ef4 JL	138	*
	139	* @cycles: Timer interval ticks
	140	* @evt: Address of clock event instance
	141	*
	142	* returns: Always 0 - success
	143	**/
f184c5ca	144	static int xttcps_set_next_event(unsigned long cycles,
b85a3ef4 JL	145	struct clock_event_device *evt)
b85a3ef4 JL	146	{
f184c5ca SB	147	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
f184c5ca SB	148	struct xttcps_timer *timer = &xttce->xttc;
b85a3ef4	149
f184c5ca	150	xttcps_set_interval(timer, cycles);
b85a3ef4 JL	151	return 0;
	152	}
	153
	154	/**
f184c5ca	155	* xttcps_set_mode - Sets the mode of timer
b85a3ef4 JL	156	*
	157	* @mode: Mode to be set
	158	* @evt: Address of clock event instance
	159	**/
f184c5ca	160	static void xttcps_set_mode(enum clock_event_mode mode,
b85a3ef4 JL	161	struct clock_event_device *evt)
b85a3ef4 JL	162	{
f184c5ca SB	163	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
f184c5ca SB	164	struct xttcps_timer *timer = &xttce->xttc;
b85a3ef4 JL	165	u32 ctrl_reg;
	166
	167	switch (mode) {
	168	case CLOCK_EVT_MODE_PERIODIC:
f184c5ca	169	xttcps_set_interval(timer,
91dc985c JC	170	DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
91dc985c JC	171	PRESCALE * HZ));
b85a3ef4 JL	172	break;
	173	case CLOCK_EVT_MODE_ONESHOT:
	174	case CLOCK_EVT_MODE_UNUSED:
	175	case CLOCK_EVT_MODE_SHUTDOWN:
	176	ctrl_reg = __raw_readl(timer->base_addr +
f184c5ca SB	177	XTTCPS_CNT_CNTRL_OFFSET);
f184c5ca SB	178	ctrl_reg \|= XTTCPS_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	179	__raw_writel(ctrl_reg,
f184c5ca	180	timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4 JL	181	break;
	182	case CLOCK_EVT_MODE_RESUME:
	183	ctrl_reg = __raw_readl(timer->base_addr +
f184c5ca SB	184	XTTCPS_CNT_CNTRL_OFFSET);
f184c5ca SB	185	ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	186	__raw_writel(ctrl_reg,
f184c5ca	187	timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4 JL	188	break;
	189	}
	190	}
	191
91dc985c JC	192	static void __init zynq_ttc_setup_clocksource(struct device_node *np,
	193	void __iomem *base)
	194	{
f184c5ca	195	struct xttcps_timer_clocksource *ttccs;
91dc985c JC	196	struct clk *clk;
	197	int err;
	198	u32 reg;
	199
	200	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	201	if (WARN_ON(!ttccs))
	202	return;
	203
	204	err = of_property_read_u32(np, "reg", &reg);
	205	if (WARN_ON(err))
	206	return;
	207
	208	clk = of_clk_get_by_name(np, "cpu_1x");
	209	if (WARN_ON(IS_ERR(clk)))
	210	return;
	211
	212	err = clk_prepare_enable(clk);
	213	if (WARN_ON(err))
	214	return;
	215
	216	ttccs->xttc.base_addr = base + reg * 4;
	217
	218	ttccs->cs.name = np->name;
	219	ttccs->cs.rating = 200;
	220	ttccs->cs.read = __xttc_clocksource_read;
	221	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	222	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	223
f184c5ca	224	__raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
91dc985c	225	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
f184c5ca	226	ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
91dc985c	227	__raw_writel(CNT_CNTRL_RESET,
f184c5ca	228	ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
91dc985c JC	229
	230	err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
	231	if (WARN_ON(err))
	232	return;
	233	}
	234
	235	static void __init zynq_ttc_setup_clockevent(struct device_node *np,
	236	void __iomem *base)
	237	{
f184c5ca	238	struct xttcps_timer_clockevent *ttcce;
91dc985c JC	239	int err, irq;
	240	u32 reg;
	241
	242	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	243	if (WARN_ON(!ttcce))
	244	return;
	245
	246	err = of_property_read_u32(np, "reg", &reg);
	247	if (WARN_ON(err))
	248	return;
	249
	250	ttcce->xttc.base_addr = base + reg * 4;
	251
	252	ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
	253	if (WARN_ON(IS_ERR(ttcce->clk)))
	254	return;
	255
	256	err = clk_prepare_enable(ttcce->clk);
	257	if (WARN_ON(err))
	258	return;
	259
	260	irq = irq_of_parse_and_map(np, 0);
	261	if (WARN_ON(!irq))
	262	return;
	263
	264	ttcce->ce.name = np->name;
	265	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
f184c5ca SB	266	ttcce->ce.set_next_event = xttcps_set_next_event;
f184c5ca SB	267	ttcce->ce.set_mode = xttcps_set_mode;
91dc985c JC	268	ttcce->ce.rating = 200;
91dc985c JC	269	ttcce->ce.irq = irq;
87e4ee75	270	ttcce->ce.cpumask = cpu_possible_mask;
91dc985c	271
f184c5ca	272	__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
91dc985c	273	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
f184c5ca SB	274	ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
f184c5ca SB	275	__raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
91dc985c	276
f184c5ca	277	err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
91dc985c JC	278	np->name, ttcce);
	279	if (WARN_ON(err))
	280	return;
	281
	282	clockevents_config_and_register(&ttcce->ce,
	283	clk_get_rate(ttcce->clk) / PRESCALE,
	284	1, 0xfffe);
	285	}
	286
	287	static const __initconst struct of_device_id zynq_ttc_match[] = {
	288	{ .compatible = "xlnx,ttc-counter-clocksource",
	289	.data = zynq_ttc_setup_clocksource, },
	290	{ .compatible = "xlnx,ttc-counter-clockevent",
	291	.data = zynq_ttc_setup_clockevent, },
	292	{}
b85a3ef4 JL	293	};
	294
	295	/**
f184c5ca	296	* xttcps_timer_init - Initialize the timer
b85a3ef4 JL	297	*
	298	* Initializes the timer hardware and register the clock source and clock event
	299	* timers with Linux kernal timer framework
	300	**/
f184c5ca	301	void __init xttcps_timer_init(void)
b85a3ef4	302	{
91dc985c JC	303	struct device_node *np;
	304
	305	for_each_compatible_node(np, NULL, "xlnx,ttc") {
	306	struct device_node *np_chld;
	307	void __iomem *base;
	308
	309	base = of_iomap(np, 0);
	310	if (WARN_ON(!base))
	311	return;
	312
	313	for_each_available_child_of_node(np, np_chld) {
	314	int (cb)(struct device_node np, void __iomem *base);
	315	const struct of_device_id *match;
	316
	317	match = of_match_node(zynq_ttc_match, np_chld);
	318	if (match) {
	319	cb = match->data;
	320	cb(np_chld, base);
	321	}
	322	}
	323	}
b85a3ef4	324	}