Commit | Line | Data |
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b85a3ef4 | 1 | /* |
9e09dc5f | 2 | * This file contains driver for the Cadence Triple Timer Counter Rev 06 |
b85a3ef4 | 3 | * |
e932900a | 4 | * Copyright (C) 2011-2013 Xilinx |
b85a3ef4 JL |
5 | * |
6 | * based on arch/mips/kernel/time.c timer driver | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
e932900a | 18 | #include <linux/clk.h> |
b85a3ef4 | 19 | #include <linux/interrupt.h> |
b85a3ef4 | 20 | #include <linux/clockchips.h> |
91dc985c JC |
21 | #include <linux/of_address.h> |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/clk-provider.h> | |
b85a3ef4 | 25 | |
e932900a MS |
26 | /* |
27 | * This driver configures the 2 16-bit count-up timers as follows: | |
28 | * | |
29 | * T1: Timer 1, clocksource for generic timekeeping | |
30 | * T2: Timer 2, clockevent source for hrtimers | |
31 | * T3: Timer 3, <unused> | |
32 | * | |
33 | * The input frequency to the timer module for emulation is 2.5MHz which is | |
34 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, | |
35 | * the timers are clocked at 78.125KHz (12.8 us resolution). | |
36 | ||
37 | * The input frequency to the timer module in silicon is configurable and | |
38 | * obtained from device tree. The pre-scaler of 32 is used. | |
39 | */ | |
40 | ||
b85a3ef4 JL |
41 | /* |
42 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 | |
43 | * and use same offsets for Timer 2 | |
44 | */ | |
9e09dc5f MS |
45 | #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
46 | #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ | |
47 | #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ | |
48 | #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ | |
49 | #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ | |
50 | #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ | |
f184c5ca | 51 | |
9e09dc5f | 52 | #define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
b85a3ef4 | 53 | |
03377e58 SB |
54 | /* |
55 | * Setup the timers to use pre-scaling, using a fixed value for now that will | |
91dc985c JC |
56 | * work across most input frequency, but it may need to be more dynamic |
57 | */ | |
58 | #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ | |
59 | #define PRESCALE 2048 /* The exponent must match this */ | |
60 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) | |
61 | #define CLK_CNTRL_PRESCALE_EN 1 | |
e932900a | 62 | #define CNT_CNTRL_RESET (1 << 4) |
b85a3ef4 JL |
63 | |
64 | /** | |
9e09dc5f | 65 | * struct ttc_timer - This definition defines local timer structure |
b85a3ef4 JL |
66 | * |
67 | * @base_addr: Base address of timer | |
e932900a MS |
68 | * @clk: Associated clock source |
69 | * @clk_rate_change_nb Notifier block for clock rate changes | |
70 | */ | |
9e09dc5f | 71 | struct ttc_timer { |
e932900a MS |
72 | void __iomem *base_addr; |
73 | struct clk *clk; | |
74 | struct notifier_block clk_rate_change_nb; | |
91dc985c JC |
75 | }; |
76 | ||
9e09dc5f MS |
77 | #define to_ttc_timer(x) \ |
78 | container_of(x, struct ttc_timer, clk_rate_change_nb) | |
e932900a | 79 | |
9e09dc5f MS |
80 | struct ttc_timer_clocksource { |
81 | struct ttc_timer ttc; | |
91dc985c | 82 | struct clocksource cs; |
b85a3ef4 JL |
83 | }; |
84 | ||
9e09dc5f MS |
85 | #define to_ttc_timer_clksrc(x) \ |
86 | container_of(x, struct ttc_timer_clocksource, cs) | |
91dc985c | 87 | |
9e09dc5f MS |
88 | struct ttc_timer_clockevent { |
89 | struct ttc_timer ttc; | |
91dc985c | 90 | struct clock_event_device ce; |
91dc985c JC |
91 | }; |
92 | ||
9e09dc5f MS |
93 | #define to_ttc_timer_clkevent(x) \ |
94 | container_of(x, struct ttc_timer_clockevent, ce) | |
b85a3ef4 JL |
95 | |
96 | /** | |
9e09dc5f | 97 | * ttc_set_interval - Set the timer interval value |
b85a3ef4 JL |
98 | * |
99 | * @timer: Pointer to the timer instance | |
100 | * @cycles: Timer interval ticks | |
101 | **/ | |
9e09dc5f | 102 | static void ttc_set_interval(struct ttc_timer *timer, |
b85a3ef4 JL |
103 | unsigned long cycles) |
104 | { | |
105 | u32 ctrl_reg; | |
106 | ||
107 | /* Disable the counter, set the counter value and re-enable counter */ | |
9e09dc5f MS |
108 | ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
109 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
110 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
b85a3ef4 | 111 | |
9e09dc5f | 112 | __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
b85a3ef4 | 113 | |
03377e58 SB |
114 | /* |
115 | * Reset the counter (0x10) so that it starts from 0, one-shot | |
116 | * mode makes this needed for timing to be right. | |
117 | */ | |
91dc985c | 118 | ctrl_reg |= CNT_CNTRL_RESET; |
9e09dc5f MS |
119 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
120 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
b85a3ef4 JL |
121 | } |
122 | ||
123 | /** | |
9e09dc5f | 124 | * ttc_clock_event_interrupt - Clock event timer interrupt handler |
b85a3ef4 JL |
125 | * |
126 | * @irq: IRQ number of the Timer | |
9e09dc5f | 127 | * @dev_id: void pointer to the ttc_timer instance |
b85a3ef4 JL |
128 | * |
129 | * returns: Always IRQ_HANDLED - success | |
130 | **/ | |
9e09dc5f | 131 | static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
b85a3ef4 | 132 | { |
9e09dc5f MS |
133 | struct ttc_timer_clockevent *ttce = dev_id; |
134 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
135 | |
136 | /* Acknowledge the interrupt and call event handler */ | |
9e09dc5f | 137 | __raw_readl(timer->base_addr + TTC_ISR_OFFSET); |
b85a3ef4 | 138 | |
9e09dc5f | 139 | ttce->ce.event_handler(&ttce->ce); |
b85a3ef4 JL |
140 | |
141 | return IRQ_HANDLED; | |
142 | } | |
143 | ||
b85a3ef4 | 144 | /** |
9e09dc5f | 145 | * __ttc_clocksource_read - Reads the timer counter register |
b85a3ef4 JL |
146 | * |
147 | * returns: Current timer counter register value | |
148 | **/ | |
9e09dc5f | 149 | static cycle_t __ttc_clocksource_read(struct clocksource *cs) |
b85a3ef4 | 150 | { |
9e09dc5f | 151 | struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
b85a3ef4 JL |
152 | |
153 | return (cycle_t)__raw_readl(timer->base_addr + | |
9e09dc5f | 154 | TTC_COUNT_VAL_OFFSET); |
b85a3ef4 JL |
155 | } |
156 | ||
b85a3ef4 | 157 | /** |
9e09dc5f | 158 | * ttc_set_next_event - Sets the time interval for next event |
b85a3ef4 JL |
159 | * |
160 | * @cycles: Timer interval ticks | |
161 | * @evt: Address of clock event instance | |
162 | * | |
163 | * returns: Always 0 - success | |
164 | **/ | |
9e09dc5f | 165 | static int ttc_set_next_event(unsigned long cycles, |
b85a3ef4 JL |
166 | struct clock_event_device *evt) |
167 | { | |
9e09dc5f MS |
168 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
169 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 | 170 | |
9e09dc5f | 171 | ttc_set_interval(timer, cycles); |
b85a3ef4 JL |
172 | return 0; |
173 | } | |
174 | ||
175 | /** | |
9e09dc5f | 176 | * ttc_set_mode - Sets the mode of timer |
b85a3ef4 JL |
177 | * |
178 | * @mode: Mode to be set | |
179 | * @evt: Address of clock event instance | |
180 | **/ | |
9e09dc5f | 181 | static void ttc_set_mode(enum clock_event_mode mode, |
b85a3ef4 JL |
182 | struct clock_event_device *evt) |
183 | { | |
9e09dc5f MS |
184 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
185 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
186 | u32 ctrl_reg; |
187 | ||
188 | switch (mode) { | |
189 | case CLOCK_EVT_MODE_PERIODIC: | |
9e09dc5f MS |
190 | ttc_set_interval(timer, |
191 | DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), | |
e932900a | 192 | PRESCALE * HZ)); |
b85a3ef4 JL |
193 | break; |
194 | case CLOCK_EVT_MODE_ONESHOT: | |
195 | case CLOCK_EVT_MODE_UNUSED: | |
196 | case CLOCK_EVT_MODE_SHUTDOWN: | |
197 | ctrl_reg = __raw_readl(timer->base_addr + | |
9e09dc5f MS |
198 | TTC_CNT_CNTRL_OFFSET); |
199 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
b85a3ef4 | 200 | __raw_writel(ctrl_reg, |
9e09dc5f | 201 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
202 | break; |
203 | case CLOCK_EVT_MODE_RESUME: | |
204 | ctrl_reg = __raw_readl(timer->base_addr + | |
9e09dc5f MS |
205 | TTC_CNT_CNTRL_OFFSET); |
206 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; | |
b85a3ef4 | 207 | __raw_writel(ctrl_reg, |
9e09dc5f | 208 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
209 | break; |
210 | } | |
211 | } | |
212 | ||
9e09dc5f | 213 | static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
e932900a MS |
214 | unsigned long event, void *data) |
215 | { | |
216 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
217 | struct ttc_timer *ttc = to_ttc_timer(nb); |
218 | struct ttc_timer_clocksource *ttccs = container_of(ttc, | |
219 | struct ttc_timer_clocksource, ttc); | |
e932900a MS |
220 | |
221 | switch (event) { | |
222 | case POST_RATE_CHANGE: | |
223 | /* | |
224 | * Do whatever is necessary to maintain a proper time base | |
225 | * | |
226 | * I cannot find a way to adjust the currently used clocksource | |
227 | * to the new frequency. __clocksource_updatefreq_hz() sounds | |
228 | * good, but does not work. Not sure what's that missing. | |
229 | * | |
230 | * This approach works, but triggers two clocksource switches. | |
231 | * The first after unregister to clocksource jiffies. And | |
232 | * another one after the register to the newly registered timer. | |
233 | * | |
234 | * Alternatively we could 'waste' another HW timer to ping pong | |
235 | * between clock sources. That would also use one register and | |
236 | * one unregister call, but only trigger one clocksource switch | |
237 | * for the cost of another HW timer used by the OS. | |
238 | */ | |
9e09dc5f MS |
239 | clocksource_unregister(&ttccs->cs); |
240 | clocksource_register_hz(&ttccs->cs, | |
e932900a MS |
241 | ndata->new_rate / PRESCALE); |
242 | /* fall through */ | |
243 | case PRE_RATE_CHANGE: | |
244 | case ABORT_RATE_CHANGE: | |
245 | default: | |
246 | return NOTIFY_DONE; | |
247 | } | |
248 | } | |
249 | ||
9e09dc5f | 250 | static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) |
91dc985c | 251 | { |
9e09dc5f | 252 | struct ttc_timer_clocksource *ttccs; |
91dc985c | 253 | int err; |
91dc985c JC |
254 | |
255 | ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); | |
256 | if (WARN_ON(!ttccs)) | |
257 | return; | |
258 | ||
9e09dc5f | 259 | ttccs->ttc.clk = clk; |
91dc985c | 260 | |
9e09dc5f | 261 | err = clk_prepare_enable(ttccs->ttc.clk); |
c5263bb8 MS |
262 | if (WARN_ON(err)) { |
263 | kfree(ttccs); | |
91dc985c | 264 | return; |
c5263bb8 | 265 | } |
91dc985c | 266 | |
9e09dc5f MS |
267 | ttccs->ttc.clk_rate_change_nb.notifier_call = |
268 | ttc_rate_change_clocksource_cb; | |
269 | ttccs->ttc.clk_rate_change_nb.next = NULL; | |
270 | if (clk_notifier_register(ttccs->ttc.clk, | |
271 | &ttccs->ttc.clk_rate_change_nb)) | |
e932900a | 272 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 273 | |
9e09dc5f MS |
274 | ttccs->ttc.base_addr = base; |
275 | ttccs->cs.name = "ttc_clocksource"; | |
91dc985c | 276 | ttccs->cs.rating = 200; |
9e09dc5f | 277 | ttccs->cs.read = __ttc_clocksource_read; |
91dc985c JC |
278 | ttccs->cs.mask = CLOCKSOURCE_MASK(16); |
279 | ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
280 | ||
e932900a MS |
281 | /* |
282 | * Setup the clock source counter to be an incrementing counter | |
283 | * with no interrupt and it rolls over at 0xFFFF. Pre-scale | |
284 | * it by 32 also. Let it start running now. | |
285 | */ | |
9e09dc5f | 286 | __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); |
91dc985c | 287 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f | 288 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
91dc985c | 289 | __raw_writel(CNT_CNTRL_RESET, |
9e09dc5f | 290 | ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 291 | |
e932900a | 292 | err = clocksource_register_hz(&ttccs->cs, |
9e09dc5f | 293 | clk_get_rate(ttccs->ttc.clk) / PRESCALE); |
c5263bb8 MS |
294 | if (WARN_ON(err)) { |
295 | kfree(ttccs); | |
91dc985c | 296 | return; |
c5263bb8 | 297 | } |
91dc985c JC |
298 | } |
299 | ||
9e09dc5f | 300 | static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
e932900a MS |
301 | unsigned long event, void *data) |
302 | { | |
303 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
304 | struct ttc_timer *ttc = to_ttc_timer(nb); |
305 | struct ttc_timer_clockevent *ttcce = container_of(ttc, | |
306 | struct ttc_timer_clockevent, ttc); | |
e932900a MS |
307 | |
308 | switch (event) { | |
309 | case POST_RATE_CHANGE: | |
310 | { | |
311 | unsigned long flags; | |
312 | ||
313 | /* | |
314 | * clockevents_update_freq should be called with IRQ disabled on | |
315 | * the CPU the timer provides events for. The timer we use is | |
316 | * common to both CPUs, not sure if we need to run on both | |
317 | * cores. | |
318 | */ | |
319 | local_irq_save(flags); | |
9e09dc5f | 320 | clockevents_update_freq(&ttcce->ce, |
e932900a MS |
321 | ndata->new_rate / PRESCALE); |
322 | local_irq_restore(flags); | |
323 | ||
324 | /* fall through */ | |
325 | } | |
326 | case PRE_RATE_CHANGE: | |
327 | case ABORT_RATE_CHANGE: | |
328 | default: | |
329 | return NOTIFY_DONE; | |
330 | } | |
331 | } | |
332 | ||
9e09dc5f | 333 | static void __init ttc_setup_clockevent(struct clk *clk, |
e932900a | 334 | void __iomem *base, u32 irq) |
91dc985c | 335 | { |
9e09dc5f | 336 | struct ttc_timer_clockevent *ttcce; |
e932900a | 337 | int err; |
91dc985c JC |
338 | |
339 | ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); | |
340 | if (WARN_ON(!ttcce)) | |
341 | return; | |
342 | ||
9e09dc5f | 343 | ttcce->ttc.clk = clk; |
91dc985c | 344 | |
9e09dc5f | 345 | err = clk_prepare_enable(ttcce->ttc.clk); |
c5263bb8 MS |
346 | if (WARN_ON(err)) { |
347 | kfree(ttcce); | |
91dc985c | 348 | return; |
c5263bb8 | 349 | } |
91dc985c | 350 | |
9e09dc5f MS |
351 | ttcce->ttc.clk_rate_change_nb.notifier_call = |
352 | ttc_rate_change_clockevent_cb; | |
353 | ttcce->ttc.clk_rate_change_nb.next = NULL; | |
354 | if (clk_notifier_register(ttcce->ttc.clk, | |
355 | &ttcce->ttc.clk_rate_change_nb)) | |
e932900a | 356 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 357 | |
9e09dc5f MS |
358 | ttcce->ttc.base_addr = base; |
359 | ttcce->ce.name = "ttc_clockevent"; | |
91dc985c | 360 | ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
9e09dc5f MS |
361 | ttcce->ce.set_next_event = ttc_set_next_event; |
362 | ttcce->ce.set_mode = ttc_set_mode; | |
91dc985c JC |
363 | ttcce->ce.rating = 200; |
364 | ttcce->ce.irq = irq; | |
87e4ee75 | 365 | ttcce->ce.cpumask = cpu_possible_mask; |
91dc985c | 366 | |
e932900a MS |
367 | /* |
368 | * Setup the clock event timer to be an interval timer which | |
369 | * is prescaled by 32 using the interval interrupt. Leave it | |
370 | * disabled for now. | |
371 | */ | |
9e09dc5f | 372 | __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 373 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f MS |
374 | ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
375 | __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); | |
91dc985c | 376 | |
9e09dc5f | 377 | err = request_irq(irq, ttc_clock_event_interrupt, |
e932900a MS |
378 | IRQF_DISABLED | IRQF_TIMER, |
379 | ttcce->ce.name, ttcce); | |
c5263bb8 MS |
380 | if (WARN_ON(err)) { |
381 | kfree(ttcce); | |
91dc985c | 382 | return; |
c5263bb8 | 383 | } |
91dc985c JC |
384 | |
385 | clockevents_config_and_register(&ttcce->ce, | |
9e09dc5f | 386 | clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); |
91dc985c JC |
387 | } |
388 | ||
b85a3ef4 | 389 | /** |
9e09dc5f | 390 | * ttc_timer_init - Initialize the timer |
b85a3ef4 JL |
391 | * |
392 | * Initializes the timer hardware and register the clock source and clock event | |
393 | * timers with Linux kernal timer framework | |
e932900a | 394 | */ |
9e09dc5f | 395 | static void __init ttc_timer_init(struct device_node *timer) |
e932900a MS |
396 | { |
397 | unsigned int irq; | |
398 | void __iomem *timer_baseaddr; | |
399 | struct clk *clk; | |
c5263bb8 MS |
400 | static int initialized; |
401 | ||
402 | if (initialized) | |
403 | return; | |
404 | ||
405 | initialized = 1; | |
e932900a MS |
406 | |
407 | /* | |
408 | * Get the 1st Triple Timer Counter (TTC) block from the device tree | |
409 | * and use it. Note that the event timer uses the interrupt and it's the | |
410 | * 2nd TTC hence the irq_of_parse_and_map(,1) | |
411 | */ | |
412 | timer_baseaddr = of_iomap(timer, 0); | |
413 | if (!timer_baseaddr) { | |
414 | pr_err("ERROR: invalid timer base address\n"); | |
415 | BUG(); | |
416 | } | |
417 | ||
418 | irq = irq_of_parse_and_map(timer, 1); | |
419 | if (irq <= 0) { | |
420 | pr_err("ERROR: invalid interrupt number\n"); | |
421 | BUG(); | |
422 | } | |
423 | ||
424 | clk = of_clk_get_by_name(timer, "cpu_1x"); | |
425 | if (IS_ERR(clk)) { | |
426 | pr_err("ERROR: timer input clock not found\n"); | |
427 | BUG(); | |
428 | } | |
429 | ||
9e09dc5f MS |
430 | ttc_setup_clocksource(clk, timer_baseaddr); |
431 | ttc_setup_clockevent(clk, timer_baseaddr + 4, irq); | |
e932900a MS |
432 | |
433 | pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); | |
434 | } | |
435 | ||
9e09dc5f | 436 | CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |