[deliverable/linux.git] / arch / arm / mach-zynq / timer.c

/*
 * This file contains driver for the Xilinx PS Timer Counter IP.
 *
 *  Copyright (C) 2011 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk-provider.h>

#include "common.h"

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define XTTCPS_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define XTTCPS_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define XTTCPS_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define XTTCPS_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define XTTCPS_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define XTTCPS_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define XTTCPS_CNT_CNTRL_DISABLE_MASK	0x1

/* Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1<<4)

/**
 * struct xttcps_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 **/
struct xttcps_timer {
	void __iomem	*base_addr;
};

struct xttcps_timer_clocksource {
	struct xttcps_timer	xttc;
	struct clocksource	cs;
};

#define to_xttcps_timer_clksrc(x) \
		container_of(x, struct xttcps_timer_clocksource, cs)

struct xttcps_timer_clockevent {
	struct xttcps_timer		xttc;
	struct clock_event_device	ce;
	struct clk			*clk;
};

#define to_xttcps_timer_clkevent(x) \
		container_of(x, struct xttcps_timer_clockevent, ce)

/**
 * xttcps_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void xttcps_set_interval(struct xttcps_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
	ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);

	__raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);

	/* Reset the counter (0x10) so that it starts from 0, one-shot
	   mode makes this needed for timing to be right. */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
}

/**
 * xttcps_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the xttcps_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
{
	struct xttcps_timer_clockevent *xttce = dev_id;
	struct xttcps_timer *timer = &xttce->xttc;

	/* Acknowledge the interrupt and call event handler */
	__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);

	xttce->ce.event_handler(&xttce->ce);

	return IRQ_HANDLED;
}

/**
 * __xttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static cycle_t __xttc_clocksource_read(struct clocksource *cs)
{
	struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;

	return (cycle_t)__raw_readl(timer->base_addr +
				XTTCPS_COUNT_VAL_OFFSET);
}

/**
 * xttcps_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int xttcps_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
	struct xttcps_timer *timer = &xttce->xttc;

	xttcps_set_interval(timer, cycles);
	return 0;
}

/**
 * xttcps_set_mode - Sets the mode of timer
 *
 * @mode:	Mode to be set
 * @evt:	Address of clock event instance
 **/
static void xttcps_set_mode(enum clock_event_mode mode,
					struct clock_event_device *evt)
{
	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
	struct xttcps_timer *timer = &xttce->xttc;
	u32 ctrl_reg;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		xttcps_set_interval(timer,
				     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
						       PRESCALE * HZ));
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl_reg = __raw_readl(timer->base_addr +
					XTTCPS_CNT_CNTRL_OFFSET);
		ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
		break;
	case CLOCK_EVT_MODE_RESUME:
		ctrl_reg = __raw_readl(timer->base_addr +
					XTTCPS_CNT_CNTRL_OFFSET);
		ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
		break;
	}
}

static void __init zynq_ttc_setup_clocksource(struct device_node *np,
					     void __iomem *base)
{
	struct xttcps_timer_clocksource *ttccs;
	struct clk *clk;
	int err;
	u32 reg;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (WARN_ON(!ttccs))
		return;

	err = of_property_read_u32(np, "reg", &reg);
	if (WARN_ON(err))
		return;

	clk = of_clk_get_by_name(np, "cpu_1x");
	if (WARN_ON(IS_ERR(clk)))
		return;

	err = clk_prepare_enable(clk);
	if (WARN_ON(err))
		return;

	ttccs->xttc.base_addr = base + reg * 4;

	ttccs->cs.name = np->name;
	ttccs->cs.rating = 200;
	ttccs->cs.read = __xttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	__raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
	__raw_writel(CNT_CNTRL_RESET,
		     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
	if (WARN_ON(err))
		return;
}

static void __init zynq_ttc_setup_clockevent(struct device_node *np,
					    void __iomem *base)
{
	struct xttcps_timer_clockevent *ttcce;
	int err, irq;
	u32 reg;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (WARN_ON(!ttcce))
		return;

	err = of_property_read_u32(np, "reg", &reg);
	if (WARN_ON(err))
		return;

	ttcce->xttc.base_addr = base + reg * 4;

	ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
	if (WARN_ON(IS_ERR(ttcce->clk)))
		return;

	err = clk_prepare_enable(ttcce->clk);
	if (WARN_ON(err))
		return;

	irq = irq_of_parse_and_map(np, 0);
	if (WARN_ON(!irq))
		return;

	ttcce->ce.name = np->name;
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = xttcps_set_next_event;
	ttcce->ce.set_mode = xttcps_set_mode;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;

	__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
	__raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);

	err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
			  np->name, ttcce);
	if (WARN_ON(err))
		return;

	clockevents_config_and_register(&ttcce->ce,
					clk_get_rate(ttcce->clk) / PRESCALE,
					1, 0xfffe);
}

static const __initconst struct of_device_id zynq_ttc_match[] = {
	{ .compatible = "xlnx,ttc-counter-clocksource",
		.data = zynq_ttc_setup_clocksource, },
	{ .compatible = "xlnx,ttc-counter-clockevent",
		.data = zynq_ttc_setup_clockevent, },
	{}
};

/**
 * xttcps_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 **/
void __init xttcps_timer_init(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "xlnx,ttc") {
		struct device_node *np_chld;
		void __iomem *base;

		base = of_iomap(np, 0);
		if (WARN_ON(!base))
			return;

		for_each_available_child_of_node(np, np_chld) {
			int (*cb)(struct device_node *np, void __iomem *base);
			const struct of_device_id *match;

			match = of_match_node(zynq_ttc_match, np_chld);
			if (match) {
				cb = match->data;
				cb(np_chld, base);
			}
		}
	}
}
Commit	Line	Data
b85a3ef4 JL	1	/*
	2	* This file contains driver for the Xilinx PS Timer Counter IP.
	3	*
	4	* Copyright (C) 2011 Xilinx
	5	*
	6	* based on arch/mips/kernel/time.c timer driver
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/irq.h>
	22	#include <linux/types.h>
	23	#include <linux/clocksource.h>
	24	#include <linux/clockchips.h>
	25	#include <linux/io.h>
91dc985c JC	26	#include <linux/of.h>
	27	#include <linux/of_address.h>
	28	#include <linux/of_irq.h>
	29	#include <linux/slab.h>
	30	#include <linux/clk-provider.h>
b85a3ef4	31
b85a3ef4 JL	32	#include "common.h"
b85a3ef4 JL	33
b85a3ef4 JL	34	/*
	35	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	36	* and use same offsets for Timer 2
	37	*/
d16aaf47 SB	38	#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	39	#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	40	#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
f184c5ca	41	#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
f184c5ca SB	42	#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	43	#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
	44
	45	#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1
b85a3ef4	46
91dc985c JC	47	/* Setup the timers to use pre-scaling, using a fixed value for now that will
	48	* work across most input frequency, but it may need to be more dynamic
	49	*/
	50	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	51	#define PRESCALE 2048 /* The exponent must match this */
	52	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	53	#define CLK_CNTRL_PRESCALE_EN 1
	54	#define CNT_CNTRL_RESET (1<<4)
b85a3ef4 JL	55
b85a3ef4 JL	56	/**
f184c5ca	57	* struct xttcps_timer - This definition defines local timer structure
b85a3ef4 JL	58	*
	59	* @base_addr: Base address of timer
	60	**/
f184c5ca	61	struct xttcps_timer {
91dc985c JC	62	void __iomem *base_addr;
	63	};
	64
f184c5ca SB	65	struct xttcps_timer_clocksource {
f184c5ca SB	66	struct xttcps_timer xttc;
91dc985c	67	struct clocksource cs;
b85a3ef4 JL	68	};
b85a3ef4 JL	69
f184c5ca SB	70	#define to_xttcps_timer_clksrc(x) \
f184c5ca SB	71	container_of(x, struct xttcps_timer_clocksource, cs)
91dc985c	72
f184c5ca SB	73	struct xttcps_timer_clockevent {
f184c5ca SB	74	struct xttcps_timer xttc;
91dc985c JC	75	struct clock_event_device ce;
	76	struct clk *clk;
	77	};
	78
f184c5ca SB	79	#define to_xttcps_timer_clkevent(x) \
f184c5ca SB	80	container_of(x, struct xttcps_timer_clockevent, ce)
b85a3ef4 JL	81
b85a3ef4 JL	82	/**
f184c5ca	83	* xttcps_set_interval - Set the timer interval value
b85a3ef4 JL	84	*
	85	* @timer: Pointer to the timer instance
	86	* @cycles: Timer interval ticks
	87	**/
f184c5ca	88	static void xttcps_set_interval(struct xttcps_timer *timer,
b85a3ef4 JL	89	unsigned long cycles)
	90	{
	91	u32 ctrl_reg;
	92
	93	/* Disable the counter, set the counter value and re-enable counter */
f184c5ca SB	94	ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
	95	ctrl_reg \|= XTTCPS_CNT_CNTRL_DISABLE_MASK;
	96	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4	97
f184c5ca	98	__raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
b85a3ef4 JL	99
	100	/* Reset the counter (0x10) so that it starts from 0, one-shot
	101	mode makes this needed for timing to be right. */
91dc985c	102	ctrl_reg \|= CNT_CNTRL_RESET;
f184c5ca SB	103	ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
f184c5ca SB	104	__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4 JL	105	}
	106
	107	/**
f184c5ca	108	* xttcps_clock_event_interrupt - Clock event timer interrupt handler
b85a3ef4 JL	109	*
b85a3ef4 JL	110	* @irq: IRQ number of the Timer
f184c5ca	111	* @dev_id: void pointer to the xttcps_timer instance
b85a3ef4 JL	112	*
	113	* returns: Always IRQ_HANDLED - success
	114	**/
f184c5ca	115	static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
b85a3ef4	116	{
f184c5ca SB	117	struct xttcps_timer_clockevent *xttce = dev_id;
f184c5ca SB	118	struct xttcps_timer *timer = &xttce->xttc;
b85a3ef4 JL	119
b85a3ef4 JL	120	/* Acknowledge the interrupt and call event handler */
af7f032d	121	__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
b85a3ef4	122
91dc985c	123	xttce->ce.event_handler(&xttce->ce);
b85a3ef4 JL	124
	125	return IRQ_HANDLED;
	126	}
	127
b85a3ef4	128	/**
91dc985c	129	* __xttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	130	*
	131	* returns: Current timer counter register value
	132	**/
91dc985c	133	static cycle_t __xttc_clocksource_read(struct clocksource *cs)
b85a3ef4	134	{
f184c5ca	135	struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
b85a3ef4 JL	136
b85a3ef4 JL	137	return (cycle_t)__raw_readl(timer->base_addr +
f184c5ca	138	XTTCPS_COUNT_VAL_OFFSET);
b85a3ef4 JL	139	}
b85a3ef4 JL	140
b85a3ef4	141	/**
f184c5ca	142	* xttcps_set_next_event - Sets the time interval for next event
b85a3ef4 JL	143	*
	144	* @cycles: Timer interval ticks
	145	* @evt: Address of clock event instance
	146	*
	147	* returns: Always 0 - success
	148	**/
f184c5ca	149	static int xttcps_set_next_event(unsigned long cycles,
b85a3ef4 JL	150	struct clock_event_device *evt)
b85a3ef4 JL	151	{
f184c5ca SB	152	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
f184c5ca SB	153	struct xttcps_timer *timer = &xttce->xttc;
b85a3ef4	154
f184c5ca	155	xttcps_set_interval(timer, cycles);
b85a3ef4 JL	156	return 0;
	157	}
	158
	159	/**
f184c5ca	160	* xttcps_set_mode - Sets the mode of timer
b85a3ef4 JL	161	*
	162	* @mode: Mode to be set
	163	* @evt: Address of clock event instance
	164	**/
f184c5ca	165	static void xttcps_set_mode(enum clock_event_mode mode,
b85a3ef4 JL	166	struct clock_event_device *evt)
b85a3ef4 JL	167	{
f184c5ca SB	168	struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
f184c5ca SB	169	struct xttcps_timer *timer = &xttce->xttc;
b85a3ef4 JL	170	u32 ctrl_reg;
	171
	172	switch (mode) {
	173	case CLOCK_EVT_MODE_PERIODIC:
f184c5ca	174	xttcps_set_interval(timer,
91dc985c JC	175	DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
91dc985c JC	176	PRESCALE * HZ));
b85a3ef4 JL	177	break;
	178	case CLOCK_EVT_MODE_ONESHOT:
	179	case CLOCK_EVT_MODE_UNUSED:
	180	case CLOCK_EVT_MODE_SHUTDOWN:
	181	ctrl_reg = __raw_readl(timer->base_addr +
f184c5ca SB	182	XTTCPS_CNT_CNTRL_OFFSET);
f184c5ca SB	183	ctrl_reg \|= XTTCPS_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	184	__raw_writel(ctrl_reg,
f184c5ca	185	timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4 JL	186	break;
	187	case CLOCK_EVT_MODE_RESUME:
	188	ctrl_reg = __raw_readl(timer->base_addr +
f184c5ca SB	189	XTTCPS_CNT_CNTRL_OFFSET);
f184c5ca SB	190	ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	191	__raw_writel(ctrl_reg,
f184c5ca	192	timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
b85a3ef4 JL	193	break;
	194	}
	195	}
	196
91dc985c JC	197	static void __init zynq_ttc_setup_clocksource(struct device_node *np,
	198	void __iomem *base)
	199	{
f184c5ca	200	struct xttcps_timer_clocksource *ttccs;
91dc985c JC	201	struct clk *clk;
	202	int err;
	203	u32 reg;
	204
	205	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	206	if (WARN_ON(!ttccs))
	207	return;
	208
	209	err = of_property_read_u32(np, "reg", &reg);
	210	if (WARN_ON(err))
	211	return;
	212
	213	clk = of_clk_get_by_name(np, "cpu_1x");
	214	if (WARN_ON(IS_ERR(clk)))
	215	return;
	216
	217	err = clk_prepare_enable(clk);
	218	if (WARN_ON(err))
	219	return;
	220
	221	ttccs->xttc.base_addr = base + reg * 4;
	222
	223	ttccs->cs.name = np->name;
	224	ttccs->cs.rating = 200;
	225	ttccs->cs.read = __xttc_clocksource_read;
	226	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	227	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	228
f184c5ca	229	__raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
91dc985c	230	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
f184c5ca	231	ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
91dc985c	232	__raw_writel(CNT_CNTRL_RESET,
f184c5ca	233	ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
91dc985c JC	234
	235	err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
	236	if (WARN_ON(err))
	237	return;
	238	}
	239
	240	static void __init zynq_ttc_setup_clockevent(struct device_node *np,
	241	void __iomem *base)
	242	{
f184c5ca	243	struct xttcps_timer_clockevent *ttcce;
91dc985c JC	244	int err, irq;
	245	u32 reg;
	246
	247	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	248	if (WARN_ON(!ttcce))
	249	return;
	250
	251	err = of_property_read_u32(np, "reg", &reg);
	252	if (WARN_ON(err))
	253	return;
	254
	255	ttcce->xttc.base_addr = base + reg * 4;
	256
	257	ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
	258	if (WARN_ON(IS_ERR(ttcce->clk)))
	259	return;
	260
	261	err = clk_prepare_enable(ttcce->clk);
	262	if (WARN_ON(err))
	263	return;
	264
	265	irq = irq_of_parse_and_map(np, 0);
	266	if (WARN_ON(!irq))
	267	return;
	268
	269	ttcce->ce.name = np->name;
	270	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
f184c5ca SB	271	ttcce->ce.set_next_event = xttcps_set_next_event;
f184c5ca SB	272	ttcce->ce.set_mode = xttcps_set_mode;
91dc985c JC	273	ttcce->ce.rating = 200;
	274	ttcce->ce.irq = irq;
	275
f184c5ca	276	__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
91dc985c	277	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
f184c5ca SB	278	ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
f184c5ca SB	279	__raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
91dc985c	280
f184c5ca	281	err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
91dc985c JC	282	np->name, ttcce);
	283	if (WARN_ON(err))
	284	return;
	285
	286	clockevents_config_and_register(&ttcce->ce,
	287	clk_get_rate(ttcce->clk) / PRESCALE,
	288	1, 0xfffe);
	289	}
	290
	291	static const __initconst struct of_device_id zynq_ttc_match[] = {
	292	{ .compatible = "xlnx,ttc-counter-clocksource",
	293	.data = zynq_ttc_setup_clocksource, },
	294	{ .compatible = "xlnx,ttc-counter-clockevent",
	295	.data = zynq_ttc_setup_clockevent, },
	296	{}
b85a3ef4 JL	297	};
	298
	299	/**
f184c5ca	300	* xttcps_timer_init - Initialize the timer
b85a3ef4 JL	301	*
	302	* Initializes the timer hardware and register the clock source and clock event
	303	* timers with Linux kernal timer framework
	304	**/
f184c5ca	305	void __init xttcps_timer_init(void)
b85a3ef4	306	{
91dc985c JC	307	struct device_node *np;
	308
	309	for_each_compatible_node(np, NULL, "xlnx,ttc") {
	310	struct device_node *np_chld;
	311	void __iomem *base;
	312
	313	base = of_iomap(np, 0);
	314	if (WARN_ON(!base))
	315	return;
	316
	317	for_each_available_child_of_node(np, np_chld) {
	318	int (cb)(struct device_node np, void __iomem *base);
	319	const struct of_device_id *match;
	320
	321	match = of_match_node(zynq_ttc_match, np_chld);
	322	if (match) {
	323	cb = match->data;
	324	cb(np_chld, base);
	325	}
	326	}
	327	}
b85a3ef4	328	}