Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | comment "Processor Type" |
2 | ||
1da177e4 LT |
3 | # Select CPU types depending on the architecture selected. This selects |
4 | # which CPUs we support in the kernel image, and the compiler instruction | |
5 | # optimiser behaviour. | |
6 | ||
07e0da78 HC |
7 | # ARM7TDMI |
8 | config CPU_ARM7TDMI | |
c32b7655 | 9 | bool |
6b237a35 | 10 | depends on !MMU |
07e0da78 HC |
11 | select CPU_32v4T |
12 | select CPU_ABRT_LV4T | |
13 | select CPU_CACHE_V4 | |
b1b3f49c | 14 | select CPU_PABRT_LEGACY |
07e0da78 HC |
15 | help |
16 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
17 | which has no memory control unit and cache. | |
18 | ||
19 | Say Y if you want support for the ARM7TDMI processor. | |
20 | Otherwise, say N. | |
21 | ||
1da177e4 LT |
22 | # ARM720T |
23 | config CPU_ARM720T | |
17d44d7d | 24 | bool |
260e98ed | 25 | select CPU_32v4T |
1da177e4 LT |
26 | select CPU_ABRT_LV4T |
27 | select CPU_CACHE_V4 | |
28 | select CPU_CACHE_VIVT | |
f9c21a6e | 29 | select CPU_COPY_V4WT if MMU |
b1b3f49c RK |
30 | select CPU_CP15_MMU |
31 | select CPU_PABRT_LEGACY | |
f9c21a6e | 32 | select CPU_TLB_V4WT if MMU |
1da177e4 LT |
33 | help |
34 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
35 | MMU built around an ARM7TDMI core. | |
36 | ||
37 | Say Y if you want support for the ARM720T processor. | |
38 | Otherwise, say N. | |
39 | ||
b731c311 HC |
40 | # ARM740T |
41 | config CPU_ARM740T | |
17d44d7d | 42 | bool |
6b237a35 | 43 | depends on !MMU |
b731c311 HC |
44 | select CPU_32v4T |
45 | select CPU_ABRT_LV4T | |
82d9b0d0 | 46 | select CPU_CACHE_V4 |
b731c311 | 47 | select CPU_CP15_MPU |
b1b3f49c | 48 | select CPU_PABRT_LEGACY |
b731c311 HC |
49 | help |
50 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
51 | write buffer and MPU(Protection Unit) built around | |
52 | an ARM7TDMI core. | |
53 | ||
54 | Say Y if you want support for the ARM740T processor. | |
55 | Otherwise, say N. | |
56 | ||
43f5f014 HC |
57 | # ARM9TDMI |
58 | config CPU_ARM9TDMI | |
c32b7655 | 59 | bool |
6b237a35 | 60 | depends on !MMU |
43f5f014 | 61 | select CPU_32v4T |
0f45d7f3 | 62 | select CPU_ABRT_NOMMU |
43f5f014 | 63 | select CPU_CACHE_V4 |
b1b3f49c | 64 | select CPU_PABRT_LEGACY |
43f5f014 HC |
65 | help |
66 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
67 | which has no memory control unit and cache. | |
68 | ||
69 | Say Y if you want support for the ARM9TDMI processor. | |
70 | Otherwise, say N. | |
71 | ||
1da177e4 LT |
72 | # ARM920T |
73 | config CPU_ARM920T | |
17d44d7d | 74 | bool |
260e98ed | 75 | select CPU_32v4T |
1da177e4 LT |
76 | select CPU_ABRT_EV4T |
77 | select CPU_CACHE_V4WT | |
78 | select CPU_CACHE_VIVT | |
f9c21a6e | 79 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
80 | select CPU_CP15_MMU |
81 | select CPU_PABRT_LEGACY | |
f9c21a6e | 82 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
83 | help |
84 | The ARM920T is licensed to be produced by numerous vendors, | |
c768e676 | 85 | and is used in the Cirrus EP93xx and the Samsung S3C2410. |
1da177e4 LT |
86 | |
87 | Say Y if you want support for the ARM920T processor. | |
88 | Otherwise, say N. | |
89 | ||
90 | # ARM922T | |
91 | config CPU_ARM922T | |
17d44d7d | 92 | bool |
260e98ed | 93 | select CPU_32v4T |
1da177e4 LT |
94 | select CPU_ABRT_EV4T |
95 | select CPU_CACHE_V4WT | |
96 | select CPU_CACHE_VIVT | |
f9c21a6e | 97 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
98 | select CPU_CP15_MMU |
99 | select CPU_PABRT_LEGACY | |
f9c21a6e | 100 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
101 | help |
102 | The ARM922T is a version of the ARM920T, but with smaller | |
103 | instruction and data caches. It is used in Altera's | |
c53c9cf6 | 104 | Excalibur XA device family and Micrel's KS8695 Centaur. |
1da177e4 LT |
105 | |
106 | Say Y if you want support for the ARM922T processor. | |
107 | Otherwise, say N. | |
108 | ||
109 | # ARM925T | |
110 | config CPU_ARM925T | |
17d44d7d | 111 | bool |
260e98ed | 112 | select CPU_32v4T |
1da177e4 LT |
113 | select CPU_ABRT_EV4T |
114 | select CPU_CACHE_V4WT | |
115 | select CPU_CACHE_VIVT | |
f9c21a6e | 116 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
117 | select CPU_CP15_MMU |
118 | select CPU_PABRT_LEGACY | |
f9c21a6e | 119 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
120 | help |
121 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
122 | different instruction and data caches. It is used in TI's OMAP | |
123 | device family. | |
124 | ||
125 | Say Y if you want support for the ARM925T processor. | |
126 | Otherwise, say N. | |
127 | ||
128 | # ARM926T | |
129 | config CPU_ARM926T | |
17d44d7d | 130 | bool |
1da177e4 LT |
131 | select CPU_32v5 |
132 | select CPU_ABRT_EV5TJ | |
133 | select CPU_CACHE_VIVT | |
f9c21a6e | 134 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
135 | select CPU_CP15_MMU |
136 | select CPU_PABRT_LEGACY | |
f9c21a6e | 137 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
138 | help |
139 | This is a variant of the ARM920. It has slightly different | |
140 | instruction sequences for cache and TLB operations. Curiously, | |
141 | there is no documentation on it at the ARM corporate website. | |
142 | ||
143 | Say Y if you want support for the ARM926T processor. | |
144 | Otherwise, say N. | |
145 | ||
28853ac8 PZ |
146 | # FA526 |
147 | config CPU_FA526 | |
148 | bool | |
149 | select CPU_32v4 | |
150 | select CPU_ABRT_EV4 | |
28853ac8 | 151 | select CPU_CACHE_FA |
b1b3f49c | 152 | select CPU_CACHE_VIVT |
28853ac8 | 153 | select CPU_COPY_FA if MMU |
b1b3f49c RK |
154 | select CPU_CP15_MMU |
155 | select CPU_PABRT_LEGACY | |
28853ac8 PZ |
156 | select CPU_TLB_FA if MMU |
157 | help | |
158 | The FA526 is a version of the ARMv4 compatible processor with | |
159 | Branch Target Buffer, Unified TLB and cache line size 16. | |
160 | ||
161 | Say Y if you want support for the FA526 processor. | |
162 | Otherwise, say N. | |
163 | ||
d60674eb HC |
164 | # ARM940T |
165 | config CPU_ARM940T | |
17d44d7d | 166 | bool |
6b237a35 | 167 | depends on !MMU |
d60674eb | 168 | select CPU_32v4T |
0f45d7f3 | 169 | select CPU_ABRT_NOMMU |
d60674eb HC |
170 | select CPU_CACHE_VIVT |
171 | select CPU_CP15_MPU | |
b1b3f49c | 172 | select CPU_PABRT_LEGACY |
d60674eb HC |
173 | help |
174 | ARM940T is a member of the ARM9TDMI family of general- | |
3cb2fccc | 175 | purpose microprocessors with MPU and separate 4KB |
d60674eb HC |
176 | instruction and 4KB data cases, each with a 4-word line |
177 | length. | |
178 | ||
179 | Say Y if you want support for the ARM940T processor. | |
180 | Otherwise, say N. | |
181 | ||
f37f46eb HC |
182 | # ARM946E-S |
183 | config CPU_ARM946E | |
17d44d7d | 184 | bool |
6b237a35 | 185 | depends on !MMU |
f37f46eb | 186 | select CPU_32v5 |
0f45d7f3 | 187 | select CPU_ABRT_NOMMU |
f37f46eb HC |
188 | select CPU_CACHE_VIVT |
189 | select CPU_CP15_MPU | |
b1b3f49c | 190 | select CPU_PABRT_LEGACY |
f37f46eb HC |
191 | help |
192 | ARM946E-S is a member of the ARM9E-S family of high- | |
193 | performance, 32-bit system-on-chip processor solutions. | |
194 | The TCM and ARMv5TE 32-bit instruction set is supported. | |
195 | ||
196 | Say Y if you want support for the ARM946E-S processor. | |
197 | Otherwise, say N. | |
198 | ||
1da177e4 LT |
199 | # ARM1020 - needs validating |
200 | config CPU_ARM1020 | |
17d44d7d | 201 | bool |
1da177e4 LT |
202 | select CPU_32v5 |
203 | select CPU_ABRT_EV4T | |
204 | select CPU_CACHE_V4WT | |
205 | select CPU_CACHE_VIVT | |
f9c21a6e | 206 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
207 | select CPU_CP15_MMU |
208 | select CPU_PABRT_LEGACY | |
f9c21a6e | 209 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
210 | help |
211 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
212 | with an addition of a floating-point unit. | |
213 | ||
214 | Say Y if you want support for the ARM1020 processor. | |
215 | Otherwise, say N. | |
216 | ||
217 | # ARM1020E - needs validating | |
218 | config CPU_ARM1020E | |
17d44d7d | 219 | bool |
b1b3f49c | 220 | depends on n |
1da177e4 LT |
221 | select CPU_32v5 |
222 | select CPU_ABRT_EV4T | |
223 | select CPU_CACHE_V4WT | |
224 | select CPU_CACHE_VIVT | |
f9c21a6e | 225 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
226 | select CPU_CP15_MMU |
227 | select CPU_PABRT_LEGACY | |
f9c21a6e | 228 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
229 | |
230 | # ARM1022E | |
231 | config CPU_ARM1022 | |
17d44d7d | 232 | bool |
1da177e4 LT |
233 | select CPU_32v5 |
234 | select CPU_ABRT_EV4T | |
235 | select CPU_CACHE_VIVT | |
f9c21a6e | 236 | select CPU_COPY_V4WB if MMU # can probably do better |
b1b3f49c RK |
237 | select CPU_CP15_MMU |
238 | select CPU_PABRT_LEGACY | |
f9c21a6e | 239 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
240 | help |
241 | The ARM1022E is an implementation of the ARMv5TE architecture | |
242 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
243 | embedded trace macrocell, and a floating-point unit. | |
244 | ||
245 | Say Y if you want support for the ARM1022E processor. | |
246 | Otherwise, say N. | |
247 | ||
248 | # ARM1026EJ-S | |
249 | config CPU_ARM1026 | |
17d44d7d | 250 | bool |
1da177e4 LT |
251 | select CPU_32v5 |
252 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
253 | select CPU_CACHE_VIVT | |
f9c21a6e | 254 | select CPU_COPY_V4WB if MMU # can probably do better |
b1b3f49c RK |
255 | select CPU_CP15_MMU |
256 | select CPU_PABRT_LEGACY | |
f9c21a6e | 257 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
258 | help |
259 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
260 | based upon the ARM10 integer core. | |
261 | ||
262 | Say Y if you want support for the ARM1026EJ-S processor. | |
263 | Otherwise, say N. | |
264 | ||
265 | # SA110 | |
266 | config CPU_SA110 | |
fa04e209 | 267 | bool |
1da177e4 LT |
268 | select CPU_32v3 if ARCH_RPC |
269 | select CPU_32v4 if !ARCH_RPC | |
270 | select CPU_ABRT_EV4 | |
271 | select CPU_CACHE_V4WB | |
272 | select CPU_CACHE_VIVT | |
f9c21a6e | 273 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
274 | select CPU_CP15_MMU |
275 | select CPU_PABRT_LEGACY | |
f9c21a6e | 276 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
277 | help |
278 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
279 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
280 | More information is available at | |
281 | <http://developer.intel.com/design/strong/sa110.htm>. | |
282 | ||
283 | Say Y if you want support for the SA-110 processor. | |
284 | Otherwise, say N. | |
285 | ||
286 | # SA1100 | |
287 | config CPU_SA1100 | |
288 | bool | |
1da177e4 LT |
289 | select CPU_32v4 |
290 | select CPU_ABRT_EV4 | |
291 | select CPU_CACHE_V4WB | |
292 | select CPU_CACHE_VIVT | |
fefdaa06 | 293 | select CPU_CP15_MMU |
b1b3f49c | 294 | select CPU_PABRT_LEGACY |
f9c21a6e | 295 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
296 | |
297 | # XScale | |
298 | config CPU_XSCALE | |
299 | bool | |
1da177e4 LT |
300 | select CPU_32v5 |
301 | select CPU_ABRT_EV5T | |
302 | select CPU_CACHE_VIVT | |
fefdaa06 | 303 | select CPU_CP15_MMU |
b1b3f49c | 304 | select CPU_PABRT_LEGACY |
f9c21a6e | 305 | select CPU_TLB_V4WBI if MMU |
1da177e4 | 306 | |
23bdf86a LB |
307 | # XScale Core Version 3 |
308 | config CPU_XSC3 | |
309 | bool | |
23bdf86a LB |
310 | select CPU_32v5 |
311 | select CPU_ABRT_EV5T | |
312 | select CPU_CACHE_VIVT | |
fefdaa06 | 313 | select CPU_CP15_MMU |
b1b3f49c | 314 | select CPU_PABRT_LEGACY |
f9c21a6e | 315 | select CPU_TLB_V4WBI if MMU |
23bdf86a LB |
316 | select IO_36 |
317 | ||
49cbe786 EM |
318 | # Marvell PJ1 (Mohawk) |
319 | config CPU_MOHAWK | |
320 | bool | |
321 | select CPU_32v5 | |
322 | select CPU_ABRT_EV5T | |
49cbe786 | 323 | select CPU_CACHE_VIVT |
b1b3f49c | 324 | select CPU_COPY_V4WB if MMU |
49cbe786 | 325 | select CPU_CP15_MMU |
b1b3f49c | 326 | select CPU_PABRT_LEGACY |
49cbe786 | 327 | select CPU_TLB_V4WBI if MMU |
49cbe786 | 328 | |
e50d6409 AH |
329 | # Feroceon |
330 | config CPU_FEROCEON | |
331 | bool | |
e50d6409 AH |
332 | select CPU_32v5 |
333 | select CPU_ABRT_EV5T | |
334 | select CPU_CACHE_VIVT | |
0ed15071 | 335 | select CPU_COPY_FEROCEON if MMU |
b1b3f49c RK |
336 | select CPU_CP15_MMU |
337 | select CPU_PABRT_LEGACY | |
99c6dc11 | 338 | select CPU_TLB_FEROCEON if MMU |
e50d6409 | 339 | |
d910a0aa TP |
340 | config CPU_FEROCEON_OLD_ID |
341 | bool "Accept early Feroceon cores with an ARM926 ID" | |
342 | depends on CPU_FEROCEON && !CPU_ARM926T | |
343 | default y | |
344 | help | |
345 | This enables the usage of some old Feroceon cores | |
346 | for which the CPU ID is equal to the ARM926 ID. | |
347 | Relevant for Feroceon-1850 and early Feroceon-2850. | |
348 | ||
a4553358 HZ |
349 | # Marvell PJ4 |
350 | config CPU_PJ4 | |
351 | bool | |
a4553358 | 352 | select ARM_THUMBEE |
b1b3f49c | 353 | select CPU_V7 |
a4553358 | 354 | |
de490193 GC |
355 | config CPU_PJ4B |
356 | bool | |
357 | select CPU_V7 | |
358 | ||
1da177e4 LT |
359 | # ARMv6 |
360 | config CPU_V6 | |
17d44d7d | 361 | bool |
1da177e4 LT |
362 | select CPU_32v6 |
363 | select CPU_ABRT_EV6 | |
364 | select CPU_CACHE_V6 | |
365 | select CPU_CACHE_VIPT | |
b1b3f49c | 366 | select CPU_COPY_V6 if MMU |
fefdaa06 | 367 | select CPU_CP15_MMU |
7b4c965a | 368 | select CPU_HAS_ASID if MMU |
b1b3f49c | 369 | select CPU_PABRT_V6 |
f9c21a6e | 370 | select CPU_TLB_V6 if MMU |
1da177e4 | 371 | |
4a5f79e7 | 372 | # ARMv6k |
e399b1a4 | 373 | config CPU_V6K |
17d44d7d | 374 | bool |
e399b1a4 | 375 | select CPU_32v6 |
60799c6d | 376 | select CPU_32v6K |
e399b1a4 | 377 | select CPU_ABRT_EV6 |
e399b1a4 RK |
378 | select CPU_CACHE_V6 |
379 | select CPU_CACHE_VIPT | |
b1b3f49c | 380 | select CPU_COPY_V6 if MMU |
e399b1a4 RK |
381 | select CPU_CP15_MMU |
382 | select CPU_HAS_ASID if MMU | |
b1b3f49c | 383 | select CPU_PABRT_V6 |
e399b1a4 | 384 | select CPU_TLB_V6 if MMU |
4a5f79e7 | 385 | |
23688e99 CM |
386 | # ARMv7 |
387 | config CPU_V7 | |
17d44d7d | 388 | bool |
15490ef8 | 389 | select CPU_32v6K |
23688e99 CM |
390 | select CPU_32v7 |
391 | select CPU_ABRT_EV7 | |
392 | select CPU_CACHE_V7 | |
393 | select CPU_CACHE_VIPT | |
b1b3f49c | 394 | select CPU_COPY_V6 if MMU |
66567618 JA |
395 | select CPU_CP15_MMU if MMU |
396 | select CPU_CP15_MPU if !MMU | |
2eb8c82b | 397 | select CPU_HAS_ASID if MMU |
b1b3f49c | 398 | select CPU_PABRT_V7 |
2ccdd1e7 | 399 | select CPU_TLB_V7 if MMU |
23688e99 | 400 | |
4477ca45 UKK |
401 | # ARMv7M |
402 | config CPU_V7M | |
403 | bool | |
404 | select CPU_32v7M | |
405 | select CPU_ABRT_NOMMU | |
406 | select CPU_CACHE_NOP | |
407 | select CPU_PABRT_LEGACY | |
408 | select CPU_THUMBONLY | |
409 | ||
bc7dea00 UKK |
410 | config CPU_THUMBONLY |
411 | bool | |
412 | # There are no CPUs available with MMU that don't implement an ARM ISA: | |
413 | depends on !MMU | |
414 | help | |
415 | Select this if your CPU doesn't support the 32 bit ARM instructions. | |
416 | ||
1da177e4 LT |
417 | # Figure out what processor architecture version we should be using. |
418 | # This defines the compiler instruction set which depends on the machine type. | |
419 | config CPU_32v3 | |
420 | bool | |
8762df4d | 421 | select CPU_USE_DOMAINS if MMU |
f6f91b0d | 422 | select NEED_KUSER_HELPERS |
51aaf81f | 423 | select TLS_REG_EMUL if SMP || !MMU |
1da177e4 LT |
424 | |
425 | config CPU_32v4 | |
426 | bool | |
8762df4d | 427 | select CPU_USE_DOMAINS if MMU |
f6f91b0d | 428 | select NEED_KUSER_HELPERS |
51aaf81f | 429 | select TLS_REG_EMUL if SMP || !MMU |
1da177e4 | 430 | |
260e98ed LB |
431 | config CPU_32v4T |
432 | bool | |
8762df4d | 433 | select CPU_USE_DOMAINS if MMU |
f6f91b0d | 434 | select NEED_KUSER_HELPERS |
51aaf81f | 435 | select TLS_REG_EMUL if SMP || !MMU |
260e98ed | 436 | |
1da177e4 LT |
437 | config CPU_32v5 |
438 | bool | |
8762df4d | 439 | select CPU_USE_DOMAINS if MMU |
f6f91b0d | 440 | select NEED_KUSER_HELPERS |
51aaf81f | 441 | select TLS_REG_EMUL if SMP || !MMU |
1da177e4 LT |
442 | |
443 | config CPU_32v6 | |
444 | bool | |
b1b3f49c | 445 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
1da177e4 | 446 | |
e399b1a4 | 447 | config CPU_32v6K |
60799c6d | 448 | bool |
1da177e4 | 449 | |
23688e99 CM |
450 | config CPU_32v7 |
451 | bool | |
452 | ||
4477ca45 UKK |
453 | config CPU_32v7M |
454 | bool | |
455 | ||
1da177e4 | 456 | # The abort model |
0f45d7f3 HC |
457 | config CPU_ABRT_NOMMU |
458 | bool | |
459 | ||
1da177e4 LT |
460 | config CPU_ABRT_EV4 |
461 | bool | |
462 | ||
463 | config CPU_ABRT_EV4T | |
464 | bool | |
465 | ||
466 | config CPU_ABRT_LV4T | |
467 | bool | |
468 | ||
469 | config CPU_ABRT_EV5T | |
470 | bool | |
471 | ||
472 | config CPU_ABRT_EV5TJ | |
473 | bool | |
474 | ||
475 | config CPU_ABRT_EV6 | |
476 | bool | |
477 | ||
23688e99 CM |
478 | config CPU_ABRT_EV7 |
479 | bool | |
480 | ||
4fb28474 | 481 | config CPU_PABRT_LEGACY |
48d7927b PB |
482 | bool |
483 | ||
4fb28474 KS |
484 | config CPU_PABRT_V6 |
485 | bool | |
486 | ||
487 | config CPU_PABRT_V7 | |
48d7927b PB |
488 | bool |
489 | ||
1da177e4 | 490 | # The cache model |
1da177e4 LT |
491 | config CPU_CACHE_V4 |
492 | bool | |
493 | ||
494 | config CPU_CACHE_V4WT | |
495 | bool | |
496 | ||
497 | config CPU_CACHE_V4WB | |
498 | bool | |
499 | ||
500 | config CPU_CACHE_V6 | |
501 | bool | |
502 | ||
23688e99 CM |
503 | config CPU_CACHE_V7 |
504 | bool | |
505 | ||
4477ca45 UKK |
506 | config CPU_CACHE_NOP |
507 | bool | |
508 | ||
1da177e4 LT |
509 | config CPU_CACHE_VIVT |
510 | bool | |
511 | ||
512 | config CPU_CACHE_VIPT | |
513 | bool | |
514 | ||
28853ac8 PZ |
515 | config CPU_CACHE_FA |
516 | bool | |
517 | ||
f9c21a6e | 518 | if MMU |
1da177e4 | 519 | # The copy-page model |
1da177e4 LT |
520 | config CPU_COPY_V4WT |
521 | bool | |
522 | ||
523 | config CPU_COPY_V4WB | |
524 | bool | |
525 | ||
0ed15071 LB |
526 | config CPU_COPY_FEROCEON |
527 | bool | |
528 | ||
28853ac8 PZ |
529 | config CPU_COPY_FA |
530 | bool | |
531 | ||
1da177e4 LT |
532 | config CPU_COPY_V6 |
533 | bool | |
534 | ||
535 | # This selects the TLB model | |
1da177e4 LT |
536 | config CPU_TLB_V4WT |
537 | bool | |
538 | help | |
539 | ARM Architecture Version 4 TLB with writethrough cache. | |
540 | ||
541 | config CPU_TLB_V4WB | |
542 | bool | |
543 | help | |
544 | ARM Architecture Version 4 TLB with writeback cache. | |
545 | ||
546 | config CPU_TLB_V4WBI | |
547 | bool | |
548 | help | |
549 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
550 | instruction cache entry. | |
551 | ||
99c6dc11 LB |
552 | config CPU_TLB_FEROCEON |
553 | bool | |
554 | help | |
555 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | |
556 | ||
28853ac8 PZ |
557 | config CPU_TLB_FA |
558 | bool | |
559 | help | |
560 | Faraday ARM FA526 architecture, unified TLB with writeback cache | |
561 | and invalidate instruction cache entry. Branch target buffer is | |
562 | also supported. | |
563 | ||
1da177e4 LT |
564 | config CPU_TLB_V6 |
565 | bool | |
566 | ||
2ccdd1e7 CM |
567 | config CPU_TLB_V7 |
568 | bool | |
569 | ||
e220ba60 DE |
570 | config VERIFY_PERMISSION_FAULT |
571 | bool | |
f9c21a6e HC |
572 | endif |
573 | ||
516793c6 RK |
574 | config CPU_HAS_ASID |
575 | bool | |
576 | help | |
577 | This indicates whether the CPU has the ASID register; used to | |
578 | tag TLB and possibly cache entries. | |
579 | ||
fefdaa06 HC |
580 | config CPU_CP15 |
581 | bool | |
582 | help | |
583 | Processor has the CP15 register. | |
584 | ||
585 | config CPU_CP15_MMU | |
586 | bool | |
587 | select CPU_CP15 | |
588 | help | |
589 | Processor has the CP15 register, which has MMU related registers. | |
590 | ||
591 | config CPU_CP15_MPU | |
592 | bool | |
593 | select CPU_CP15 | |
594 | help | |
595 | Processor has the CP15 register, which has MPU related registers. | |
596 | ||
247055aa CM |
597 | config CPU_USE_DOMAINS |
598 | bool | |
247055aa CM |
599 | help |
600 | This option enables or disables the use of domain switching | |
601 | via the set_fs() function. | |
602 | ||
6b1814cd MC |
603 | config CPU_V7M_NUM_IRQ |
604 | int "Number of external interrupts connected to the NVIC" | |
605 | depends on CPU_V7M | |
606 | default 90 if ARCH_STM32 | |
607 | default 38 if ARCH_EFM32 | |
45b0fa09 | 608 | default 112 if SOC_VF610 |
6b1814cd MC |
609 | default 240 |
610 | help | |
611 | This option indicates the number of interrupts connected to the NVIC. | |
612 | The value can be larger than the real number of interrupts supported | |
613 | by the system, but must not be lower. | |
614 | The default value is 240, corresponding to the maximum number of | |
615 | interrupts supported by the NVIC on Cortex-M family. | |
616 | ||
617 | If unsure, keep default value. | |
618 | ||
23bdf86a LB |
619 | # |
620 | # CPU supports 36-bit I/O | |
621 | # | |
622 | config IO_36 | |
623 | bool | |
624 | ||
1da177e4 LT |
625 | comment "Processor Features" |
626 | ||
497b7e94 CM |
627 | config ARM_LPAE |
628 | bool "Support for the Large Physical Address Extension" | |
08a183f0 CM |
629 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ |
630 | !CPU_32v4 && !CPU_32v3 | |
497b7e94 CM |
631 | help |
632 | Say Y if you have an ARMv7 processor supporting the LPAE page | |
633 | table format and you would like to access memory beyond the | |
634 | 4GB limit. The resulting kernel image will not run on | |
635 | processors without the LPA extension. | |
636 | ||
637 | If unsure, say N. | |
638 | ||
d8dc7fbd RK |
639 | config ARM_PV_FIXUP |
640 | def_bool y | |
641 | depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE | |
642 | ||
497b7e94 CM |
643 | config ARCH_PHYS_ADDR_T_64BIT |
644 | def_bool ARM_LPAE | |
645 | ||
646 | config ARCH_DMA_ADDR_T_64BIT | |
647 | bool | |
648 | ||
1da177e4 | 649 | config ARM_THUMB |
bc7dea00 | 650 | bool "Support Thumb user binaries" if !CPU_THUMBONLY |
4477ca45 UKK |
651 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ |
652 | CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ | |
653 | CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ | |
654 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ | |
655 | CPU_V7 || CPU_FEROCEON || CPU_V7M | |
1da177e4 LT |
656 | default y |
657 | help | |
658 | Say Y if you want to include kernel support for running user space | |
659 | Thumb binaries. | |
660 | ||
661 | The Thumb instruction set is a compressed form of the standard ARM | |
662 | instruction set resulting in smaller binaries at the expense of | |
663 | slightly less efficient code. | |
664 | ||
665 | If you don't know what this all is, saying Y is a safe choice. | |
666 | ||
d7f864be CM |
667 | config ARM_THUMBEE |
668 | bool "Enable ThumbEE CPU extension" | |
669 | depends on CPU_V7 | |
670 | help | |
671 | Say Y here if you have a CPU with the ThumbEE extension and code to | |
672 | make use of it. Say N for code that can run on CPUs without ThumbEE. | |
673 | ||
5b6728d4 | 674 | config ARM_VIRT_EXT |
651134b0 WD |
675 | bool |
676 | depends on MMU | |
677 | default y if CPU_V7 | |
5b6728d4 DM |
678 | help |
679 | Enable the kernel to make use of the ARM Virtualization | |
680 | Extensions to install hypervisors without run-time firmware | |
681 | assistance. | |
682 | ||
683 | A compliant bootloader is required in order to make maximum | |
684 | use of this feature. Refer to Documentation/arm/Booting for | |
685 | details. | |
686 | ||
64d2dc38 | 687 | config SWP_EMULATE |
a11dd731 | 688 | bool "Emulate SWP/SWPB instructions" if !SMP |
b6ccb980 | 689 | depends on CPU_V7 |
64d2dc38 | 690 | default y if SMP |
b1b3f49c | 691 | select HAVE_PROC_CPU if PROC_FS |
64d2dc38 LL |
692 | help |
693 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. | |
694 | ARMv7 multiprocessing extensions introduce the ability to disable | |
695 | these instructions, triggering an undefined instruction exception | |
696 | when executed. Say Y here to enable software emulation of these | |
697 | instructions for userspace (not kernel) using LDREX/STREX. | |
698 | Also creates /proc/cpu/swp_emulation for statistics. | |
699 | ||
700 | In some older versions of glibc [<=2.8] SWP is used during futex | |
701 | trylock() operations with the assumption that the code will not | |
702 | be preempted. This invalid assumption may be more likely to fail | |
703 | with SWP emulation enabled, leading to deadlock of the user | |
704 | application. | |
705 | ||
706 | NOTE: when accessing uncached shared regions, LDREX/STREX rely | |
707 | on an external transaction monitoring block called a global | |
708 | monitor to maintain update atomicity. If your system does not | |
709 | implement a global monitor, this option can cause programs that | |
710 | perform SWP operations to uncached memory to deadlock. | |
711 | ||
712 | If unsure, say Y. | |
713 | ||
1da177e4 LT |
714 | config CPU_BIG_ENDIAN |
715 | bool "Build big-endian kernel" | |
716 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
717 | help | |
718 | Say Y if you plan on running a kernel in big-endian mode. | |
719 | Note that your board must be properly built and your board | |
720 | port must properly enable any big-endian related features | |
721 | of your chipset/board/processor. | |
722 | ||
26584853 CM |
723 | config CPU_ENDIAN_BE8 |
724 | bool | |
725 | depends on CPU_BIG_ENDIAN | |
e399b1a4 | 726 | default CPU_V6 || CPU_V6K || CPU_V7 |
26584853 CM |
727 | help |
728 | Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. | |
729 | ||
730 | config CPU_ENDIAN_BE32 | |
731 | bool | |
732 | depends on CPU_BIG_ENDIAN | |
733 | default !CPU_ENDIAN_BE8 | |
734 | help | |
735 | Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. | |
736 | ||
6afd6fae | 737 | config CPU_HIGH_VECTOR |
6340aa61 | 738 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
6afd6fae | 739 | bool "Select the High exception vector" |
6afd6fae HC |
740 | help |
741 | Say Y here to select high exception vector(0xFFFF0000~). | |
9b7333a9 | 742 | The exception vector can vary depending on the platform |
6afd6fae HC |
743 | design in nommu mode. If your platform needs to select |
744 | high exception vector, say Y. | |
745 | Otherwise or if you are unsure, say N, and the low exception | |
746 | vector (0x00000000~) will be used. | |
747 | ||
1da177e4 | 748 | config CPU_ICACHE_DISABLE |
f12d0d7c | 749 | bool "Disable I-Cache (I-bit)" |
357c9c1f | 750 | depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) |
1da177e4 LT |
751 | help |
752 | Say Y here to disable the processor instruction cache. Unless | |
753 | you have a reason not to or are unsure, say N. | |
754 | ||
755 | config CPU_DCACHE_DISABLE | |
f12d0d7c | 756 | bool "Disable D-Cache (C-bit)" |
e1e2f6e4 | 757 | depends on CPU_CP15 && !SMP |
1da177e4 LT |
758 | help |
759 | Say Y here to disable the processor data cache. Unless | |
760 | you have a reason not to or are unsure, say N. | |
761 | ||
f37f46eb HC |
762 | config CPU_DCACHE_SIZE |
763 | hex | |
764 | depends on CPU_ARM740T || CPU_ARM946E | |
765 | default 0x00001000 if CPU_ARM740T | |
766 | default 0x00002000 # default size for ARM946E-S | |
767 | help | |
768 | Some cores are synthesizable to have various sized cache. For | |
769 | ARM946E-S case, it can vary from 0KB to 1MB. | |
770 | To support such cache operations, it is efficient to know the size | |
771 | before compile time. | |
772 | If your SoC is configured to have a different size, define the value | |
773 | here with proper conditions. | |
774 | ||
1da177e4 LT |
775 | config CPU_DCACHE_WRITETHROUGH |
776 | bool "Force write through D-cache" | |
28853ac8 | 777 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
1da177e4 LT |
778 | default y if CPU_ARM925T |
779 | help | |
780 | Say Y here to use the data cache in writethrough mode. Unless you | |
781 | specifically require this or are unsure, say N. | |
782 | ||
783 | config CPU_CACHE_ROUND_ROBIN | |
784 | bool "Round robin I and D cache replacement algorithm" | |
f37f46eb | 785 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
1da177e4 LT |
786 | help |
787 | Say Y here to use the predictable round-robin cache replacement | |
788 | policy. Unless you specifically require this or are unsure, say N. | |
789 | ||
790 | config CPU_BPREDICT_DISABLE | |
791 | bool "Disable branch prediction" | |
e399b1a4 | 792 | depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
1da177e4 LT |
793 | help |
794 | Say Y here to disable branch prediction. If unsure, say N. | |
2d2669b6 | 795 | |
4b0e07a5 NP |
796 | config TLS_REG_EMUL |
797 | bool | |
f6f91b0d | 798 | select NEED_KUSER_HELPERS |
4b0e07a5 | 799 | help |
70489c88 NP |
800 | An SMP system using a pre-ARMv6 processor (there are apparently |
801 | a few prototypes like that in existence) and therefore access to | |
802 | that required register must be emulated. | |
4b0e07a5 | 803 | |
f6f91b0d RK |
804 | config NEED_KUSER_HELPERS |
805 | bool | |
806 | ||
807 | config KUSER_HELPERS | |
808 | bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS | |
08b964ff | 809 | depends on MMU |
f6f91b0d RK |
810 | default y |
811 | help | |
812 | Warning: disabling this option may break user programs. | |
813 | ||
814 | Provide kuser helpers in the vector page. The kernel provides | |
815 | helper code to userspace in read only form at a fixed location | |
816 | in the high vector page to allow userspace to be independent of | |
817 | the CPU type fitted to the system. This permits binaries to be | |
818 | run on ARMv4 through to ARMv7 without modification. | |
819 | ||
ac124504 NP |
820 | See Documentation/arm/kernel_user_helpers.txt for details. |
821 | ||
f6f91b0d RK |
822 | However, the fixed address nature of these helpers can be used |
823 | by ROP (return orientated programming) authors when creating | |
824 | exploits. | |
825 | ||
826 | If all of the binaries and libraries which run on your platform | |
827 | are built specifically for your platform, and make no use of | |
ac124504 NP |
828 | these helpers, then you can turn this option off to hinder |
829 | such exploits. However, in that case, if a binary or library | |
830 | relying on those helpers is run, it will receive a SIGILL signal, | |
831 | which will terminate the program. | |
f6f91b0d RK |
832 | |
833 | Say N here only if you are absolutely certain that you do not | |
834 | need these helpers; otherwise, the safe option is to say Y. | |
835 | ||
e5b61deb NL |
836 | config VDSO |
837 | bool "Enable VDSO for acceleration of some system calls" | |
5d38000b | 838 | depends on AEABI && MMU && CPU_V7 |
e5b61deb NL |
839 | default y if ARM_ARCH_TIMER |
840 | select GENERIC_TIME_VSYSCALL | |
841 | help | |
842 | Place in the process address space an ELF shared object | |
843 | providing fast implementations of gettimeofday and | |
844 | clock_gettime. Systems that implement the ARM architected | |
845 | timer will receive maximum benefit. | |
846 | ||
847 | You must have glibc 2.22 or later for programs to seamlessly | |
848 | take advantage of this. | |
849 | ||
ad642d9f CM |
850 | config DMA_CACHE_RWFO |
851 | bool "Enable read/write for ownership DMA cache maintenance" | |
3bc28c8e | 852 | depends on CPU_V6K && SMP |
ad642d9f CM |
853 | default y |
854 | help | |
855 | The Snoop Control Unit on ARM11MPCore does not detect the | |
856 | cache maintenance operations and the dma_{map,unmap}_area() | |
857 | functions may leave stale cache entries on other CPUs. By | |
858 | enabling this option, Read or Write For Ownership in the ARMv6 | |
859 | DMA cache maintenance functions is performed. These LDR/STR | |
860 | instructions change the cache line state to shared or modified | |
861 | so that the cache operation has the desired effect. | |
862 | ||
863 | Note that the workaround is only valid on processors that do | |
864 | not perform speculative loads into the D-cache. For such | |
865 | processors, if cache maintenance operations are not broadcast | |
866 | in hardware, other workarounds are needed (e.g. cache | |
867 | maintenance broadcasting in software via FIQ). | |
868 | ||
953233dc CM |
869 | config OUTER_CACHE |
870 | bool | |
382266ad | 871 | |
319f551a CM |
872 | config OUTER_CACHE_SYNC |
873 | bool | |
f8130906 | 874 | select ARM_HEAVY_MB |
319f551a CM |
875 | help |
876 | The outer cache has a outer_cache_fns.sync function pointer | |
877 | that can be used to drain the write buffer of the outer cache. | |
878 | ||
99c6dc11 LB |
879 | config CACHE_FEROCEON_L2 |
880 | bool "Enable the Feroceon L2 cache controller" | |
ba364fc7 | 881 | depends on ARCH_MV78XX0 || ARCH_MVEBU |
99c6dc11 LB |
882 | default y |
883 | select OUTER_CACHE | |
884 | help | |
885 | This option enables the Feroceon L2 cache controller. | |
886 | ||
4360bb41 RS |
887 | config CACHE_FEROCEON_L2_WRITETHROUGH |
888 | bool "Force Feroceon L2 cache write through" | |
889 | depends on CACHE_FEROCEON_L2 | |
4360bb41 RS |
890 | help |
891 | Say Y here to use the Feroceon L2 cache in writethrough mode. | |
892 | Unless you specifically require this, say N for writeback mode. | |
893 | ||
ce5ea9f3 DM |
894 | config MIGHT_HAVE_CACHE_L2X0 |
895 | bool | |
896 | help | |
897 | This option should be selected by machines which have a L2x0 | |
898 | or PL310 cache controller, but where its use is optional. | |
899 | ||
900 | The only effect of this option is to make CACHE_L2X0 and | |
901 | related options available to the user for configuration. | |
902 | ||
903 | Boards or SoCs which always require the cache controller | |
904 | support to be present should select CACHE_L2X0 directly | |
905 | instead of this option, thus preventing the user from | |
906 | inadvertently configuring a broken kernel. | |
907 | ||
382266ad | 908 | config CACHE_L2X0 |
ce5ea9f3 DM |
909 | bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 |
910 | default MIGHT_HAVE_CACHE_L2X0 | |
382266ad | 911 | select OUTER_CACHE |
23107c54 | 912 | select OUTER_CACHE_SYNC |
ba927951 CM |
913 | help |
914 | This option enables the L2x0 PrimeCell. | |
905a09d5 | 915 | |
a641f3a6 RK |
916 | if CACHE_L2X0 |
917 | ||
c0fe18ba RK |
918 | config PL310_ERRATA_588369 |
919 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" | |
c0fe18ba RK |
920 | help |
921 | The PL310 L2 cache controller implements three types of Clean & | |
922 | Invalidate maintenance operations: by Physical Address | |
923 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
924 | They are architecturally defined to behave as the execution of a | |
925 | clean operation followed immediately by an invalidate operation, | |
926 | both performing to the same memory location. This functionality | |
80d3cb91 SG |
927 | is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0) |
928 | as clean lines are not invalidated as a result of these operations. | |
c0fe18ba RK |
929 | |
930 | config PL310_ERRATA_727915 | |
931 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" | |
c0fe18ba RK |
932 | help |
933 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
934 | operation (offset 0x7FC). This operation runs in background so that | |
935 | PL310 can handle normal accesses while it is in progress. Under very | |
936 | rare circumstances, due to this erratum, write data can be lost when | |
937 | PL310 treats a cacheable write transaction during a Clean & | |
80d3cb91 SG |
938 | Invalidate by Way operation. Revisions prior to r3p1 are affected by |
939 | this errata (fixed in r3p1). | |
c0fe18ba RK |
940 | |
941 | config PL310_ERRATA_753970 | |
942 | bool "PL310 errata: cache sync operation may be faulty" | |
c0fe18ba RK |
943 | help |
944 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
945 | ||
946 | Under some condition the effect of cache sync operation on | |
947 | the store buffer still remains when the operation completes. | |
948 | This means that the store buffer is always asked to drain and | |
949 | this prevents it from merging any further writes. The workaround | |
950 | is to replace the normal offset of cache sync operation (0x730) | |
951 | by another offset targeting an unmapped PL310 register 0x740. | |
952 | This has the same effect as the cache sync operation: store buffer | |
953 | drain and waiting for all buffers empty. | |
954 | ||
955 | config PL310_ERRATA_769419 | |
956 | bool "PL310 errata: no automatic Store Buffer drain" | |
c0fe18ba RK |
957 | help |
958 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
959 | not automatically drain. This can cause normal, non-cacheable | |
960 | writes to be retained when the memory system is idle, leading | |
961 | to suboptimal I/O performance for drivers using coherent DMA. | |
962 | This option adds a write barrier to the cpu_idle loop so that, | |
963 | on systems with an outer cache, the store buffer is drained | |
964 | explicitly. | |
965 | ||
a641f3a6 RK |
966 | endif |
967 | ||
573a652f LB |
968 | config CACHE_TAUROS2 |
969 | bool "Enable the Tauros2 L2 cache controller" | |
3f408fa0 | 970 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) |
573a652f LB |
971 | default y |
972 | select OUTER_CACHE | |
973 | help | |
974 | This option enables the Tauros2 L2 cache controller (as | |
975 | found on PJ1/PJ4). | |
976 | ||
e7ecbc05 MY |
977 | config CACHE_UNIPHIER |
978 | bool "Enable the UniPhier outer cache controller" | |
979 | depends on ARCH_UNIPHIER | |
980 | default y | |
981 | select OUTER_CACHE | |
982 | select OUTER_CACHE_SYNC | |
983 | help | |
984 | This option enables the UniPhier outer cache (system cache) | |
985 | controller. | |
986 | ||
905a09d5 EM |
987 | config CACHE_XSC3L2 |
988 | bool "Enable the L2 cache on XScale3" | |
989 | depends on CPU_XSC3 | |
990 | default y | |
991 | select OUTER_CACHE | |
992 | help | |
993 | This option enables the L2 cache on XScale3. | |
910a17e5 | 994 | |
5637a126 RK |
995 | config ARM_L1_CACHE_SHIFT_6 |
996 | bool | |
a092f2b1 | 997 | default y if CPU_V7 |
5637a126 RK |
998 | help |
999 | Setting ARM L1 cache line size to 64 Bytes. | |
1000 | ||
910a17e5 KS |
1001 | config ARM_L1_CACHE_SHIFT |
1002 | int | |
d6d502fa | 1003 | default 6 if ARM_L1_CACHE_SHIFT_6 |
910a17e5 | 1004 | default 5 |
47ab0dee RK |
1005 | |
1006 | config ARM_DMA_MEM_BUFFERABLE | |
e399b1a4 | 1007 | bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 |
e399b1a4 | 1008 | default y if CPU_V6 || CPU_V6K || CPU_V7 |
47ab0dee RK |
1009 | help |
1010 | Historically, the kernel has used strongly ordered mappings to | |
1011 | provide DMA coherent memory. With the advent of ARMv7, mapping | |
1012 | memory with differing types results in unpredictable behaviour, | |
1013 | so on these CPUs, this option is forced on. | |
1014 | ||
1015 | Multiple mappings with differing attributes is also unpredictable | |
1016 | on ARMv6 CPUs, but since they do not have aggressive speculative | |
1017 | prefetch, no harm appears to occur. | |
1018 | ||
1019 | However, drivers may be missing the necessary barriers for ARMv6, | |
1020 | and therefore turning this on may result in unpredictable driver | |
1021 | behaviour. Therefore, we offer this as an option. | |
1022 | ||
1023 | You are recommended say 'Y' here and debug any affected drivers. | |
ac1d426e | 1024 | |
e7c5650f CM |
1025 | config ARCH_HAS_BARRIERS |
1026 | bool | |
1027 | help | |
1028 | This option allows the use of custom mandatory barriers | |
1029 | included via the mach/barriers.h file. | |
d10d2d48 | 1030 | |
f8130906 RK |
1031 | config ARM_HEAVY_MB |
1032 | bool | |
1033 | ||
d10d2d48 BD |
1034 | config ARCH_SUPPORTS_BIG_ENDIAN |
1035 | bool | |
1036 | help | |
1037 | This option specifies the architecture can support big endian | |
1038 | operation. | |
1e6b4811 | 1039 | |
25362dc4 KC |
1040 | config DEBUG_RODATA |
1041 | bool "Make kernel text and rodata read-only" | |
ac96680d | 1042 | depends on MMU && !XIP_KERNEL |
25362dc4 | 1043 | default y if CPU_V7 |
1e6b4811 | 1044 | help |
25362dc4 KC |
1045 | If this is set, kernel text and rodata memory will be made |
1046 | read-only, and non-text kernel memory will be made non-executable. | |
1047 | The tradeoff is that each region is padded to section-size (1MiB) | |
1048 | boundaries (because their permissions are different and splitting | |
1049 | the 1M pages into 4K ones causes TLB performance problems), which | |
1050 | can waste memory. | |
80d6b0c2 | 1051 | |
25362dc4 KC |
1052 | config DEBUG_ALIGN_RODATA |
1053 | bool "Make rodata strictly non-executable" | |
1054 | depends on DEBUG_RODATA | |
80d6b0c2 KC |
1055 | default y |
1056 | help | |
25362dc4 KC |
1057 | If this is set, rodata will be made explicitly non-executable. This |
1058 | provides protection on the rare chance that attackers might find and | |
1059 | use ROP gadgets that exist in the rodata section. This adds an | |
1060 | additional section-aligned split of rodata from kernel text so it | |
1061 | can be made explicitly non-executable. This padding may waste memory | |
1062 | space to gain the additional protection. |