Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | comment "Processor Type" |
2 | ||
1da177e4 LT |
3 | # Select CPU types depending on the architecture selected. This selects |
4 | # which CPUs we support in the kernel image, and the compiler instruction | |
5 | # optimiser behaviour. | |
6 | ||
7 | # ARM610 | |
8 | config CPU_ARM610 | |
c750815e | 9 | bool "Support ARM610 processor" if ARCH_RPC |
1da177e4 LT |
10 | select CPU_32v3 |
11 | select CPU_CACHE_V3 | |
12 | select CPU_CACHE_VIVT | |
fefdaa06 | 13 | select CPU_CP15_MMU |
f9c21a6e HC |
14 | select CPU_COPY_V3 if MMU |
15 | select CPU_TLB_V3 if MMU | |
4fb28474 | 16 | select CPU_PABRT_LEGACY |
1da177e4 LT |
17 | help |
18 | The ARM610 is the successor to the ARM3 processor | |
19 | and was produced by VLSI Technology Inc. | |
20 | ||
21 | Say Y if you want support for the ARM610 processor. | |
22 | Otherwise, say N. | |
23 | ||
07e0da78 HC |
24 | # ARM7TDMI |
25 | config CPU_ARM7TDMI | |
26 | bool "Support ARM7TDMI processor" | |
6b237a35 | 27 | depends on !MMU |
07e0da78 HC |
28 | select CPU_32v4T |
29 | select CPU_ABRT_LV4T | |
4fb28474 | 30 | select CPU_PABRT_LEGACY |
07e0da78 HC |
31 | select CPU_CACHE_V4 |
32 | help | |
33 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
34 | which has no memory control unit and cache. | |
35 | ||
36 | Say Y if you want support for the ARM7TDMI processor. | |
37 | Otherwise, say N. | |
38 | ||
1da177e4 LT |
39 | # ARM710 |
40 | config CPU_ARM710 | |
c750815e | 41 | bool "Support ARM710 processor" if ARCH_RPC |
1da177e4 LT |
42 | select CPU_32v3 |
43 | select CPU_CACHE_V3 | |
44 | select CPU_CACHE_VIVT | |
fefdaa06 | 45 | select CPU_CP15_MMU |
f9c21a6e HC |
46 | select CPU_COPY_V3 if MMU |
47 | select CPU_TLB_V3 if MMU | |
4fb28474 | 48 | select CPU_PABRT_LEGACY |
1da177e4 LT |
49 | help |
50 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
51 | designed by Advanced RISC Machines Ltd. The ARM710 is the | |
52 | successor to the ARM610 processor. It was released in | |
53 | July 1994 by VLSI Technology Inc. | |
54 | ||
55 | Say Y if you want support for the ARM710 processor. | |
56 | Otherwise, say N. | |
57 | ||
58 | # ARM720T | |
59 | config CPU_ARM720T | |
c750815e | 60 | bool "Support ARM720T processor" if ARCH_INTEGRATOR |
260e98ed | 61 | select CPU_32v4T |
1da177e4 | 62 | select CPU_ABRT_LV4T |
4fb28474 | 63 | select CPU_PABRT_LEGACY |
1da177e4 LT |
64 | select CPU_CACHE_V4 |
65 | select CPU_CACHE_VIVT | |
fefdaa06 | 66 | select CPU_CP15_MMU |
f9c21a6e HC |
67 | select CPU_COPY_V4WT if MMU |
68 | select CPU_TLB_V4WT if MMU | |
1da177e4 LT |
69 | help |
70 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
71 | MMU built around an ARM7TDMI core. | |
72 | ||
73 | Say Y if you want support for the ARM720T processor. | |
74 | Otherwise, say N. | |
75 | ||
b731c311 HC |
76 | # ARM740T |
77 | config CPU_ARM740T | |
78 | bool "Support ARM740T processor" if ARCH_INTEGRATOR | |
6b237a35 | 79 | depends on !MMU |
b731c311 HC |
80 | select CPU_32v4T |
81 | select CPU_ABRT_LV4T | |
4fb28474 | 82 | select CPU_PABRT_LEGACY |
b731c311 HC |
83 | select CPU_CACHE_V3 # although the core is v4t |
84 | select CPU_CP15_MPU | |
85 | help | |
86 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
87 | write buffer and MPU(Protection Unit) built around | |
88 | an ARM7TDMI core. | |
89 | ||
90 | Say Y if you want support for the ARM740T processor. | |
91 | Otherwise, say N. | |
92 | ||
43f5f014 HC |
93 | # ARM9TDMI |
94 | config CPU_ARM9TDMI | |
95 | bool "Support ARM9TDMI processor" | |
6b237a35 | 96 | depends on !MMU |
43f5f014 | 97 | select CPU_32v4T |
0f45d7f3 | 98 | select CPU_ABRT_NOMMU |
4fb28474 | 99 | select CPU_PABRT_LEGACY |
43f5f014 HC |
100 | select CPU_CACHE_V4 |
101 | help | |
102 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
103 | which has no memory control unit and cache. | |
104 | ||
105 | Say Y if you want support for the ARM9TDMI processor. | |
106 | Otherwise, say N. | |
107 | ||
1da177e4 LT |
108 | # ARM920T |
109 | config CPU_ARM920T | |
c750815e | 110 | bool "Support ARM920T processor" if ARCH_INTEGRATOR |
260e98ed | 111 | select CPU_32v4T |
1da177e4 | 112 | select CPU_ABRT_EV4T |
4fb28474 | 113 | select CPU_PABRT_LEGACY |
1da177e4 LT |
114 | select CPU_CACHE_V4WT |
115 | select CPU_CACHE_VIVT | |
fefdaa06 | 116 | select CPU_CP15_MMU |
f9c21a6e HC |
117 | select CPU_COPY_V4WB if MMU |
118 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
119 | help |
120 | The ARM920T is licensed to be produced by numerous vendors, | |
c768e676 | 121 | and is used in the Cirrus EP93xx and the Samsung S3C2410. |
1da177e4 LT |
122 | |
123 | Say Y if you want support for the ARM920T processor. | |
124 | Otherwise, say N. | |
125 | ||
126 | # ARM922T | |
127 | config CPU_ARM922T | |
128 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | |
260e98ed | 129 | select CPU_32v4T |
1da177e4 | 130 | select CPU_ABRT_EV4T |
4fb28474 | 131 | select CPU_PABRT_LEGACY |
1da177e4 LT |
132 | select CPU_CACHE_V4WT |
133 | select CPU_CACHE_VIVT | |
fefdaa06 | 134 | select CPU_CP15_MMU |
f9c21a6e HC |
135 | select CPU_COPY_V4WB if MMU |
136 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
137 | help |
138 | The ARM922T is a version of the ARM920T, but with smaller | |
139 | instruction and data caches. It is used in Altera's | |
c53c9cf6 | 140 | Excalibur XA device family and Micrel's KS8695 Centaur. |
1da177e4 LT |
141 | |
142 | Say Y if you want support for the ARM922T processor. | |
143 | Otherwise, say N. | |
144 | ||
145 | # ARM925T | |
146 | config CPU_ARM925T | |
b288f75f | 147 | bool "Support ARM925T processor" if ARCH_OMAP1 |
260e98ed | 148 | select CPU_32v4T |
1da177e4 | 149 | select CPU_ABRT_EV4T |
4fb28474 | 150 | select CPU_PABRT_LEGACY |
1da177e4 LT |
151 | select CPU_CACHE_V4WT |
152 | select CPU_CACHE_VIVT | |
fefdaa06 | 153 | select CPU_CP15_MMU |
f9c21a6e HC |
154 | select CPU_COPY_V4WB if MMU |
155 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
156 | help |
157 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
158 | different instruction and data caches. It is used in TI's OMAP | |
159 | device family. | |
160 | ||
161 | Say Y if you want support for the ARM925T processor. | |
162 | Otherwise, say N. | |
163 | ||
164 | # ARM926T | |
165 | config CPU_ARM926T | |
c750815e | 166 | bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
1da177e4 LT |
167 | select CPU_32v5 |
168 | select CPU_ABRT_EV5TJ | |
4fb28474 | 169 | select CPU_PABRT_LEGACY |
1da177e4 | 170 | select CPU_CACHE_VIVT |
fefdaa06 | 171 | select CPU_CP15_MMU |
f9c21a6e HC |
172 | select CPU_COPY_V4WB if MMU |
173 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
174 | help |
175 | This is a variant of the ARM920. It has slightly different | |
176 | instruction sequences for cache and TLB operations. Curiously, | |
177 | there is no documentation on it at the ARM corporate website. | |
178 | ||
179 | Say Y if you want support for the ARM926T processor. | |
180 | Otherwise, say N. | |
181 | ||
28853ac8 PZ |
182 | # FA526 |
183 | config CPU_FA526 | |
184 | bool | |
185 | select CPU_32v4 | |
186 | select CPU_ABRT_EV4 | |
4fb28474 | 187 | select CPU_PABRT_LEGACY |
28853ac8 PZ |
188 | select CPU_CACHE_VIVT |
189 | select CPU_CP15_MMU | |
190 | select CPU_CACHE_FA | |
191 | select CPU_COPY_FA if MMU | |
192 | select CPU_TLB_FA if MMU | |
193 | help | |
194 | The FA526 is a version of the ARMv4 compatible processor with | |
195 | Branch Target Buffer, Unified TLB and cache line size 16. | |
196 | ||
197 | Say Y if you want support for the FA526 processor. | |
198 | Otherwise, say N. | |
199 | ||
d60674eb HC |
200 | # ARM940T |
201 | config CPU_ARM940T | |
202 | bool "Support ARM940T processor" if ARCH_INTEGRATOR | |
6b237a35 | 203 | depends on !MMU |
d60674eb | 204 | select CPU_32v4T |
0f45d7f3 | 205 | select CPU_ABRT_NOMMU |
4fb28474 | 206 | select CPU_PABRT_LEGACY |
d60674eb HC |
207 | select CPU_CACHE_VIVT |
208 | select CPU_CP15_MPU | |
209 | help | |
210 | ARM940T is a member of the ARM9TDMI family of general- | |
3cb2fccc | 211 | purpose microprocessors with MPU and separate 4KB |
d60674eb HC |
212 | instruction and 4KB data cases, each with a 4-word line |
213 | length. | |
214 | ||
215 | Say Y if you want support for the ARM940T processor. | |
216 | Otherwise, say N. | |
217 | ||
f37f46eb HC |
218 | # ARM946E-S |
219 | config CPU_ARM946E | |
220 | bool "Support ARM946E-S processor" if ARCH_INTEGRATOR | |
6b237a35 | 221 | depends on !MMU |
f37f46eb | 222 | select CPU_32v5 |
0f45d7f3 | 223 | select CPU_ABRT_NOMMU |
4fb28474 | 224 | select CPU_PABRT_LEGACY |
f37f46eb HC |
225 | select CPU_CACHE_VIVT |
226 | select CPU_CP15_MPU | |
227 | help | |
228 | ARM946E-S is a member of the ARM9E-S family of high- | |
229 | performance, 32-bit system-on-chip processor solutions. | |
230 | The TCM and ARMv5TE 32-bit instruction set is supported. | |
231 | ||
232 | Say Y if you want support for the ARM946E-S processor. | |
233 | Otherwise, say N. | |
234 | ||
1da177e4 LT |
235 | # ARM1020 - needs validating |
236 | config CPU_ARM1020 | |
c750815e | 237 | bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR |
1da177e4 LT |
238 | select CPU_32v5 |
239 | select CPU_ABRT_EV4T | |
4fb28474 | 240 | select CPU_PABRT_LEGACY |
1da177e4 LT |
241 | select CPU_CACHE_V4WT |
242 | select CPU_CACHE_VIVT | |
fefdaa06 | 243 | select CPU_CP15_MMU |
f9c21a6e HC |
244 | select CPU_COPY_V4WB if MMU |
245 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
246 | help |
247 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
248 | with an addition of a floating-point unit. | |
249 | ||
250 | Say Y if you want support for the ARM1020 processor. | |
251 | Otherwise, say N. | |
252 | ||
253 | # ARM1020E - needs validating | |
254 | config CPU_ARM1020E | |
c750815e | 255 | bool "Support ARM1020E processor" if ARCH_INTEGRATOR |
1da177e4 LT |
256 | select CPU_32v5 |
257 | select CPU_ABRT_EV4T | |
4fb28474 | 258 | select CPU_PABRT_LEGACY |
1da177e4 LT |
259 | select CPU_CACHE_V4WT |
260 | select CPU_CACHE_VIVT | |
fefdaa06 | 261 | select CPU_CP15_MMU |
f9c21a6e HC |
262 | select CPU_COPY_V4WB if MMU |
263 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
264 | depends on n |
265 | ||
266 | # ARM1022E | |
267 | config CPU_ARM1022 | |
c750815e | 268 | bool "Support ARM1022E processor" if ARCH_INTEGRATOR |
1da177e4 LT |
269 | select CPU_32v5 |
270 | select CPU_ABRT_EV4T | |
4fb28474 | 271 | select CPU_PABRT_LEGACY |
1da177e4 | 272 | select CPU_CACHE_VIVT |
fefdaa06 | 273 | select CPU_CP15_MMU |
f9c21a6e HC |
274 | select CPU_COPY_V4WB if MMU # can probably do better |
275 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
276 | help |
277 | The ARM1022E is an implementation of the ARMv5TE architecture | |
278 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
279 | embedded trace macrocell, and a floating-point unit. | |
280 | ||
281 | Say Y if you want support for the ARM1022E processor. | |
282 | Otherwise, say N. | |
283 | ||
284 | # ARM1026EJ-S | |
285 | config CPU_ARM1026 | |
c750815e | 286 | bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR |
1da177e4 LT |
287 | select CPU_32v5 |
288 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
4fb28474 | 289 | select CPU_PABRT_LEGACY |
1da177e4 | 290 | select CPU_CACHE_VIVT |
fefdaa06 | 291 | select CPU_CP15_MMU |
f9c21a6e HC |
292 | select CPU_COPY_V4WB if MMU # can probably do better |
293 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
294 | help |
295 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
296 | based upon the ARM10 integer core. | |
297 | ||
298 | Say Y if you want support for the ARM1026EJ-S processor. | |
299 | Otherwise, say N. | |
300 | ||
301 | # SA110 | |
302 | config CPU_SA110 | |
c750815e | 303 | bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC |
1da177e4 LT |
304 | select CPU_32v3 if ARCH_RPC |
305 | select CPU_32v4 if !ARCH_RPC | |
306 | select CPU_ABRT_EV4 | |
4fb28474 | 307 | select CPU_PABRT_LEGACY |
1da177e4 LT |
308 | select CPU_CACHE_V4WB |
309 | select CPU_CACHE_VIVT | |
fefdaa06 | 310 | select CPU_CP15_MMU |
f9c21a6e HC |
311 | select CPU_COPY_V4WB if MMU |
312 | select CPU_TLB_V4WB if MMU | |
1da177e4 LT |
313 | help |
314 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
315 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
316 | More information is available at | |
317 | <http://developer.intel.com/design/strong/sa110.htm>. | |
318 | ||
319 | Say Y if you want support for the SA-110 processor. | |
320 | Otherwise, say N. | |
321 | ||
322 | # SA1100 | |
323 | config CPU_SA1100 | |
324 | bool | |
1da177e4 LT |
325 | select CPU_32v4 |
326 | select CPU_ABRT_EV4 | |
4fb28474 | 327 | select CPU_PABRT_LEGACY |
1da177e4 LT |
328 | select CPU_CACHE_V4WB |
329 | select CPU_CACHE_VIVT | |
fefdaa06 | 330 | select CPU_CP15_MMU |
f9c21a6e | 331 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
332 | |
333 | # XScale | |
334 | config CPU_XSCALE | |
335 | bool | |
1da177e4 LT |
336 | select CPU_32v5 |
337 | select CPU_ABRT_EV5T | |
4fb28474 | 338 | select CPU_PABRT_LEGACY |
1da177e4 | 339 | select CPU_CACHE_VIVT |
fefdaa06 | 340 | select CPU_CP15_MMU |
f9c21a6e | 341 | select CPU_TLB_V4WBI if MMU |
1da177e4 | 342 | |
23bdf86a LB |
343 | # XScale Core Version 3 |
344 | config CPU_XSC3 | |
345 | bool | |
23bdf86a LB |
346 | select CPU_32v5 |
347 | select CPU_ABRT_EV5T | |
4fb28474 | 348 | select CPU_PABRT_LEGACY |
23bdf86a | 349 | select CPU_CACHE_VIVT |
fefdaa06 | 350 | select CPU_CP15_MMU |
f9c21a6e | 351 | select CPU_TLB_V4WBI if MMU |
23bdf86a LB |
352 | select IO_36 |
353 | ||
49cbe786 EM |
354 | # Marvell PJ1 (Mohawk) |
355 | config CPU_MOHAWK | |
356 | bool | |
357 | select CPU_32v5 | |
358 | select CPU_ABRT_EV5T | |
4fb28474 | 359 | select CPU_PABRT_LEGACY |
49cbe786 EM |
360 | select CPU_CACHE_VIVT |
361 | select CPU_CP15_MMU | |
362 | select CPU_TLB_V4WBI if MMU | |
363 | select CPU_COPY_V4WB if MMU | |
364 | ||
e50d6409 AH |
365 | # Feroceon |
366 | config CPU_FEROCEON | |
367 | bool | |
e50d6409 AH |
368 | select CPU_32v5 |
369 | select CPU_ABRT_EV5T | |
4fb28474 | 370 | select CPU_PABRT_LEGACY |
e50d6409 AH |
371 | select CPU_CACHE_VIVT |
372 | select CPU_CP15_MMU | |
0ed15071 | 373 | select CPU_COPY_FEROCEON if MMU |
99c6dc11 | 374 | select CPU_TLB_FEROCEON if MMU |
e50d6409 | 375 | |
d910a0aa TP |
376 | config CPU_FEROCEON_OLD_ID |
377 | bool "Accept early Feroceon cores with an ARM926 ID" | |
378 | depends on CPU_FEROCEON && !CPU_ARM926T | |
379 | default y | |
380 | help | |
381 | This enables the usage of some old Feroceon cores | |
382 | for which the CPU ID is equal to the ARM926 ID. | |
383 | Relevant for Feroceon-1850 and early Feroceon-2850. | |
384 | ||
a4553358 HZ |
385 | # Marvell PJ4 |
386 | config CPU_PJ4 | |
387 | bool | |
388 | select CPU_V7 | |
389 | select ARM_THUMBEE | |
390 | ||
1da177e4 LT |
391 | # ARMv6 |
392 | config CPU_V6 | |
c786282e | 393 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
1da177e4 LT |
394 | select CPU_32v6 |
395 | select CPU_ABRT_EV6 | |
4fb28474 | 396 | select CPU_PABRT_V6 |
1da177e4 LT |
397 | select CPU_CACHE_V6 |
398 | select CPU_CACHE_VIPT | |
fefdaa06 | 399 | select CPU_CP15_MMU |
7b4c965a | 400 | select CPU_HAS_ASID if MMU |
f9c21a6e HC |
401 | select CPU_COPY_V6 if MMU |
402 | select CPU_TLB_V6 if MMU | |
1da177e4 | 403 | |
4a5f79e7 | 404 | # ARMv6k |
e399b1a4 | 405 | config CPU_V6K |
c786282e | 406 | bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
e399b1a4 RK |
407 | select CPU_32v6 |
408 | select CPU_32v6K if !ARCH_OMAP2 | |
409 | select CPU_ABRT_EV6 | |
410 | select CPU_PABRT_V6 | |
411 | select CPU_CACHE_V6 | |
412 | select CPU_CACHE_VIPT | |
413 | select CPU_CP15_MMU | |
414 | select CPU_HAS_ASID if MMU | |
415 | select CPU_COPY_V6 if MMU | |
416 | select CPU_TLB_V6 if MMU | |
4a5f79e7 | 417 | |
23688e99 CM |
418 | # ARMv7 |
419 | config CPU_V7 | |
1b504bbe | 420 | bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
1a28e3d9 | 421 | select CPU_32v6K if !ARCH_OMAP2 |
23688e99 CM |
422 | select CPU_32v7 |
423 | select CPU_ABRT_EV7 | |
4fb28474 | 424 | select CPU_PABRT_V7 |
23688e99 CM |
425 | select CPU_CACHE_V7 |
426 | select CPU_CACHE_VIPT | |
427 | select CPU_CP15_MMU | |
2eb8c82b | 428 | select CPU_HAS_ASID if MMU |
23688e99 | 429 | select CPU_COPY_V6 if MMU |
2ccdd1e7 | 430 | select CPU_TLB_V7 if MMU |
23688e99 | 431 | |
1da177e4 LT |
432 | # Figure out what processor architecture version we should be using. |
433 | # This defines the compiler instruction set which depends on the machine type. | |
434 | config CPU_32v3 | |
435 | bool | |
60b6cf68 | 436 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 437 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
8762df4d | 438 | select CPU_USE_DOMAINS if MMU |
1da177e4 LT |
439 | |
440 | config CPU_32v4 | |
441 | bool | |
60b6cf68 | 442 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 443 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
8762df4d | 444 | select CPU_USE_DOMAINS if MMU |
1da177e4 | 445 | |
260e98ed LB |
446 | config CPU_32v4T |
447 | bool | |
448 | select TLS_REG_EMUL if SMP || !MMU | |
449 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | |
8762df4d | 450 | select CPU_USE_DOMAINS if MMU |
260e98ed | 451 | |
1da177e4 LT |
452 | config CPU_32v5 |
453 | bool | |
60b6cf68 | 454 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 455 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
8762df4d | 456 | select CPU_USE_DOMAINS if MMU |
1da177e4 LT |
457 | |
458 | config CPU_32v6 | |
459 | bool | |
367afaf8 | 460 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
8762df4d | 461 | select CPU_USE_DOMAINS if CPU_V6 && MMU |
1da177e4 | 462 | |
e399b1a4 RK |
463 | config CPU_32v6K |
464 | bool "Support ARM V6K processor extensions" if !SMP | |
465 | depends on CPU_V6 || CPU_V6K || CPU_V7 | |
466 | default y if SMP && !(ARCH_MX3 || ARCH_OMAP2) | |
467 | help | |
468 | Say Y here if your ARMv6 processor supports the 'K' extension. | |
469 | This enables the kernel to use some instructions not present | |
470 | on previous processors, and as such a kernel build with this | |
471 | enabled will not boot on processors with do not support these | |
472 | instructions. | |
473 | ||
23688e99 CM |
474 | config CPU_32v7 |
475 | bool | |
476 | ||
1da177e4 | 477 | # The abort model |
0f45d7f3 HC |
478 | config CPU_ABRT_NOMMU |
479 | bool | |
480 | ||
1da177e4 LT |
481 | config CPU_ABRT_EV4 |
482 | bool | |
483 | ||
484 | config CPU_ABRT_EV4T | |
485 | bool | |
486 | ||
487 | config CPU_ABRT_LV4T | |
488 | bool | |
489 | ||
490 | config CPU_ABRT_EV5T | |
491 | bool | |
492 | ||
493 | config CPU_ABRT_EV5TJ | |
494 | bool | |
495 | ||
496 | config CPU_ABRT_EV6 | |
497 | bool | |
498 | ||
23688e99 CM |
499 | config CPU_ABRT_EV7 |
500 | bool | |
501 | ||
4fb28474 | 502 | config CPU_PABRT_LEGACY |
48d7927b PB |
503 | bool |
504 | ||
4fb28474 KS |
505 | config CPU_PABRT_V6 |
506 | bool | |
507 | ||
508 | config CPU_PABRT_V7 | |
48d7927b PB |
509 | bool |
510 | ||
1da177e4 LT |
511 | # The cache model |
512 | config CPU_CACHE_V3 | |
513 | bool | |
514 | ||
515 | config CPU_CACHE_V4 | |
516 | bool | |
517 | ||
518 | config CPU_CACHE_V4WT | |
519 | bool | |
520 | ||
521 | config CPU_CACHE_V4WB | |
522 | bool | |
523 | ||
524 | config CPU_CACHE_V6 | |
525 | bool | |
526 | ||
23688e99 CM |
527 | config CPU_CACHE_V7 |
528 | bool | |
529 | ||
1da177e4 LT |
530 | config CPU_CACHE_VIVT |
531 | bool | |
532 | ||
533 | config CPU_CACHE_VIPT | |
534 | bool | |
535 | ||
28853ac8 PZ |
536 | config CPU_CACHE_FA |
537 | bool | |
538 | ||
f9c21a6e | 539 | if MMU |
1da177e4 LT |
540 | # The copy-page model |
541 | config CPU_COPY_V3 | |
542 | bool | |
543 | ||
544 | config CPU_COPY_V4WT | |
545 | bool | |
546 | ||
547 | config CPU_COPY_V4WB | |
548 | bool | |
549 | ||
0ed15071 LB |
550 | config CPU_COPY_FEROCEON |
551 | bool | |
552 | ||
28853ac8 PZ |
553 | config CPU_COPY_FA |
554 | bool | |
555 | ||
1da177e4 LT |
556 | config CPU_COPY_V6 |
557 | bool | |
558 | ||
559 | # This selects the TLB model | |
560 | config CPU_TLB_V3 | |
561 | bool | |
562 | help | |
563 | ARM Architecture Version 3 TLB. | |
564 | ||
565 | config CPU_TLB_V4WT | |
566 | bool | |
567 | help | |
568 | ARM Architecture Version 4 TLB with writethrough cache. | |
569 | ||
570 | config CPU_TLB_V4WB | |
571 | bool | |
572 | help | |
573 | ARM Architecture Version 4 TLB with writeback cache. | |
574 | ||
575 | config CPU_TLB_V4WBI | |
576 | bool | |
577 | help | |
578 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
579 | instruction cache entry. | |
580 | ||
99c6dc11 LB |
581 | config CPU_TLB_FEROCEON |
582 | bool | |
583 | help | |
584 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | |
585 | ||
28853ac8 PZ |
586 | config CPU_TLB_FA |
587 | bool | |
588 | help | |
589 | Faraday ARM FA526 architecture, unified TLB with writeback cache | |
590 | and invalidate instruction cache entry. Branch target buffer is | |
591 | also supported. | |
592 | ||
1da177e4 LT |
593 | config CPU_TLB_V6 |
594 | bool | |
595 | ||
2ccdd1e7 CM |
596 | config CPU_TLB_V7 |
597 | bool | |
598 | ||
e220ba60 DE |
599 | config VERIFY_PERMISSION_FAULT |
600 | bool | |
f9c21a6e HC |
601 | endif |
602 | ||
516793c6 RK |
603 | config CPU_HAS_ASID |
604 | bool | |
605 | help | |
606 | This indicates whether the CPU has the ASID register; used to | |
607 | tag TLB and possibly cache entries. | |
608 | ||
fefdaa06 HC |
609 | config CPU_CP15 |
610 | bool | |
611 | help | |
612 | Processor has the CP15 register. | |
613 | ||
614 | config CPU_CP15_MMU | |
615 | bool | |
616 | select CPU_CP15 | |
617 | help | |
618 | Processor has the CP15 register, which has MMU related registers. | |
619 | ||
620 | config CPU_CP15_MPU | |
621 | bool | |
622 | select CPU_CP15 | |
623 | help | |
624 | Processor has the CP15 register, which has MPU related registers. | |
625 | ||
247055aa CM |
626 | config CPU_USE_DOMAINS |
627 | bool | |
247055aa CM |
628 | help |
629 | This option enables or disables the use of domain switching | |
630 | via the set_fs() function. | |
631 | ||
23bdf86a LB |
632 | # |
633 | # CPU supports 36-bit I/O | |
634 | # | |
635 | config IO_36 | |
636 | bool | |
637 | ||
1da177e4 LT |
638 | comment "Processor Features" |
639 | ||
640 | config ARM_THUMB | |
641 | bool "Support Thumb user binaries" | |
e399b1a4 | 642 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
643 | default y |
644 | help | |
645 | Say Y if you want to include kernel support for running user space | |
646 | Thumb binaries. | |
647 | ||
648 | The Thumb instruction set is a compressed form of the standard ARM | |
649 | instruction set resulting in smaller binaries at the expense of | |
650 | slightly less efficient code. | |
651 | ||
652 | If you don't know what this all is, saying Y is a safe choice. | |
653 | ||
d7f864be CM |
654 | config ARM_THUMBEE |
655 | bool "Enable ThumbEE CPU extension" | |
656 | depends on CPU_V7 | |
657 | help | |
658 | Say Y here if you have a CPU with the ThumbEE extension and code to | |
659 | make use of it. Say N for code that can run on CPUs without ThumbEE. | |
660 | ||
64d2dc38 LL |
661 | config SWP_EMULATE |
662 | bool "Emulate SWP/SWPB instructions" | |
e118a1df | 663 | depends on CPU_V7 && !CPU_V6 |
64d2dc38 LL |
664 | select HAVE_PROC_CPU if PROC_FS |
665 | default y if SMP | |
666 | help | |
667 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. | |
668 | ARMv7 multiprocessing extensions introduce the ability to disable | |
669 | these instructions, triggering an undefined instruction exception | |
670 | when executed. Say Y here to enable software emulation of these | |
671 | instructions for userspace (not kernel) using LDREX/STREX. | |
672 | Also creates /proc/cpu/swp_emulation for statistics. | |
673 | ||
674 | In some older versions of glibc [<=2.8] SWP is used during futex | |
675 | trylock() operations with the assumption that the code will not | |
676 | be preempted. This invalid assumption may be more likely to fail | |
677 | with SWP emulation enabled, leading to deadlock of the user | |
678 | application. | |
679 | ||
680 | NOTE: when accessing uncached shared regions, LDREX/STREX rely | |
681 | on an external transaction monitoring block called a global | |
682 | monitor to maintain update atomicity. If your system does not | |
683 | implement a global monitor, this option can cause programs that | |
684 | perform SWP operations to uncached memory to deadlock. | |
685 | ||
686 | If unsure, say Y. | |
687 | ||
1da177e4 LT |
688 | config CPU_BIG_ENDIAN |
689 | bool "Build big-endian kernel" | |
690 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
691 | help | |
692 | Say Y if you plan on running a kernel in big-endian mode. | |
693 | Note that your board must be properly built and your board | |
694 | port must properly enable any big-endian related features | |
695 | of your chipset/board/processor. | |
696 | ||
26584853 CM |
697 | config CPU_ENDIAN_BE8 |
698 | bool | |
699 | depends on CPU_BIG_ENDIAN | |
e399b1a4 | 700 | default CPU_V6 || CPU_V6K || CPU_V7 |
26584853 CM |
701 | help |
702 | Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. | |
703 | ||
704 | config CPU_ENDIAN_BE32 | |
705 | bool | |
706 | depends on CPU_BIG_ENDIAN | |
707 | default !CPU_ENDIAN_BE8 | |
708 | help | |
709 | Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. | |
710 | ||
6afd6fae | 711 | config CPU_HIGH_VECTOR |
6340aa61 | 712 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
6afd6fae | 713 | bool "Select the High exception vector" |
6afd6fae HC |
714 | help |
715 | Say Y here to select high exception vector(0xFFFF0000~). | |
716 | The exception vector can be vary depending on the platform | |
717 | design in nommu mode. If your platform needs to select | |
718 | high exception vector, say Y. | |
719 | Otherwise or if you are unsure, say N, and the low exception | |
720 | vector (0x00000000~) will be used. | |
721 | ||
1da177e4 | 722 | config CPU_ICACHE_DISABLE |
f12d0d7c HC |
723 | bool "Disable I-Cache (I-bit)" |
724 | depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) | |
1da177e4 LT |
725 | help |
726 | Say Y here to disable the processor instruction cache. Unless | |
727 | you have a reason not to or are unsure, say N. | |
728 | ||
729 | config CPU_DCACHE_DISABLE | |
f12d0d7c HC |
730 | bool "Disable D-Cache (C-bit)" |
731 | depends on CPU_CP15 | |
1da177e4 LT |
732 | help |
733 | Say Y here to disable the processor data cache. Unless | |
734 | you have a reason not to or are unsure, say N. | |
735 | ||
f37f46eb HC |
736 | config CPU_DCACHE_SIZE |
737 | hex | |
738 | depends on CPU_ARM740T || CPU_ARM946E | |
739 | default 0x00001000 if CPU_ARM740T | |
740 | default 0x00002000 # default size for ARM946E-S | |
741 | help | |
742 | Some cores are synthesizable to have various sized cache. For | |
743 | ARM946E-S case, it can vary from 0KB to 1MB. | |
744 | To support such cache operations, it is efficient to know the size | |
745 | before compile time. | |
746 | If your SoC is configured to have a different size, define the value | |
747 | here with proper conditions. | |
748 | ||
1da177e4 LT |
749 | config CPU_DCACHE_WRITETHROUGH |
750 | bool "Force write through D-cache" | |
28853ac8 | 751 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
1da177e4 LT |
752 | default y if CPU_ARM925T |
753 | help | |
754 | Say Y here to use the data cache in writethrough mode. Unless you | |
755 | specifically require this or are unsure, say N. | |
756 | ||
757 | config CPU_CACHE_ROUND_ROBIN | |
758 | bool "Round robin I and D cache replacement algorithm" | |
f37f46eb | 759 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
1da177e4 LT |
760 | help |
761 | Say Y here to use the predictable round-robin cache replacement | |
762 | policy. Unless you specifically require this or are unsure, say N. | |
763 | ||
764 | config CPU_BPREDICT_DISABLE | |
765 | bool "Disable branch prediction" | |
e399b1a4 | 766 | depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
1da177e4 LT |
767 | help |
768 | Say Y here to disable branch prediction. If unsure, say N. | |
2d2669b6 | 769 | |
4b0e07a5 NP |
770 | config TLS_REG_EMUL |
771 | bool | |
4b0e07a5 | 772 | help |
70489c88 NP |
773 | An SMP system using a pre-ARMv6 processor (there are apparently |
774 | a few prototypes like that in existence) and therefore access to | |
775 | that required register must be emulated. | |
4b0e07a5 | 776 | |
dcef1f63 NP |
777 | config NEEDS_SYSCALL_FOR_CMPXCHG |
778 | bool | |
dcef1f63 NP |
779 | help |
780 | SMP on a pre-ARMv6 processor? Well OK then. | |
781 | Forget about fast user space cmpxchg support. | |
782 | It is just not possible. | |
783 | ||
ad642d9f CM |
784 | config DMA_CACHE_RWFO |
785 | bool "Enable read/write for ownership DMA cache maintenance" | |
e399b1a4 | 786 | depends on (CPU_V6 || CPU_V6K) && SMP |
ad642d9f CM |
787 | default y |
788 | help | |
789 | The Snoop Control Unit on ARM11MPCore does not detect the | |
790 | cache maintenance operations and the dma_{map,unmap}_area() | |
791 | functions may leave stale cache entries on other CPUs. By | |
792 | enabling this option, Read or Write For Ownership in the ARMv6 | |
793 | DMA cache maintenance functions is performed. These LDR/STR | |
794 | instructions change the cache line state to shared or modified | |
795 | so that the cache operation has the desired effect. | |
796 | ||
797 | Note that the workaround is only valid on processors that do | |
798 | not perform speculative loads into the D-cache. For such | |
799 | processors, if cache maintenance operations are not broadcast | |
800 | in hardware, other workarounds are needed (e.g. cache | |
801 | maintenance broadcasting in software via FIQ). | |
802 | ||
953233dc CM |
803 | config OUTER_CACHE |
804 | bool | |
382266ad | 805 | |
319f551a CM |
806 | config OUTER_CACHE_SYNC |
807 | bool | |
808 | help | |
809 | The outer cache has a outer_cache_fns.sync function pointer | |
810 | that can be used to drain the write buffer of the outer cache. | |
811 | ||
99c6dc11 LB |
812 | config CACHE_FEROCEON_L2 |
813 | bool "Enable the Feroceon L2 cache controller" | |
794d15b2 | 814 | depends on ARCH_KIRKWOOD || ARCH_MV78XX0 |
99c6dc11 LB |
815 | default y |
816 | select OUTER_CACHE | |
817 | help | |
818 | This option enables the Feroceon L2 cache controller. | |
819 | ||
4360bb41 RS |
820 | config CACHE_FEROCEON_L2_WRITETHROUGH |
821 | bool "Force Feroceon L2 cache write through" | |
822 | depends on CACHE_FEROCEON_L2 | |
4360bb41 RS |
823 | help |
824 | Say Y here to use the Feroceon L2 cache in writethrough mode. | |
825 | Unless you specifically require this, say N for writeback mode. | |
826 | ||
382266ad | 827 | config CACHE_L2X0 |
ba927951 | 828 | bool "Enable the L2x0 outer cache controller" |
cb88214d | 829 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ |
8e797a7e | 830 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ |
0b019a41 | 831 | ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ |
6d9598e2 | 832 | ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE |
ba927951 | 833 | default y |
382266ad | 834 | select OUTER_CACHE |
23107c54 | 835 | select OUTER_CACHE_SYNC |
ba927951 CM |
836 | help |
837 | This option enables the L2x0 PrimeCell. | |
905a09d5 | 838 | |
9a6655e4 CM |
839 | config CACHE_PL310 |
840 | bool | |
841 | depends on CACHE_L2X0 | |
e399b1a4 | 842 | default y if CPU_V7 && !(CPU_V6 || CPU_V6K) |
9a6655e4 CM |
843 | help |
844 | This option enables optimisations for the PL310 cache | |
845 | controller. | |
846 | ||
573a652f LB |
847 | config CACHE_TAUROS2 |
848 | bool "Enable the Tauros2 L2 cache controller" | |
3f408fa0 | 849 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) |
573a652f LB |
850 | default y |
851 | select OUTER_CACHE | |
852 | help | |
853 | This option enables the Tauros2 L2 cache controller (as | |
854 | found on PJ1/PJ4). | |
855 | ||
905a09d5 EM |
856 | config CACHE_XSC3L2 |
857 | bool "Enable the L2 cache on XScale3" | |
858 | depends on CPU_XSC3 | |
859 | default y | |
860 | select OUTER_CACHE | |
861 | help | |
862 | This option enables the L2 cache on XScale3. | |
910a17e5 KS |
863 | |
864 | config ARM_L1_CACHE_SHIFT | |
865 | int | |
d6d502fa | 866 | default 6 if ARM_L1_CACHE_SHIFT_6 |
910a17e5 | 867 | default 5 |
47ab0dee RK |
868 | |
869 | config ARM_DMA_MEM_BUFFERABLE | |
e399b1a4 | 870 | bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 |
42c4dafe CM |
871 | depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ |
872 | MACH_REALVIEW_PB11MP) | |
e399b1a4 | 873 | default y if CPU_V6 || CPU_V6K || CPU_V7 |
47ab0dee RK |
874 | help |
875 | Historically, the kernel has used strongly ordered mappings to | |
876 | provide DMA coherent memory. With the advent of ARMv7, mapping | |
877 | memory with differing types results in unpredictable behaviour, | |
878 | so on these CPUs, this option is forced on. | |
879 | ||
880 | Multiple mappings with differing attributes is also unpredictable | |
881 | on ARMv6 CPUs, but since they do not have aggressive speculative | |
882 | prefetch, no harm appears to occur. | |
883 | ||
884 | However, drivers may be missing the necessary barriers for ARMv6, | |
885 | and therefore turning this on may result in unpredictable driver | |
886 | behaviour. Therefore, we offer this as an option. | |
887 | ||
888 | You are recommended say 'Y' here and debug any affected drivers. | |
ac1d426e | 889 | |
e7c5650f CM |
890 | config ARCH_HAS_BARRIERS |
891 | bool | |
892 | help | |
893 | This option allows the use of custom mandatory barriers | |
894 | included via the mach/barriers.h file. |