Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | comment "Processor Type" |
2 | ||
3 | config CPU_32 | |
4 | bool | |
5 | default y | |
6 | ||
7 | # Select CPU types depending on the architecture selected. This selects | |
8 | # which CPUs we support in the kernel image, and the compiler instruction | |
9 | # optimiser behaviour. | |
10 | ||
11 | # ARM610 | |
12 | config CPU_ARM610 | |
13 | bool "Support ARM610 processor" | |
14 | depends on ARCH_RPC | |
15 | select CPU_32v3 | |
16 | select CPU_CACHE_V3 | |
17 | select CPU_CACHE_VIVT | |
fefdaa06 | 18 | select CPU_CP15_MMU |
f9c21a6e HC |
19 | select CPU_COPY_V3 if MMU |
20 | select CPU_TLB_V3 if MMU | |
1da177e4 LT |
21 | help |
22 | The ARM610 is the successor to the ARM3 processor | |
23 | and was produced by VLSI Technology Inc. | |
24 | ||
25 | Say Y if you want support for the ARM610 processor. | |
26 | Otherwise, say N. | |
27 | ||
07e0da78 HC |
28 | # ARM7TDMI |
29 | config CPU_ARM7TDMI | |
30 | bool "Support ARM7TDMI processor" | |
31 | select CPU_32v4T | |
32 | select CPU_ABRT_LV4T | |
33 | select CPU_CACHE_V4 | |
34 | help | |
35 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
36 | which has no memory control unit and cache. | |
37 | ||
38 | Say Y if you want support for the ARM7TDMI processor. | |
39 | Otherwise, say N. | |
40 | ||
1da177e4 LT |
41 | # ARM710 |
42 | config CPU_ARM710 | |
43 | bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC | |
44 | default y if ARCH_CLPS7500 | |
45 | select CPU_32v3 | |
46 | select CPU_CACHE_V3 | |
47 | select CPU_CACHE_VIVT | |
fefdaa06 | 48 | select CPU_CP15_MMU |
f9c21a6e HC |
49 | select CPU_COPY_V3 if MMU |
50 | select CPU_TLB_V3 if MMU | |
1da177e4 LT |
51 | help |
52 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
53 | designed by Advanced RISC Machines Ltd. The ARM710 is the | |
54 | successor to the ARM610 processor. It was released in | |
55 | July 1994 by VLSI Technology Inc. | |
56 | ||
57 | Say Y if you want support for the ARM710 processor. | |
58 | Otherwise, say N. | |
59 | ||
60 | # ARM720T | |
61 | config CPU_ARM720T | |
62 | bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR | |
63 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X | |
260e98ed | 64 | select CPU_32v4T |
1da177e4 LT |
65 | select CPU_ABRT_LV4T |
66 | select CPU_CACHE_V4 | |
67 | select CPU_CACHE_VIVT | |
fefdaa06 | 68 | select CPU_CP15_MMU |
f9c21a6e HC |
69 | select CPU_COPY_V4WT if MMU |
70 | select CPU_TLB_V4WT if MMU | |
1da177e4 LT |
71 | help |
72 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
73 | MMU built around an ARM7TDMI core. | |
74 | ||
75 | Say Y if you want support for the ARM720T processor. | |
76 | Otherwise, say N. | |
77 | ||
b731c311 HC |
78 | # ARM740T |
79 | config CPU_ARM740T | |
80 | bool "Support ARM740T processor" if ARCH_INTEGRATOR | |
81 | select CPU_32v4T | |
82 | select CPU_ABRT_LV4T | |
83 | select CPU_CACHE_V3 # although the core is v4t | |
84 | select CPU_CP15_MPU | |
85 | help | |
86 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
87 | write buffer and MPU(Protection Unit) built around | |
88 | an ARM7TDMI core. | |
89 | ||
90 | Say Y if you want support for the ARM740T processor. | |
91 | Otherwise, say N. | |
92 | ||
43f5f014 HC |
93 | # ARM9TDMI |
94 | config CPU_ARM9TDMI | |
95 | bool "Support ARM9TDMI processor" | |
96 | select CPU_32v4T | |
97 | select CPU_ABRT_EV4T | |
98 | select CPU_CACHE_V4 | |
99 | help | |
100 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
101 | which has no memory control unit and cache. | |
102 | ||
103 | Say Y if you want support for the ARM9TDMI processor. | |
104 | Otherwise, say N. | |
105 | ||
1da177e4 LT |
106 | # ARM920T |
107 | config CPU_ARM920T | |
3434d9d9 BD |
108 | bool "Support ARM920T processor" |
109 | depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 | |
110 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 | |
260e98ed | 111 | select CPU_32v4T |
1da177e4 LT |
112 | select CPU_ABRT_EV4T |
113 | select CPU_CACHE_V4WT | |
114 | select CPU_CACHE_VIVT | |
fefdaa06 | 115 | select CPU_CP15_MMU |
f9c21a6e HC |
116 | select CPU_COPY_V4WB if MMU |
117 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
118 | help |
119 | The ARM920T is licensed to be produced by numerous vendors, | |
120 | and is used in the Maverick EP9312 and the Samsung S3C2410. | |
121 | ||
122 | More information on the Maverick EP9312 at | |
123 | <http://linuxdevices.com/products/PD2382866068.html>. | |
124 | ||
125 | Say Y if you want support for the ARM920T processor. | |
126 | Otherwise, say N. | |
127 | ||
128 | # ARM922T | |
129 | config CPU_ARM922T | |
130 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | |
0fec53a2 RK |
131 | depends on ARCH_LH7A40X || ARCH_INTEGRATOR |
132 | default y if ARCH_LH7A40X | |
260e98ed | 133 | select CPU_32v4T |
1da177e4 LT |
134 | select CPU_ABRT_EV4T |
135 | select CPU_CACHE_V4WT | |
136 | select CPU_CACHE_VIVT | |
fefdaa06 | 137 | select CPU_CP15_MMU |
f9c21a6e HC |
138 | select CPU_COPY_V4WB if MMU |
139 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
140 | help |
141 | The ARM922T is a version of the ARM920T, but with smaller | |
142 | instruction and data caches. It is used in Altera's | |
143 | Excalibur XA device family. | |
144 | ||
145 | Say Y if you want support for the ARM922T processor. | |
146 | Otherwise, say N. | |
147 | ||
148 | # ARM925T | |
149 | config CPU_ARM925T | |
b288f75f | 150 | bool "Support ARM925T processor" if ARCH_OMAP1 |
3179a019 TL |
151 | depends on ARCH_OMAP15XX |
152 | default y if ARCH_OMAP15XX | |
260e98ed | 153 | select CPU_32v4T |
1da177e4 LT |
154 | select CPU_ABRT_EV4T |
155 | select CPU_CACHE_V4WT | |
156 | select CPU_CACHE_VIVT | |
fefdaa06 | 157 | select CPU_CP15_MMU |
f9c21a6e HC |
158 | select CPU_COPY_V4WB if MMU |
159 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
160 | help |
161 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
162 | different instruction and data caches. It is used in TI's OMAP | |
163 | device family. | |
164 | ||
165 | Say Y if you want support for the ARM925T processor. | |
166 | Otherwise, say N. | |
167 | ||
168 | # ARM926T | |
169 | config CPU_ARM926T | |
8ad68bbf | 170 | bool "Support ARM926T processor" |
8fc5ffa0 AV |
171 | depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 |
172 | default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 | |
1da177e4 LT |
173 | select CPU_32v5 |
174 | select CPU_ABRT_EV5TJ | |
175 | select CPU_CACHE_VIVT | |
fefdaa06 | 176 | select CPU_CP15_MMU |
f9c21a6e HC |
177 | select CPU_COPY_V4WB if MMU |
178 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
179 | help |
180 | This is a variant of the ARM920. It has slightly different | |
181 | instruction sequences for cache and TLB operations. Curiously, | |
182 | there is no documentation on it at the ARM corporate website. | |
183 | ||
184 | Say Y if you want support for the ARM926T processor. | |
185 | Otherwise, say N. | |
186 | ||
d60674eb HC |
187 | # ARM940T |
188 | config CPU_ARM940T | |
189 | bool "Support ARM940T processor" if ARCH_INTEGRATOR | |
190 | select CPU_32v4T | |
191 | select CPU_ABRT_EV4T | |
192 | select CPU_CACHE_VIVT | |
193 | select CPU_CP15_MPU | |
194 | help | |
195 | ARM940T is a member of the ARM9TDMI family of general- | |
196 | purpose microprocessors with MPU and seperate 4KB | |
197 | instruction and 4KB data cases, each with a 4-word line | |
198 | length. | |
199 | ||
200 | Say Y if you want support for the ARM940T processor. | |
201 | Otherwise, say N. | |
202 | ||
1da177e4 LT |
203 | # ARM1020 - needs validating |
204 | config CPU_ARM1020 | |
205 | bool "Support ARM1020T (rev 0) processor" | |
206 | depends on ARCH_INTEGRATOR | |
207 | select CPU_32v5 | |
208 | select CPU_ABRT_EV4T | |
209 | select CPU_CACHE_V4WT | |
210 | select CPU_CACHE_VIVT | |
fefdaa06 | 211 | select CPU_CP15_MMU |
f9c21a6e HC |
212 | select CPU_COPY_V4WB if MMU |
213 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
214 | help |
215 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
216 | with an addition of a floating-point unit. | |
217 | ||
218 | Say Y if you want support for the ARM1020 processor. | |
219 | Otherwise, say N. | |
220 | ||
221 | # ARM1020E - needs validating | |
222 | config CPU_ARM1020E | |
223 | bool "Support ARM1020E processor" | |
224 | depends on ARCH_INTEGRATOR | |
225 | select CPU_32v5 | |
226 | select CPU_ABRT_EV4T | |
227 | select CPU_CACHE_V4WT | |
228 | select CPU_CACHE_VIVT | |
fefdaa06 | 229 | select CPU_CP15_MMU |
f9c21a6e HC |
230 | select CPU_COPY_V4WB if MMU |
231 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
232 | depends on n |
233 | ||
234 | # ARM1022E | |
235 | config CPU_ARM1022 | |
236 | bool "Support ARM1022E processor" | |
237 | depends on ARCH_INTEGRATOR | |
238 | select CPU_32v5 | |
239 | select CPU_ABRT_EV4T | |
240 | select CPU_CACHE_VIVT | |
fefdaa06 | 241 | select CPU_CP15_MMU |
f9c21a6e HC |
242 | select CPU_COPY_V4WB if MMU # can probably do better |
243 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
244 | help |
245 | The ARM1022E is an implementation of the ARMv5TE architecture | |
246 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
247 | embedded trace macrocell, and a floating-point unit. | |
248 | ||
249 | Say Y if you want support for the ARM1022E processor. | |
250 | Otherwise, say N. | |
251 | ||
252 | # ARM1026EJ-S | |
253 | config CPU_ARM1026 | |
254 | bool "Support ARM1026EJ-S processor" | |
255 | depends on ARCH_INTEGRATOR | |
256 | select CPU_32v5 | |
257 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
258 | select CPU_CACHE_VIVT | |
fefdaa06 | 259 | select CPU_CP15_MMU |
f9c21a6e HC |
260 | select CPU_COPY_V4WB if MMU # can probably do better |
261 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
262 | help |
263 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
264 | based upon the ARM10 integer core. | |
265 | ||
266 | Say Y if you want support for the ARM1026EJ-S processor. | |
267 | Otherwise, say N. | |
268 | ||
269 | # SA110 | |
270 | config CPU_SA110 | |
271 | bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC | |
272 | default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI | |
273 | select CPU_32v3 if ARCH_RPC | |
274 | select CPU_32v4 if !ARCH_RPC | |
275 | select CPU_ABRT_EV4 | |
276 | select CPU_CACHE_V4WB | |
277 | select CPU_CACHE_VIVT | |
fefdaa06 | 278 | select CPU_CP15_MMU |
f9c21a6e HC |
279 | select CPU_COPY_V4WB if MMU |
280 | select CPU_TLB_V4WB if MMU | |
1da177e4 LT |
281 | help |
282 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
283 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
284 | More information is available at | |
285 | <http://developer.intel.com/design/strong/sa110.htm>. | |
286 | ||
287 | Say Y if you want support for the SA-110 processor. | |
288 | Otherwise, say N. | |
289 | ||
290 | # SA1100 | |
291 | config CPU_SA1100 | |
292 | bool | |
293 | depends on ARCH_SA1100 | |
294 | default y | |
295 | select CPU_32v4 | |
296 | select CPU_ABRT_EV4 | |
297 | select CPU_CACHE_V4WB | |
298 | select CPU_CACHE_VIVT | |
fefdaa06 | 299 | select CPU_CP15_MMU |
f9c21a6e | 300 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
301 | |
302 | # XScale | |
303 | config CPU_XSCALE | |
304 | bool | |
3f7e5815 | 305 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 |
1da177e4 LT |
306 | default y |
307 | select CPU_32v5 | |
308 | select CPU_ABRT_EV5T | |
309 | select CPU_CACHE_VIVT | |
fefdaa06 | 310 | select CPU_CP15_MMU |
f9c21a6e | 311 | select CPU_TLB_V4WBI if MMU |
1da177e4 | 312 | |
23bdf86a LB |
313 | # XScale Core Version 3 |
314 | config CPU_XSC3 | |
315 | bool | |
316 | depends on ARCH_IXP23XX | |
317 | default y | |
318 | select CPU_32v5 | |
319 | select CPU_ABRT_EV5T | |
320 | select CPU_CACHE_VIVT | |
fefdaa06 | 321 | select CPU_CP15_MMU |
f9c21a6e | 322 | select CPU_TLB_V4WBI if MMU |
23bdf86a LB |
323 | select IO_36 |
324 | ||
1da177e4 LT |
325 | # ARMv6 |
326 | config CPU_V6 | |
327 | bool "Support ARM V6 processor" | |
1dbae815 | 328 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 |
1da177e4 LT |
329 | select CPU_32v6 |
330 | select CPU_ABRT_EV6 | |
331 | select CPU_CACHE_V6 | |
332 | select CPU_CACHE_VIPT | |
fefdaa06 | 333 | select CPU_CP15_MMU |
f9c21a6e HC |
334 | select CPU_COPY_V6 if MMU |
335 | select CPU_TLB_V6 if MMU | |
1da177e4 | 336 | |
4a5f79e7 RK |
337 | # ARMv6k |
338 | config CPU_32v6K | |
339 | bool "Support ARM V6K processor extensions" if !SMP | |
340 | depends on CPU_V6 | |
341 | default y if SMP | |
342 | help | |
343 | Say Y here if your ARMv6 processor supports the 'K' extension. | |
344 | This enables the kernel to use some instructions not present | |
345 | on previous processors, and as such a kernel build with this | |
346 | enabled will not boot on processors with do not support these | |
347 | instructions. | |
348 | ||
1da177e4 LT |
349 | # Figure out what processor architecture version we should be using. |
350 | # This defines the compiler instruction set which depends on the machine type. | |
351 | config CPU_32v3 | |
352 | bool | |
60b6cf68 | 353 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 354 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 LT |
355 | |
356 | config CPU_32v4 | |
357 | bool | |
60b6cf68 | 358 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 359 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 | 360 | |
260e98ed LB |
361 | config CPU_32v4T |
362 | bool | |
363 | select TLS_REG_EMUL if SMP || !MMU | |
364 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | |
365 | ||
1da177e4 LT |
366 | config CPU_32v5 |
367 | bool | |
60b6cf68 | 368 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 369 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 LT |
370 | |
371 | config CPU_32v6 | |
372 | bool | |
373 | ||
374 | # The abort model | |
375 | config CPU_ABRT_EV4 | |
376 | bool | |
377 | ||
378 | config CPU_ABRT_EV4T | |
379 | bool | |
380 | ||
381 | config CPU_ABRT_LV4T | |
382 | bool | |
383 | ||
384 | config CPU_ABRT_EV5T | |
385 | bool | |
386 | ||
387 | config CPU_ABRT_EV5TJ | |
388 | bool | |
389 | ||
390 | config CPU_ABRT_EV6 | |
391 | bool | |
392 | ||
393 | # The cache model | |
394 | config CPU_CACHE_V3 | |
395 | bool | |
396 | ||
397 | config CPU_CACHE_V4 | |
398 | bool | |
399 | ||
400 | config CPU_CACHE_V4WT | |
401 | bool | |
402 | ||
403 | config CPU_CACHE_V4WB | |
404 | bool | |
405 | ||
406 | config CPU_CACHE_V6 | |
407 | bool | |
408 | ||
409 | config CPU_CACHE_VIVT | |
410 | bool | |
411 | ||
412 | config CPU_CACHE_VIPT | |
413 | bool | |
414 | ||
f9c21a6e | 415 | if MMU |
1da177e4 LT |
416 | # The copy-page model |
417 | config CPU_COPY_V3 | |
418 | bool | |
419 | ||
420 | config CPU_COPY_V4WT | |
421 | bool | |
422 | ||
423 | config CPU_COPY_V4WB | |
424 | bool | |
425 | ||
426 | config CPU_COPY_V6 | |
427 | bool | |
428 | ||
429 | # This selects the TLB model | |
430 | config CPU_TLB_V3 | |
431 | bool | |
432 | help | |
433 | ARM Architecture Version 3 TLB. | |
434 | ||
435 | config CPU_TLB_V4WT | |
436 | bool | |
437 | help | |
438 | ARM Architecture Version 4 TLB with writethrough cache. | |
439 | ||
440 | config CPU_TLB_V4WB | |
441 | bool | |
442 | help | |
443 | ARM Architecture Version 4 TLB with writeback cache. | |
444 | ||
445 | config CPU_TLB_V4WBI | |
446 | bool | |
447 | help | |
448 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
449 | instruction cache entry. | |
450 | ||
451 | config CPU_TLB_V6 | |
452 | bool | |
453 | ||
f9c21a6e HC |
454 | endif |
455 | ||
fefdaa06 HC |
456 | config CPU_CP15 |
457 | bool | |
458 | help | |
459 | Processor has the CP15 register. | |
460 | ||
461 | config CPU_CP15_MMU | |
462 | bool | |
463 | select CPU_CP15 | |
464 | help | |
465 | Processor has the CP15 register, which has MMU related registers. | |
466 | ||
467 | config CPU_CP15_MPU | |
468 | bool | |
469 | select CPU_CP15 | |
470 | help | |
471 | Processor has the CP15 register, which has MPU related registers. | |
472 | ||
23bdf86a LB |
473 | # |
474 | # CPU supports 36-bit I/O | |
475 | # | |
476 | config IO_36 | |
477 | bool | |
478 | ||
1da177e4 LT |
479 | comment "Processor Features" |
480 | ||
481 | config ARM_THUMB | |
482 | bool "Support Thumb user binaries" | |
d60674eb | 483 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 |
1da177e4 LT |
484 | default y |
485 | help | |
486 | Say Y if you want to include kernel support for running user space | |
487 | Thumb binaries. | |
488 | ||
489 | The Thumb instruction set is a compressed form of the standard ARM | |
490 | instruction set resulting in smaller binaries at the expense of | |
491 | slightly less efficient code. | |
492 | ||
493 | If you don't know what this all is, saying Y is a safe choice. | |
494 | ||
495 | config CPU_BIG_ENDIAN | |
496 | bool "Build big-endian kernel" | |
497 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
498 | help | |
499 | Say Y if you plan on running a kernel in big-endian mode. | |
500 | Note that your board must be properly built and your board | |
501 | port must properly enable any big-endian related features | |
502 | of your chipset/board/processor. | |
503 | ||
504 | config CPU_ICACHE_DISABLE | |
f12d0d7c HC |
505 | bool "Disable I-Cache (I-bit)" |
506 | depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) | |
1da177e4 LT |
507 | help |
508 | Say Y here to disable the processor instruction cache. Unless | |
509 | you have a reason not to or are unsure, say N. | |
510 | ||
511 | config CPU_DCACHE_DISABLE | |
f12d0d7c HC |
512 | bool "Disable D-Cache (C-bit)" |
513 | depends on CPU_CP15 | |
1da177e4 LT |
514 | help |
515 | Say Y here to disable the processor data cache. Unless | |
516 | you have a reason not to or are unsure, say N. | |
517 | ||
518 | config CPU_DCACHE_WRITETHROUGH | |
519 | bool "Force write through D-cache" | |
d60674eb | 520 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE |
1da177e4 LT |
521 | default y if CPU_ARM925T |
522 | help | |
523 | Say Y here to use the data cache in writethrough mode. Unless you | |
524 | specifically require this or are unsure, say N. | |
525 | ||
526 | config CPU_CACHE_ROUND_ROBIN | |
527 | bool "Round robin I and D cache replacement algorithm" | |
528 | depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) | |
529 | help | |
530 | Say Y here to use the predictable round-robin cache replacement | |
531 | policy. Unless you specifically require this or are unsure, say N. | |
532 | ||
533 | config CPU_BPREDICT_DISABLE | |
534 | bool "Disable branch prediction" | |
e03eb527 | 535 | depends on CPU_ARM1020 || CPU_V6 |
1da177e4 LT |
536 | help |
537 | Say Y here to disable branch prediction. If unsure, say N. | |
2d2669b6 | 538 | |
4b0e07a5 NP |
539 | config TLS_REG_EMUL |
540 | bool | |
4b0e07a5 | 541 | help |
70489c88 NP |
542 | An SMP system using a pre-ARMv6 processor (there are apparently |
543 | a few prototypes like that in existence) and therefore access to | |
544 | that required register must be emulated. | |
4b0e07a5 | 545 | |
2d2669b6 NP |
546 | config HAS_TLS_REG |
547 | bool | |
70489c88 NP |
548 | depends on !TLS_REG_EMUL |
549 | default y if SMP || CPU_32v7 | |
2d2669b6 NP |
550 | help |
551 | This selects support for the CP15 thread register. | |
70489c88 NP |
552 | It is defined to be available on some ARMv6 processors (including |
553 | all SMP capable ARMv6's) or later processors. User space may | |
554 | assume directly accessing that register and always obtain the | |
555 | expected value only on ARMv7 and above. | |
2d2669b6 | 556 | |
dcef1f63 NP |
557 | config NEEDS_SYSCALL_FOR_CMPXCHG |
558 | bool | |
dcef1f63 NP |
559 | help |
560 | SMP on a pre-ARMv6 processor? Well OK then. | |
561 | Forget about fast user space cmpxchg support. | |
562 | It is just not possible. | |
563 |