[deliverable/linux.git] / arch / arm / mm / abort-ev6.S

#include <linux/linkage.h>
#include <asm/assembler.h>
#include "abort-macro.S"
/*
 * Function: v6_early_abort
 *
 * Params  : r2 = pt_regs
 *	   : r4 = aborted context pc
 *	   : r5 = aborted context psr
 *
 * Returns : r4 - r11, r13 preserved
 *
 * Purpose : obtain information about current aborted instruction.
 * Note: we read user space.  This means we might cause a data
 * abort here if the I-TLB and D-TLB aren't seeing the same
 * picture.  Unfortunately, this does happen.  We live with it.
 */
	.align	5
ENTRY(v6_early_abort)
#ifdef CONFIG_CPU_V6
	sub	r1, sp, #4			@ Get unused stack location
	strex	r0, r1, [r1]			@ Clear the exclusive monitor
#elif defined(CONFIG_CPU_32v6K)
	clrex
#endif
	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
/*
 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
 * The test below covers all the write situations, including Java bytecodes
 */
	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR
	tst	r5, #PSR_J_BIT			@ Java?
	bne	do_DataAbort
	do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
	ldreq	r3, [r4]			@ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8
	reveq	r3, r3
#endif
	do_ldrd_abort tmp=ip, insn=r3
	tst	r3, #1 << 20			@ L = 0 -> write
	orreq	r1, r1, #1 << 11		@ yes.
	b	do_DataAbort
Commit	Line	Data
1da177e4 LT	1	#include <linux/linkage.h>
1da177e4 LT	2	#include <asm/assembler.h>
3a1e5015	3	#include "abort-macro.S"
1da177e4 LT	4	/*
	5	* Function: v6_early_abort
	6	*
da740472 RK	7	* Params : r2 = pt_regs
da740472 RK	8	* : r4 = aborted context pc
3e287bec	9	* : r5 = aborted context psr
1da177e4	10	*
da740472	11	* Returns : r4 - r11, r13 preserved
1da177e4 LT	12	*
1da177e4 LT	13	* Purpose : obtain information about current aborted instruction.
3a1e5015 GD	14	* Note: we read user space. This means we might cause a data
	15	* abort here if the I-TLB and D-TLB aren't seeing the same
	16	* picture. Unfortunately, this does happen. We live with it.
1da177e4 LT	17	*/
	18	.align 5
	19	ENTRY(v6_early_abort)
7db44c75	20	#ifdef CONFIG_CPU_V6
25ef4a67 SF	21	sub r1, sp, #4 @ Get unused stack location
25ef4a67 SF	22	strex r0, r1, [r1] @ Clear the exclusive monitor
7db44c75 RK	23	#elif defined(CONFIG_CPU_32v6K)
7db44c75 RK	24	clrex
2c3a0540	25	#endif
1da177e4 LT	26	mrc p15, 0, r1, c5, c0, 0 @ get FSR
1da177e4 LT	27	mrc p15, 0, r0, c6, c0, 0 @ get FAR
3a1e5015	28	/*
fe68e68f	29	* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
3a1e5015 GD	30	* The test below covers all the write situations, including Java bytecodes
3a1e5015 GD	31	*/
fe68e68f	32	bic r1, r1, #1 << 11 @ clear bit 11 of FSR
3e287bec	33	tst r5, #PSR_J_BIT @ Java?
da740472	34	bne do_DataAbort
3e287bec RK	35	do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
3e287bec RK	36	ldreq r3, [r4] @ read aborted ARM instruction
26584853 CM	37	#ifdef CONFIG_CPU_ENDIAN_BE8
	38	reveq r3, r3
	39	#endif
0d147db0	40	do_ldrd_abort tmp=ip, insn=r3
3a1e5015 GD	41	tst r3, #1 << 20 @ L = 0 -> write
3a1e5015 GD	42	orreq r1, r1, #1 << 11 @ yes.
da740472	43	b do_DataAbort