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382266ad CM |
1 | /* |
2 | * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support | |
3 | * | |
4 | * Copyright (C) 2007 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
8ef418c7 | 19 | #include <linux/cpu.h> |
8c369264 | 20 | #include <linux/err.h> |
382266ad | 21 | #include <linux/init.h> |
8ef418c7 | 22 | #include <linux/smp.h> |
07620976 | 23 | #include <linux/spinlock.h> |
f3354ab6 | 24 | #include <linux/log2.h> |
fced80c7 | 25 | #include <linux/io.h> |
8c369264 RH |
26 | #include <linux/of.h> |
27 | #include <linux/of_address.h> | |
382266ad CM |
28 | |
29 | #include <asm/cacheflush.h> | |
8ef418c7 | 30 | #include <asm/cp15.h> |
4374d649 | 31 | #include <asm/cputype.h> |
382266ad | 32 | #include <asm/hardware/cache-l2x0.h> |
e68f31f4 | 33 | #include "cache-tauros3.h" |
b8db6b88 | 34 | #include "cache-aurora-l2.h" |
382266ad | 35 | |
c02642bc | 36 | struct l2c_init_data { |
051334bd | 37 | const char *type; |
0493aef4 | 38 | unsigned way_size_0; |
3b8bad57 | 39 | unsigned num_lock; |
c02642bc | 40 | void (*of_parse)(const struct device_node *, u32 *, u32 *); |
3b8bad57 | 41 | void (*enable)(void __iomem *, u32, unsigned); |
75461f5c | 42 | void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); |
9846dfc9 | 43 | void (*save)(void __iomem *); |
6b49241a | 44 | void (*configure)(void __iomem *); |
c02642bc RK |
45 | struct outer_cache_fns outer_cache; |
46 | }; | |
47 | ||
382266ad CM |
48 | #define CACHE_LINE_SIZE 32 |
49 | ||
50 | static void __iomem *l2x0_base; | |
6b49241a | 51 | static const struct l2c_init_data *l2x0_data; |
bd31b859 | 52 | static DEFINE_RAW_SPINLOCK(l2x0_lock); |
3e175ca4 RK |
53 | static u32 l2x0_way_mask; /* Bitmask of active ways */ |
54 | static u32 l2x0_size; | |
f154fe9b | 55 | static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; |
382266ad | 56 | |
91c2ebb9 BS |
57 | struct l2x0_regs l2x0_saved_regs; |
58 | ||
37abcdb9 RK |
59 | /* |
60 | * Common code for all cache controllers. | |
61 | */ | |
83841fe1 | 62 | static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) |
382266ad | 63 | { |
9a6655e4 | 64 | /* wait for cache operation by line or way to complete */ |
6775a558 | 65 | while (readl_relaxed(reg) & mask) |
1caf3092 | 66 | cpu_relax(); |
382266ad CM |
67 | } |
68 | ||
8abd259f RK |
69 | /* |
70 | * By default, we write directly to secure registers. Platforms must | |
71 | * override this if they are running non-secure. | |
72 | */ | |
73 | static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) | |
74 | { | |
75 | if (val == readl_relaxed(base + reg)) | |
76 | return; | |
77 | if (outer_cache.write_sec) | |
78 | outer_cache.write_sec(val, reg); | |
79 | else | |
80 | writel_relaxed(val, base + reg); | |
81 | } | |
82 | ||
2b2a87a1 RK |
83 | /* |
84 | * This should only be called when we have a requirement that the | |
85 | * register be written due to a work-around, as platforms running | |
86 | * in non-secure mode may not be able to access this register. | |
87 | */ | |
88 | static inline void l2c_set_debug(void __iomem *base, unsigned long val) | |
89 | { | |
678ea28b | 90 | l2c_write_sec(val, base, L2X0_DEBUG_CTRL); |
2b2a87a1 RK |
91 | } |
92 | ||
df5dd4c6 RK |
93 | static void __l2c_op_way(void __iomem *reg) |
94 | { | |
95 | writel_relaxed(l2x0_way_mask, reg); | |
83841fe1 | 96 | l2c_wait_mask(reg, l2x0_way_mask); |
df5dd4c6 RK |
97 | } |
98 | ||
37abcdb9 RK |
99 | static inline void l2c_unlock(void __iomem *base, unsigned num) |
100 | { | |
101 | unsigned i; | |
102 | ||
103 | for (i = 0; i < num; i++) { | |
104 | writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + | |
105 | i * L2X0_LOCKDOWN_STRIDE); | |
106 | writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + | |
107 | i * L2X0_LOCKDOWN_STRIDE); | |
108 | } | |
109 | } | |
110 | ||
6b49241a TF |
111 | static void l2c_configure(void __iomem *base) |
112 | { | |
c6d1a2d0 TF |
113 | if (outer_cache.configure) { |
114 | outer_cache.configure(&l2x0_saved_regs); | |
115 | return; | |
116 | } | |
117 | ||
6b49241a TF |
118 | if (l2x0_data->configure) |
119 | l2x0_data->configure(base); | |
120 | ||
121 | l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); | |
122 | } | |
123 | ||
3b8bad57 RK |
124 | /* |
125 | * Enable the L2 cache controller. This function must only be | |
126 | * called when the cache controller is known to be disabled. | |
127 | */ | |
128 | static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
6b49241a TF |
132 | /* Do not touch the controller if already enabled. */ |
133 | if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN) | |
134 | return; | |
135 | ||
136 | l2x0_saved_regs.aux_ctrl = aux; | |
137 | l2c_configure(base); | |
3b8bad57 | 138 | |
17f3f99f RK |
139 | l2c_unlock(base, num_lock); |
140 | ||
3b8bad57 RK |
141 | local_irq_save(flags); |
142 | __l2c_op_way(base + L2X0_INV_WAY); | |
143 | writel_relaxed(0, base + sync_reg_offset); | |
144 | l2c_wait_mask(base + sync_reg_offset, 1); | |
145 | local_irq_restore(flags); | |
146 | ||
8abd259f | 147 | l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL); |
3b8bad57 RK |
148 | } |
149 | ||
150 | static void l2c_disable(void) | |
151 | { | |
152 | void __iomem *base = l2x0_base; | |
153 | ||
154 | outer_cache.flush_all(); | |
8abd259f | 155 | l2c_write_sec(0, base, L2X0_CTRL); |
3b8bad57 RK |
156 | dsb(st); |
157 | } | |
158 | ||
9a6655e4 CM |
159 | #ifdef CONFIG_CACHE_PL310 |
160 | static inline void cache_wait(void __iomem *reg, unsigned long mask) | |
161 | { | |
162 | /* cache operations by line are atomic on PL310 */ | |
163 | } | |
164 | #else | |
83841fe1 | 165 | #define cache_wait l2c_wait_mask |
9a6655e4 CM |
166 | #endif |
167 | ||
382266ad CM |
168 | static inline void cache_sync(void) |
169 | { | |
3d107434 | 170 | void __iomem *base = l2x0_base; |
885028e4 | 171 | |
f154fe9b | 172 | writel_relaxed(0, base + sync_reg_offset); |
3d107434 | 173 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
382266ad CM |
174 | } |
175 | ||
2839e06c | 176 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) |
ab4d5368 WD |
177 | static inline void debug_writel(unsigned long val) |
178 | { | |
678ea28b | 179 | l2c_set_debug(l2x0_base, val); |
ab4d5368 | 180 | } |
2839e06c SS |
181 | #else |
182 | /* Optimised out for non-errata case */ | |
183 | static inline void debug_writel(unsigned long val) | |
184 | { | |
185 | } | |
2839e06c | 186 | #endif |
9e65582a | 187 | |
23107c54 CM |
188 | static void l2x0_cache_sync(void) |
189 | { | |
190 | unsigned long flags; | |
191 | ||
bd31b859 | 192 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
23107c54 | 193 | cache_sync(); |
bd31b859 | 194 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
23107c54 CM |
195 | } |
196 | ||
38a8914f | 197 | static void __l2x0_flush_all(void) |
2fd86589 | 198 | { |
2839e06c | 199 | debug_writel(0x03); |
df5dd4c6 | 200 | __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY); |
2fd86589 | 201 | cache_sync(); |
2839e06c | 202 | debug_writel(0x00); |
38a8914f WD |
203 | } |
204 | ||
205 | static void l2x0_flush_all(void) | |
206 | { | |
207 | unsigned long flags; | |
208 | ||
209 | /* clean all ways */ | |
bd31b859 | 210 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
38a8914f | 211 | __l2x0_flush_all(); |
bd31b859 | 212 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
2fd86589 TG |
213 | } |
214 | ||
2fd86589 TG |
215 | static void l2x0_disable(void) |
216 | { | |
217 | unsigned long flags; | |
218 | ||
bd31b859 | 219 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
38a8914f | 220 | __l2x0_flush_all(); |
8abd259f | 221 | l2c_write_sec(0, l2x0_base, L2X0_CTRL); |
9781aa8a | 222 | dsb(st); |
bd31b859 | 223 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
2fd86589 TG |
224 | } |
225 | ||
ddf7d79b RK |
226 | static void l2c_save(void __iomem *base) |
227 | { | |
228 | l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); | |
229 | } | |
230 | ||
6b49241a TF |
231 | static void l2c_resume(void) |
232 | { | |
233 | l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock); | |
234 | } | |
235 | ||
6a28cf59 RK |
236 | /* |
237 | * L2C-210 specific code. | |
238 | * | |
239 | * The L2C-2x0 PA, set/way and sync operations are atomic, but we must | |
240 | * ensure that no background operation is running. The way operations | |
241 | * are all background tasks. | |
242 | * | |
243 | * While a background operation is in progress, any new operation is | |
244 | * ignored (unspecified whether this causes an error.) Thankfully, not | |
245 | * used on SMP. | |
246 | * | |
247 | * Never has a different sync register other than L2X0_CACHE_SYNC, but | |
248 | * we use sync_reg_offset here so we can share some of this with L2C-310. | |
249 | */ | |
250 | static void __l2c210_cache_sync(void __iomem *base) | |
251 | { | |
252 | writel_relaxed(0, base + sync_reg_offset); | |
253 | } | |
254 | ||
255 | static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, | |
256 | unsigned long end) | |
257 | { | |
258 | while (start < end) { | |
259 | writel_relaxed(start, reg); | |
260 | start += CACHE_LINE_SIZE; | |
261 | } | |
262 | } | |
263 | ||
264 | static void l2c210_inv_range(unsigned long start, unsigned long end) | |
265 | { | |
266 | void __iomem *base = l2x0_base; | |
267 | ||
268 | if (start & (CACHE_LINE_SIZE - 1)) { | |
269 | start &= ~(CACHE_LINE_SIZE - 1); | |
270 | writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); | |
271 | start += CACHE_LINE_SIZE; | |
272 | } | |
273 | ||
274 | if (end & (CACHE_LINE_SIZE - 1)) { | |
275 | end &= ~(CACHE_LINE_SIZE - 1); | |
276 | writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); | |
277 | } | |
278 | ||
279 | __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); | |
280 | __l2c210_cache_sync(base); | |
281 | } | |
282 | ||
283 | static void l2c210_clean_range(unsigned long start, unsigned long end) | |
284 | { | |
285 | void __iomem *base = l2x0_base; | |
286 | ||
287 | start &= ~(CACHE_LINE_SIZE - 1); | |
288 | __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); | |
289 | __l2c210_cache_sync(base); | |
290 | } | |
291 | ||
292 | static void l2c210_flush_range(unsigned long start, unsigned long end) | |
293 | { | |
294 | void __iomem *base = l2x0_base; | |
295 | ||
296 | start &= ~(CACHE_LINE_SIZE - 1); | |
297 | __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); | |
298 | __l2c210_cache_sync(base); | |
299 | } | |
300 | ||
301 | static void l2c210_flush_all(void) | |
302 | { | |
303 | void __iomem *base = l2x0_base; | |
304 | ||
305 | BUG_ON(!irqs_disabled()); | |
306 | ||
307 | __l2c_op_way(base + L2X0_CLEAN_INV_WAY); | |
308 | __l2c210_cache_sync(base); | |
309 | } | |
310 | ||
311 | static void l2c210_sync(void) | |
312 | { | |
313 | __l2c210_cache_sync(l2x0_base); | |
314 | } | |
315 | ||
6a28cf59 | 316 | static const struct l2c_init_data l2c210_data __initconst = { |
051334bd | 317 | .type = "L2C-210", |
0493aef4 | 318 | .way_size_0 = SZ_8K, |
6a28cf59 RK |
319 | .num_lock = 1, |
320 | .enable = l2c_enable, | |
ddf7d79b | 321 | .save = l2c_save, |
6a28cf59 RK |
322 | .outer_cache = { |
323 | .inv_range = l2c210_inv_range, | |
324 | .clean_range = l2c210_clean_range, | |
325 | .flush_range = l2c210_flush_range, | |
326 | .flush_all = l2c210_flush_all, | |
327 | .disable = l2c_disable, | |
328 | .sync = l2c210_sync, | |
6b49241a | 329 | .resume = l2c_resume, |
6a28cf59 RK |
330 | }, |
331 | }; | |
332 | ||
733c6bba RK |
333 | /* |
334 | * L2C-220 specific code. | |
335 | * | |
336 | * All operations are background operations: they have to be waited for. | |
337 | * Conflicting requests generate a slave error (which will cause an | |
338 | * imprecise abort.) Never uses sync_reg_offset, so we hard-code the | |
339 | * sync register here. | |
340 | * | |
341 | * However, we can re-use the l2c210_resume call. | |
342 | */ | |
343 | static inline void __l2c220_cache_sync(void __iomem *base) | |
344 | { | |
345 | writel_relaxed(0, base + L2X0_CACHE_SYNC); | |
346 | l2c_wait_mask(base + L2X0_CACHE_SYNC, 1); | |
347 | } | |
348 | ||
349 | static void l2c220_op_way(void __iomem *base, unsigned reg) | |
350 | { | |
351 | unsigned long flags; | |
352 | ||
353 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
354 | __l2c_op_way(base + reg); | |
355 | __l2c220_cache_sync(base); | |
356 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
357 | } | |
358 | ||
359 | static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, | |
360 | unsigned long end, unsigned long flags) | |
361 | { | |
362 | raw_spinlock_t *lock = &l2x0_lock; | |
363 | ||
364 | while (start < end) { | |
365 | unsigned long blk_end = start + min(end - start, 4096UL); | |
366 | ||
367 | while (start < blk_end) { | |
368 | l2c_wait_mask(reg, 1); | |
369 | writel_relaxed(start, reg); | |
370 | start += CACHE_LINE_SIZE; | |
371 | } | |
372 | ||
373 | if (blk_end < end) { | |
374 | raw_spin_unlock_irqrestore(lock, flags); | |
375 | raw_spin_lock_irqsave(lock, flags); | |
376 | } | |
377 | } | |
378 | ||
379 | return flags; | |
380 | } | |
381 | ||
382 | static void l2c220_inv_range(unsigned long start, unsigned long end) | |
383 | { | |
384 | void __iomem *base = l2x0_base; | |
385 | unsigned long flags; | |
386 | ||
387 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
388 | if ((start | end) & (CACHE_LINE_SIZE - 1)) { | |
389 | if (start & (CACHE_LINE_SIZE - 1)) { | |
390 | start &= ~(CACHE_LINE_SIZE - 1); | |
391 | writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); | |
392 | start += CACHE_LINE_SIZE; | |
393 | } | |
394 | ||
395 | if (end & (CACHE_LINE_SIZE - 1)) { | |
396 | end &= ~(CACHE_LINE_SIZE - 1); | |
397 | l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
398 | writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); | |
399 | } | |
400 | } | |
401 | ||
402 | flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA, | |
403 | start, end, flags); | |
404 | l2c_wait_mask(base + L2X0_INV_LINE_PA, 1); | |
405 | __l2c220_cache_sync(base); | |
406 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
407 | } | |
408 | ||
409 | static void l2c220_clean_range(unsigned long start, unsigned long end) | |
410 | { | |
411 | void __iomem *base = l2x0_base; | |
412 | unsigned long flags; | |
413 | ||
414 | start &= ~(CACHE_LINE_SIZE - 1); | |
415 | if ((end - start) >= l2x0_size) { | |
416 | l2c220_op_way(base, L2X0_CLEAN_WAY); | |
417 | return; | |
418 | } | |
419 | ||
420 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
421 | flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA, | |
422 | start, end, flags); | |
423 | l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
424 | __l2c220_cache_sync(base); | |
425 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
426 | } | |
427 | ||
428 | static void l2c220_flush_range(unsigned long start, unsigned long end) | |
429 | { | |
430 | void __iomem *base = l2x0_base; | |
431 | unsigned long flags; | |
432 | ||
433 | start &= ~(CACHE_LINE_SIZE - 1); | |
434 | if ((end - start) >= l2x0_size) { | |
435 | l2c220_op_way(base, L2X0_CLEAN_INV_WAY); | |
436 | return; | |
437 | } | |
438 | ||
439 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
440 | flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, | |
441 | start, end, flags); | |
442 | l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
443 | __l2c220_cache_sync(base); | |
444 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
445 | } | |
446 | ||
447 | static void l2c220_flush_all(void) | |
448 | { | |
449 | l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY); | |
450 | } | |
451 | ||
452 | static void l2c220_sync(void) | |
453 | { | |
454 | unsigned long flags; | |
455 | ||
456 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
457 | __l2c220_cache_sync(l2x0_base); | |
458 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
459 | } | |
460 | ||
a4b041a0 RK |
461 | static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) |
462 | { | |
463 | /* | |
464 | * Always enable non-secure access to the lockdown registers - | |
465 | * we write to them as part of the L2C enable sequence so they | |
466 | * need to be accessible. | |
467 | */ | |
468 | aux |= L220_AUX_CTRL_NS_LOCKDOWN; | |
469 | ||
470 | l2c_enable(base, aux, num_lock); | |
471 | } | |
472 | ||
733c6bba | 473 | static const struct l2c_init_data l2c220_data = { |
051334bd | 474 | .type = "L2C-220", |
0493aef4 | 475 | .way_size_0 = SZ_8K, |
733c6bba | 476 | .num_lock = 1, |
a4b041a0 | 477 | .enable = l2c220_enable, |
ddf7d79b | 478 | .save = l2c_save, |
733c6bba RK |
479 | .outer_cache = { |
480 | .inv_range = l2c220_inv_range, | |
481 | .clean_range = l2c220_clean_range, | |
482 | .flush_range = l2c220_flush_range, | |
483 | .flush_all = l2c220_flush_all, | |
484 | .disable = l2c_disable, | |
485 | .sync = l2c220_sync, | |
6b49241a | 486 | .resume = l2c_resume, |
733c6bba RK |
487 | }, |
488 | }; | |
489 | ||
75461f5c RK |
490 | /* |
491 | * L2C-310 specific code. | |
492 | * | |
f777332b RK |
493 | * Very similar to L2C-210, the PA, set/way and sync operations are atomic, |
494 | * and the way operations are all background tasks. However, issuing an | |
495 | * operation while a background operation is in progress results in a | |
496 | * SLVERR response. We can reuse: | |
497 | * | |
498 | * __l2c210_cache_sync (using sync_reg_offset) | |
499 | * l2c210_sync | |
500 | * l2c210_inv_range (if 588369 is not applicable) | |
501 | * l2c210_clean_range | |
502 | * l2c210_flush_range (if 588369 is not applicable) | |
503 | * l2c210_flush_all (if 727915 is not applicable) | |
504 | * | |
75461f5c RK |
505 | * Errata: |
506 | * 588369: PL310 R0P0->R1P0, fixed R2P0. | |
507 | * Affects: all clean+invalidate operations | |
508 | * clean and invalidate skips the invalidate step, so we need to issue | |
509 | * separate operations. We also require the above debug workaround | |
510 | * enclosing this code fragment on affected parts. On unaffected parts, | |
511 | * we must not use this workaround without the debug register writes | |
512 | * to avoid exposing a problem similar to 727915. | |
513 | * | |
514 | * 727915: PL310 R2P0->R3P0, fixed R3P1. | |
515 | * Affects: clean+invalidate by way | |
516 | * clean and invalidate by way runs in the background, and a store can | |
517 | * hit the line between the clean operation and invalidate operation, | |
518 | * resulting in the store being lost. | |
519 | * | |
a8875a09 RK |
520 | * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2. |
521 | * Affects: 8x64-bit (double fill) line fetches | |
522 | * double fill line fetches can fail to cause dirty data to be evicted | |
523 | * from the cache before the new data overwrites the second line. | |
524 | * | |
75461f5c RK |
525 | * 753970: PL310 R3P0, fixed R3P1. |
526 | * Affects: sync | |
527 | * prevents merging writes after the sync operation, until another L2C | |
528 | * operation is performed (or a number of other conditions.) | |
529 | * | |
530 | * 769419: PL310 R0P0->R3P1, fixed R3P2. | |
531 | * Affects: store buffer | |
532 | * store buffer is not automatically drained. | |
533 | */ | |
ebd4219f RK |
534 | static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) |
535 | { | |
536 | void __iomem *base = l2x0_base; | |
537 | ||
538 | if ((start | end) & (CACHE_LINE_SIZE - 1)) { | |
539 | unsigned long flags; | |
540 | ||
541 | /* Erratum 588369 for both clean+invalidate operations */ | |
542 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
543 | l2c_set_debug(base, 0x03); | |
544 | ||
545 | if (start & (CACHE_LINE_SIZE - 1)) { | |
546 | start &= ~(CACHE_LINE_SIZE - 1); | |
547 | writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); | |
548 | writel_relaxed(start, base + L2X0_INV_LINE_PA); | |
549 | start += CACHE_LINE_SIZE; | |
550 | } | |
551 | ||
552 | if (end & (CACHE_LINE_SIZE - 1)) { | |
553 | end &= ~(CACHE_LINE_SIZE - 1); | |
554 | writel_relaxed(end, base + L2X0_CLEAN_LINE_PA); | |
555 | writel_relaxed(end, base + L2X0_INV_LINE_PA); | |
556 | } | |
557 | ||
558 | l2c_set_debug(base, 0x00); | |
559 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
560 | } | |
561 | ||
562 | __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); | |
563 | __l2c210_cache_sync(base); | |
564 | } | |
565 | ||
566 | static void l2c310_flush_range_erratum(unsigned long start, unsigned long end) | |
567 | { | |
568 | raw_spinlock_t *lock = &l2x0_lock; | |
569 | unsigned long flags; | |
570 | void __iomem *base = l2x0_base; | |
571 | ||
572 | raw_spin_lock_irqsave(lock, flags); | |
573 | while (start < end) { | |
574 | unsigned long blk_end = start + min(end - start, 4096UL); | |
575 | ||
576 | l2c_set_debug(base, 0x03); | |
577 | while (start < blk_end) { | |
578 | writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); | |
579 | writel_relaxed(start, base + L2X0_INV_LINE_PA); | |
580 | start += CACHE_LINE_SIZE; | |
581 | } | |
582 | l2c_set_debug(base, 0x00); | |
583 | ||
584 | if (blk_end < end) { | |
585 | raw_spin_unlock_irqrestore(lock, flags); | |
586 | raw_spin_lock_irqsave(lock, flags); | |
587 | } | |
588 | } | |
589 | raw_spin_unlock_irqrestore(lock, flags); | |
590 | __l2c210_cache_sync(base); | |
591 | } | |
592 | ||
99ca1772 RK |
593 | static void l2c310_flush_all_erratum(void) |
594 | { | |
595 | void __iomem *base = l2x0_base; | |
596 | unsigned long flags; | |
597 | ||
598 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
599 | l2c_set_debug(base, 0x03); | |
600 | __l2c_op_way(base + L2X0_CLEAN_INV_WAY); | |
601 | l2c_set_debug(base, 0x00); | |
602 | __l2c210_cache_sync(base); | |
603 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
604 | } | |
605 | ||
09a5d180 | 606 | static void __init l2c310_save(void __iomem *base) |
b98556f2 | 607 | { |
09a5d180 | 608 | unsigned revision; |
b98556f2 | 609 | |
ddf7d79b RK |
610 | l2c_save(base); |
611 | ||
b98556f2 | 612 | l2x0_saved_regs.tag_latency = readl_relaxed(base + |
1a5a954c | 613 | L310_TAG_LATENCY_CTRL); |
b98556f2 | 614 | l2x0_saved_regs.data_latency = readl_relaxed(base + |
1a5a954c | 615 | L310_DATA_LATENCY_CTRL); |
b98556f2 | 616 | l2x0_saved_regs.filter_end = readl_relaxed(base + |
1a5a954c | 617 | L310_ADDR_FILTER_END); |
b98556f2 | 618 | l2x0_saved_regs.filter_start = readl_relaxed(base + |
1a5a954c | 619 | L310_ADDR_FILTER_START); |
b98556f2 | 620 | |
09a5d180 RK |
621 | revision = readl_relaxed(base + L2X0_CACHE_ID) & |
622 | L2X0_CACHE_ID_RTL_MASK; | |
623 | ||
624 | /* From r2p0, there is Prefetch offset/control register */ | |
625 | if (revision >= L310_CACHE_ID_RTL_R2P0) | |
b98556f2 | 626 | l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + |
1a5a954c | 627 | L310_PREFETCH_CTRL); |
09a5d180 RK |
628 | |
629 | /* From r3p0, there is Power control register */ | |
630 | if (revision >= L310_CACHE_ID_RTL_R3P0) | |
631 | l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + | |
1a5a954c | 632 | L310_POWER_CTRL); |
b98556f2 RK |
633 | } |
634 | ||
6b49241a | 635 | static void l2c310_configure(void __iomem *base) |
b98556f2 | 636 | { |
6b49241a | 637 | unsigned revision; |
09a5d180 | 638 | |
6b49241a TF |
639 | /* restore pl310 setup */ |
640 | l2c_write_sec(l2x0_saved_regs.tag_latency, base, | |
641 | L310_TAG_LATENCY_CTRL); | |
642 | l2c_write_sec(l2x0_saved_regs.data_latency, base, | |
643 | L310_DATA_LATENCY_CTRL); | |
644 | l2c_write_sec(l2x0_saved_regs.filter_end, base, | |
645 | L310_ADDR_FILTER_END); | |
646 | l2c_write_sec(l2x0_saved_regs.filter_start, base, | |
647 | L310_ADDR_FILTER_START); | |
648 | ||
649 | revision = readl_relaxed(base + L2X0_CACHE_ID) & | |
650 | L2X0_CACHE_ID_RTL_MASK; | |
651 | ||
652 | if (revision >= L310_CACHE_ID_RTL_R2P0) | |
653 | l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, | |
654 | L310_PREFETCH_CTRL); | |
655 | if (revision >= L310_CACHE_ID_RTL_R3P0) | |
656 | l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base, | |
657 | L310_POWER_CTRL); | |
8ef418c7 RK |
658 | } |
659 | ||
660 | static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data) | |
661 | { | |
662 | switch (act & ~CPU_TASKS_FROZEN) { | |
663 | case CPU_STARTING: | |
664 | set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); | |
665 | break; | |
666 | case CPU_DYING: | |
667 | set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); | |
668 | break; | |
09a5d180 | 669 | } |
8ef418c7 | 670 | return NOTIFY_OK; |
b98556f2 RK |
671 | } |
672 | ||
4374d649 RK |
673 | static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) |
674 | { | |
9a2c33a4 | 675 | unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; |
af040ffc | 676 | bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9; |
4374d649 RK |
677 | |
678 | if (rev >= L310_CACHE_ID_RTL_R2P0) { | |
679 | if (cortex_a9) { | |
680 | aux |= L310_AUX_CTRL_EARLY_BRESP; | |
681 | pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); | |
682 | } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { | |
683 | pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n"); | |
684 | aux &= ~L310_AUX_CTRL_EARLY_BRESP; | |
685 | } | |
686 | } | |
687 | ||
8ef418c7 RK |
688 | if (cortex_a9) { |
689 | u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); | |
690 | u32 acr = get_auxcr(); | |
691 | ||
692 | pr_debug("Cortex-A9 ACR=0x%08x\n", acr); | |
693 | ||
694 | if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO)) | |
695 | pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n"); | |
696 | ||
697 | if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3))) | |
698 | pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n"); | |
699 | ||
700 | if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) { | |
701 | aux |= L310_AUX_CTRL_FULL_LINE_ZERO; | |
702 | pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n"); | |
703 | } | |
704 | } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) { | |
705 | pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n"); | |
706 | aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP); | |
707 | } | |
708 | ||
6b49241a TF |
709 | /* r3p0 or later has power control register */ |
710 | if (rev >= L310_CACHE_ID_RTL_R3P0) | |
711 | l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN | | |
712 | L310_STNDBY_MODE_EN; | |
713 | ||
714 | /* | |
715 | * Always enable non-secure access to the lockdown registers - | |
716 | * we write to them as part of the L2C enable sequence so they | |
717 | * need to be accessible. | |
718 | */ | |
719 | aux |= L310_AUX_CTRL_NS_LOCKDOWN; | |
720 | ||
721 | l2c_enable(base, aux, num_lock); | |
722 | ||
723 | /* Read back resulting AUX_CTRL value as it could have been altered. */ | |
724 | aux = readl_relaxed(base + L2X0_AUX_CTRL); | |
725 | ||
8ef418c7 RK |
726 | if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) { |
727 | u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL); | |
728 | ||
729 | pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n", | |
730 | aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "", | |
731 | aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "", | |
732 | 1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK)); | |
733 | } | |
734 | ||
3a43b581 RK |
735 | /* r3p0 or later has power control register */ |
736 | if (rev >= L310_CACHE_ID_RTL_R3P0) { | |
737 | u32 power_ctrl; | |
738 | ||
3a43b581 RK |
739 | power_ctrl = readl_relaxed(base + L310_POWER_CTRL); |
740 | pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n", | |
741 | power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis", | |
742 | power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); | |
743 | } | |
744 | ||
8ef418c7 RK |
745 | if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { |
746 | set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); | |
747 | cpu_notifier(l2c310_cpu_enable_flz, 0); | |
748 | } | |
4374d649 RK |
749 | } |
750 | ||
75461f5c RK |
751 | static void __init l2c310_fixup(void __iomem *base, u32 cache_id, |
752 | struct outer_cache_fns *fns) | |
753 | { | |
754 | unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; | |
a8875a09 | 755 | const char *errata[8]; |
75461f5c RK |
756 | unsigned n = 0; |
757 | ||
ebd4219f RK |
758 | if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) && |
759 | revision < L310_CACHE_ID_RTL_R2P0 && | |
760 | /* For bcm compatibility */ | |
f777332b | 761 | fns->inv_range == l2c210_inv_range) { |
ebd4219f RK |
762 | fns->inv_range = l2c310_inv_range_erratum; |
763 | fns->flush_range = l2c310_flush_range_erratum; | |
764 | errata[n++] = "588369"; | |
765 | } | |
766 | ||
99ca1772 RK |
767 | if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) && |
768 | revision >= L310_CACHE_ID_RTL_R2P0 && | |
769 | revision < L310_CACHE_ID_RTL_R3P1) { | |
770 | fns->flush_all = l2c310_flush_all_erratum; | |
771 | errata[n++] = "727915"; | |
772 | } | |
773 | ||
a8875a09 RK |
774 | if (revision >= L310_CACHE_ID_RTL_R3P0 && |
775 | revision < L310_CACHE_ID_RTL_R3P2) { | |
6b49241a | 776 | u32 val = l2x0_saved_regs.prefetch_ctrl; |
a8875a09 RK |
777 | /* I don't think bit23 is required here... but iMX6 does so */ |
778 | if (val & (BIT(30) | BIT(23))) { | |
779 | val &= ~(BIT(30) | BIT(23)); | |
6b49241a | 780 | l2x0_saved_regs.prefetch_ctrl = val; |
a8875a09 RK |
781 | errata[n++] = "752271"; |
782 | } | |
783 | } | |
784 | ||
75461f5c RK |
785 | if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && |
786 | revision == L310_CACHE_ID_RTL_R3P0) { | |
787 | sync_reg_offset = L2X0_DUMMY_REG; | |
788 | errata[n++] = "753970"; | |
789 | } | |
790 | ||
791 | if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) | |
792 | errata[n++] = "769419"; | |
793 | ||
794 | if (n) { | |
795 | unsigned i; | |
796 | ||
797 | pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); | |
798 | for (i = 0; i < n; i++) | |
799 | pr_cont(" %s", errata[i]); | |
800 | pr_cont(" enabled\n"); | |
801 | } | |
802 | } | |
803 | ||
8ef418c7 RK |
804 | static void l2c310_disable(void) |
805 | { | |
806 | /* | |
807 | * If full-line-of-zeros is enabled, we must first disable it in the | |
808 | * Cortex-A9 auxiliary control register before disabling the L2 cache. | |
809 | */ | |
810 | if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) | |
811 | set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); | |
812 | ||
813 | l2c_disable(); | |
814 | } | |
815 | ||
6b49241a TF |
816 | static void l2c310_resume(void) |
817 | { | |
818 | l2c_resume(); | |
819 | ||
820 | /* Re-enable full-line-of-zeros for Cortex-A9 */ | |
821 | if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) | |
822 | set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); | |
823 | } | |
824 | ||
75461f5c | 825 | static const struct l2c_init_data l2c310_init_fns __initconst = { |
051334bd | 826 | .type = "L2C-310", |
0493aef4 | 827 | .way_size_0 = SZ_8K, |
75461f5c | 828 | .num_lock = 8, |
4374d649 | 829 | .enable = l2c310_enable, |
75461f5c | 830 | .fixup = l2c310_fixup, |
09a5d180 | 831 | .save = l2c310_save, |
6b49241a | 832 | .configure = l2c310_configure, |
75461f5c | 833 | .outer_cache = { |
f777332b RK |
834 | .inv_range = l2c210_inv_range, |
835 | .clean_range = l2c210_clean_range, | |
836 | .flush_range = l2c210_flush_range, | |
837 | .flush_all = l2c210_flush_all, | |
8ef418c7 | 838 | .disable = l2c310_disable, |
f777332b | 839 | .sync = l2c210_sync, |
09a5d180 | 840 | .resume = l2c310_resume, |
75461f5c RK |
841 | }, |
842 | }; | |
843 | ||
6b49241a TF |
844 | static int __init __l2c_init(const struct l2c_init_data *data, |
845 | u32 aux_val, u32 aux_mask, u32 cache_id) | |
382266ad | 846 | { |
75461f5c | 847 | struct outer_cache_fns fns; |
0493aef4 | 848 | unsigned way_size_bits, ways; |
560be613 | 849 | u32 aux, old_aux; |
382266ad | 850 | |
6b49241a TF |
851 | /* |
852 | * Save the pointer globally so that callbacks which do not receive | |
853 | * context from callers can access the structure. | |
854 | */ | |
855 | l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL); | |
856 | if (!l2x0_data) | |
857 | return -ENOMEM; | |
858 | ||
560be613 RK |
859 | /* |
860 | * Sanity check the aux values. aux_mask is the bits we preserve | |
861 | * from reading the hardware register, and aux_val is the bits we | |
862 | * set. | |
863 | */ | |
864 | if (aux_val & aux_mask) | |
865 | pr_alert("L2C: platform provided aux values permit register corruption.\n"); | |
64039be8 | 866 | |
560be613 | 867 | old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
4082cfa7 SH |
868 | aux &= aux_mask; |
869 | aux |= aux_val; | |
870 | ||
560be613 RK |
871 | if (old_aux != aux) |
872 | pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n", | |
873 | old_aux, aux); | |
874 | ||
64039be8 | 875 | /* Determine the number of ways */ |
6e7aceeb | 876 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
64039be8 | 877 | case L2X0_CACHE_ID_PART_L310: |
314e47b7 RK |
878 | if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16)) |
879 | pr_warn("L2C: DT/platform tries to modify or specify cache size\n"); | |
64039be8 JM |
880 | if (aux & (1 << 16)) |
881 | ways = 16; | |
882 | else | |
883 | ways = 8; | |
64039be8 | 884 | break; |
75461f5c | 885 | |
64039be8 | 886 | case L2X0_CACHE_ID_PART_L210: |
5f47c387 | 887 | case L2X0_CACHE_ID_PART_L220: |
64039be8 | 888 | ways = (aux >> 13) & 0xf; |
64039be8 | 889 | break; |
b8db6b88 GC |
890 | |
891 | case AURORA_CACHE_ID: | |
b8db6b88 GC |
892 | ways = (aux >> 13) & 0xf; |
893 | ways = 2 << ((ways + 1) >> 2); | |
b8db6b88 | 894 | break; |
75461f5c | 895 | |
64039be8 JM |
896 | default: |
897 | /* Assume unknown chips have 8 ways */ | |
898 | ways = 8; | |
64039be8 JM |
899 | break; |
900 | } | |
901 | ||
902 | l2x0_way_mask = (1 << ways) - 1; | |
903 | ||
5ba70372 | 904 | /* |
0493aef4 RK |
905 | * way_size_0 is the size that a way_size value of zero would be |
906 | * given the calculation: way_size = way_size_0 << way_size_bits. | |
907 | * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k, | |
908 | * then way_size_0 would be 8k. | |
909 | * | |
910 | * L2 cache size = number of ways * way size. | |
5ba70372 | 911 | */ |
1a5a954c RK |
912 | way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >> |
913 | L2C_AUX_CTRL_WAY_SIZE_SHIFT; | |
0493aef4 | 914 | l2x0_size = ways * (data->way_size_0 << way_size_bits); |
5ba70372 | 915 | |
75461f5c | 916 | fns = data->outer_cache; |
8abd259f | 917 | fns.write_sec = outer_cache.write_sec; |
c6d1a2d0 | 918 | fns.configure = outer_cache.configure; |
75461f5c RK |
919 | if (data->fixup) |
920 | data->fixup(l2x0_base, cache_id, &fns); | |
921 | ||
48371cd3 | 922 | /* |
3b8bad57 RK |
923 | * Check if l2x0 controller is already enabled. If we are booting |
924 | * in non-secure mode accessing the below registers will fault. | |
48371cd3 | 925 | */ |
3b8bad57 RK |
926 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) |
927 | data->enable(l2x0_base, aux, data->num_lock); | |
382266ad | 928 | |
ddf7d79b | 929 | outer_cache = fns; |
9d4876f0 | 930 | |
ddf7d79b RK |
931 | /* |
932 | * It is strange to save the register state before initialisation, | |
933 | * but hey, this is what the DT implementations decided to do. | |
934 | */ | |
935 | if (data->save) | |
936 | data->save(l2x0_base); | |
9d4876f0 | 937 | |
ddf7d79b RK |
938 | /* Re-read it in case some bits are reserved. */ |
939 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); | |
382266ad | 940 | |
cdef8689 | 941 | pr_info("%s cache controller enabled, %d ways, %d kB\n", |
051334bd | 942 | data->type, ways, l2x0_size >> 10); |
cdef8689 | 943 | pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", |
051334bd | 944 | data->type, cache_id, aux); |
6b49241a TF |
945 | |
946 | return 0; | |
382266ad | 947 | } |
8c369264 | 948 | |
96054b0a RK |
949 | void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) |
950 | { | |
75461f5c | 951 | const struct l2c_init_data *data; |
96054b0a RK |
952 | u32 cache_id; |
953 | ||
954 | l2x0_base = base; | |
955 | ||
956 | cache_id = readl_relaxed(base + L2X0_CACHE_ID); | |
957 | ||
75461f5c RK |
958 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
959 | default: | |
6a28cf59 RK |
960 | case L2X0_CACHE_ID_PART_L210: |
961 | data = &l2c210_data; | |
962 | break; | |
963 | ||
733c6bba RK |
964 | case L2X0_CACHE_ID_PART_L220: |
965 | data = &l2c220_data; | |
966 | break; | |
967 | ||
75461f5c RK |
968 | case L2X0_CACHE_ID_PART_L310: |
969 | data = &l2c310_init_fns; | |
970 | break; | |
971 | } | |
972 | ||
6b49241a TF |
973 | /* Read back current (default) hardware configuration */ |
974 | if (data->save) | |
975 | data->save(l2x0_base); | |
976 | ||
75461f5c | 977 | __l2c_init(data, aux_val, aux_mask, cache_id); |
96054b0a RK |
978 | } |
979 | ||
8c369264 | 980 | #ifdef CONFIG_OF |
b8db6b88 GC |
981 | static int l2_wt_override; |
982 | ||
96054b0a RK |
983 | /* Aurora don't have the cache ID register available, so we have to |
984 | * pass it though the device tree */ | |
985 | static u32 cache_id_part_number_from_dt; | |
986 | ||
f3354ab6 LW |
987 | /** |
988 | * l2x0_cache_size_of_parse() - read cache size parameters from DT | |
989 | * @np: the device tree node for the l2 cache | |
990 | * @aux_val: pointer to machine-supplied auxilary register value, to | |
991 | * be augmented by the call (bits to be set to 1) | |
992 | * @aux_mask: pointer to machine-supplied auxilary register mask, to | |
993 | * be augmented by the call (bits to be set to 0) | |
994 | * @associativity: variable to return the calculated associativity in | |
995 | * @max_way_size: the maximum size in bytes for the cache ways | |
996 | */ | |
d0b92845 | 997 | static int __init l2x0_cache_size_of_parse(const struct device_node *np, |
f3354ab6 LW |
998 | u32 *aux_val, u32 *aux_mask, |
999 | u32 *associativity, | |
1000 | u32 max_way_size) | |
1001 | { | |
1002 | u32 mask = 0, val = 0; | |
1003 | u32 cache_size = 0, sets = 0; | |
1004 | u32 way_size_bits = 1; | |
1005 | u32 way_size = 0; | |
1006 | u32 block_size = 0; | |
1007 | u32 line_size = 0; | |
1008 | ||
1009 | of_property_read_u32(np, "cache-size", &cache_size); | |
1010 | of_property_read_u32(np, "cache-sets", &sets); | |
1011 | of_property_read_u32(np, "cache-block-size", &block_size); | |
1012 | of_property_read_u32(np, "cache-line-size", &line_size); | |
1013 | ||
1014 | if (!cache_size || !sets) | |
d0b92845 | 1015 | return -ENODEV; |
f3354ab6 LW |
1016 | |
1017 | /* All these l2 caches have the same line = block size actually */ | |
1018 | if (!line_size) { | |
1019 | if (block_size) { | |
1020 | /* If linesize if not given, it is equal to blocksize */ | |
1021 | line_size = block_size; | |
1022 | } else { | |
1023 | /* Fall back to known size */ | |
1024 | pr_warn("L2C OF: no cache block/line size given: " | |
1025 | "falling back to default size %d bytes\n", | |
1026 | CACHE_LINE_SIZE); | |
1027 | line_size = CACHE_LINE_SIZE; | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | if (line_size != CACHE_LINE_SIZE) | |
1032 | pr_warn("L2C OF: DT supplied line size %d bytes does " | |
1033 | "not match hardware line size of %d bytes\n", | |
1034 | line_size, | |
1035 | CACHE_LINE_SIZE); | |
1036 | ||
1037 | /* | |
1038 | * Since: | |
1039 | * set size = cache size / sets | |
1040 | * ways = cache size / (sets * line size) | |
1041 | * way size = cache size / (cache size / (sets * line size)) | |
1042 | * way size = sets * line size | |
1043 | * associativity = ways = cache size / way size | |
1044 | */ | |
1045 | way_size = sets * line_size; | |
1046 | *associativity = cache_size / way_size; | |
1047 | ||
1048 | if (way_size > max_way_size) { | |
1049 | pr_err("L2C OF: set size %dKB is too large\n", way_size); | |
d0b92845 | 1050 | return -EINVAL; |
f3354ab6 LW |
1051 | } |
1052 | ||
1053 | pr_info("L2C OF: override cache size: %d bytes (%dKB)\n", | |
1054 | cache_size, cache_size >> 10); | |
1055 | pr_info("L2C OF: override line size: %d bytes\n", line_size); | |
1056 | pr_info("L2C OF: override way size: %d bytes (%dKB)\n", | |
1057 | way_size, way_size >> 10); | |
1058 | pr_info("L2C OF: override associativity: %d\n", *associativity); | |
1059 | ||
1060 | /* | |
1061 | * Calculates the bits 17:19 to set for way size: | |
1062 | * 512KB -> 6, 256KB -> 5, ... 16KB -> 1 | |
1063 | */ | |
1064 | way_size_bits = ilog2(way_size >> 10) - 3; | |
1065 | if (way_size_bits < 1 || way_size_bits > 6) { | |
1066 | pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n", | |
1067 | way_size); | |
d0b92845 | 1068 | return -EINVAL; |
f3354ab6 LW |
1069 | } |
1070 | ||
1071 | mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; | |
1072 | val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); | |
1073 | ||
1074 | *aux_val &= ~mask; | |
1075 | *aux_val |= val; | |
1076 | *aux_mask &= ~mask; | |
d0b92845 FE |
1077 | |
1078 | return 0; | |
f3354ab6 LW |
1079 | } |
1080 | ||
da3627fb RK |
1081 | static void __init l2x0_of_parse(const struct device_node *np, |
1082 | u32 *aux_val, u32 *aux_mask) | |
1083 | { | |
1084 | u32 data[2] = { 0, 0 }; | |
1085 | u32 tag = 0; | |
1086 | u32 dirty = 0; | |
1087 | u32 val = 0, mask = 0; | |
f3354ab6 | 1088 | u32 assoc; |
d0b92845 | 1089 | int ret; |
da3627fb RK |
1090 | |
1091 | of_property_read_u32(np, "arm,tag-latency", &tag); | |
1092 | if (tag) { | |
1093 | mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; | |
1094 | val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; | |
1095 | } | |
1096 | ||
1097 | of_property_read_u32_array(np, "arm,data-latency", | |
1098 | data, ARRAY_SIZE(data)); | |
1099 | if (data[0] && data[1]) { | |
1100 | mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | | |
1101 | L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; | |
1102 | val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | | |
1103 | ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); | |
1104 | } | |
1105 | ||
1106 | of_property_read_u32(np, "arm,dirty-latency", &dirty); | |
1107 | if (dirty) { | |
1108 | mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; | |
1109 | val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; | |
1110 | } | |
1111 | ||
d0b92845 FE |
1112 | ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); |
1113 | if (ret) | |
1114 | return; | |
1115 | ||
f3354ab6 LW |
1116 | if (assoc > 8) { |
1117 | pr_err("l2x0 of: cache setting yield too high associativity\n"); | |
1118 | pr_err("l2x0 of: %d calculated, max 8\n", assoc); | |
1119 | } else { | |
1120 | mask |= L2X0_AUX_CTRL_ASSOC_MASK; | |
1121 | val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT); | |
1122 | } | |
1123 | ||
da3627fb RK |
1124 | *aux_val &= ~mask; |
1125 | *aux_val |= val; | |
1126 | *aux_mask &= ~mask; | |
1127 | } | |
1128 | ||
6a28cf59 | 1129 | static const struct l2c_init_data of_l2c210_data __initconst = { |
051334bd | 1130 | .type = "L2C-210", |
0493aef4 | 1131 | .way_size_0 = SZ_8K, |
6a28cf59 RK |
1132 | .num_lock = 1, |
1133 | .of_parse = l2x0_of_parse, | |
1134 | .enable = l2c_enable, | |
ddf7d79b | 1135 | .save = l2c_save, |
6a28cf59 RK |
1136 | .outer_cache = { |
1137 | .inv_range = l2c210_inv_range, | |
1138 | .clean_range = l2c210_clean_range, | |
1139 | .flush_range = l2c210_flush_range, | |
1140 | .flush_all = l2c210_flush_all, | |
1141 | .disable = l2c_disable, | |
1142 | .sync = l2c210_sync, | |
6b49241a | 1143 | .resume = l2c_resume, |
6a28cf59 RK |
1144 | }, |
1145 | }; | |
1146 | ||
733c6bba | 1147 | static const struct l2c_init_data of_l2c220_data __initconst = { |
051334bd | 1148 | .type = "L2C-220", |
0493aef4 | 1149 | .way_size_0 = SZ_8K, |
733c6bba | 1150 | .num_lock = 1, |
da3627fb | 1151 | .of_parse = l2x0_of_parse, |
a4b041a0 | 1152 | .enable = l2c220_enable, |
ddf7d79b | 1153 | .save = l2c_save, |
da3627fb | 1154 | .outer_cache = { |
733c6bba RK |
1155 | .inv_range = l2c220_inv_range, |
1156 | .clean_range = l2c220_clean_range, | |
1157 | .flush_range = l2c220_flush_range, | |
1158 | .flush_all = l2c220_flush_all, | |
1159 | .disable = l2c_disable, | |
1160 | .sync = l2c220_sync, | |
6b49241a | 1161 | .resume = l2c_resume, |
da3627fb RK |
1162 | }, |
1163 | }; | |
1164 | ||
f777332b RK |
1165 | static void __init l2c310_of_parse(const struct device_node *np, |
1166 | u32 *aux_val, u32 *aux_mask) | |
da3627fb RK |
1167 | { |
1168 | u32 data[3] = { 0, 0, 0 }; | |
1169 | u32 tag[3] = { 0, 0, 0 }; | |
1170 | u32 filter[2] = { 0, 0 }; | |
f3354ab6 | 1171 | u32 assoc; |
d0b92845 | 1172 | int ret; |
da3627fb RK |
1173 | |
1174 | of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); | |
1175 | if (tag[0] && tag[1] && tag[2]) | |
6b49241a | 1176 | l2x0_saved_regs.tag_latency = |
1a5a954c RK |
1177 | L310_LATENCY_CTRL_RD(tag[0] - 1) | |
1178 | L310_LATENCY_CTRL_WR(tag[1] - 1) | | |
6b49241a | 1179 | L310_LATENCY_CTRL_SETUP(tag[2] - 1); |
da3627fb RK |
1180 | |
1181 | of_property_read_u32_array(np, "arm,data-latency", | |
1182 | data, ARRAY_SIZE(data)); | |
1183 | if (data[0] && data[1] && data[2]) | |
6b49241a | 1184 | l2x0_saved_regs.data_latency = |
1a5a954c RK |
1185 | L310_LATENCY_CTRL_RD(data[0] - 1) | |
1186 | L310_LATENCY_CTRL_WR(data[1] - 1) | | |
6b49241a | 1187 | L310_LATENCY_CTRL_SETUP(data[2] - 1); |
da3627fb RK |
1188 | |
1189 | of_property_read_u32_array(np, "arm,filter-ranges", | |
1190 | filter, ARRAY_SIZE(filter)); | |
1191 | if (filter[1]) { | |
6b49241a TF |
1192 | l2x0_saved_regs.filter_end = |
1193 | ALIGN(filter[0] + filter[1], SZ_1M); | |
1194 | l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1)) | |
1195 | | L310_ADDR_FILTER_EN; | |
da3627fb | 1196 | } |
f3354ab6 | 1197 | |
d0b92845 FE |
1198 | ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); |
1199 | if (ret) | |
1200 | return; | |
1201 | ||
f3354ab6 LW |
1202 | switch (assoc) { |
1203 | case 16: | |
1204 | *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1205 | *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16; | |
1206 | *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1207 | break; | |
1208 | case 8: | |
1209 | *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1210 | *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1211 | break; | |
1212 | default: | |
6d0ec1dd FE |
1213 | pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n", |
1214 | assoc); | |
f3354ab6 LW |
1215 | break; |
1216 | } | |
da3627fb RK |
1217 | } |
1218 | ||
f777332b | 1219 | static const struct l2c_init_data of_l2c310_data __initconst = { |
051334bd | 1220 | .type = "L2C-310", |
0493aef4 | 1221 | .way_size_0 = SZ_8K, |
3b8bad57 | 1222 | .num_lock = 8, |
f777332b | 1223 | .of_parse = l2c310_of_parse, |
4374d649 | 1224 | .enable = l2c310_enable, |
75461f5c | 1225 | .fixup = l2c310_fixup, |
09a5d180 | 1226 | .save = l2c310_save, |
6b49241a | 1227 | .configure = l2c310_configure, |
da3627fb | 1228 | .outer_cache = { |
f777332b RK |
1229 | .inv_range = l2c210_inv_range, |
1230 | .clean_range = l2c210_clean_range, | |
1231 | .flush_range = l2c210_flush_range, | |
1232 | .flush_all = l2c210_flush_all, | |
8ef418c7 | 1233 | .disable = l2c310_disable, |
f777332b | 1234 | .sync = l2c210_sync, |
09a5d180 | 1235 | .resume = l2c310_resume, |
da3627fb RK |
1236 | }, |
1237 | }; | |
1238 | ||
98ea2dba TP |
1239 | /* |
1240 | * This is a variant of the of_l2c310_data with .sync set to | |
1241 | * NULL. Outer sync operations are not needed when the system is I/O | |
1242 | * coherent, and potentially harmful in certain situations (PCIe/PL310 | |
1243 | * deadlock on Armada 375/38x due to hardware I/O coherency). The | |
1244 | * other operations are kept because they are infrequent (therefore do | |
1245 | * not cause the deadlock in practice) and needed for secondary CPU | |
1246 | * boot and other power management activities. | |
1247 | */ | |
1248 | static const struct l2c_init_data of_l2c310_coherent_data __initconst = { | |
1249 | .type = "L2C-310 Coherent", | |
1250 | .way_size_0 = SZ_8K, | |
1251 | .num_lock = 8, | |
1252 | .of_parse = l2c310_of_parse, | |
1253 | .enable = l2c310_enable, | |
1254 | .fixup = l2c310_fixup, | |
1255 | .save = l2c310_save, | |
6b49241a | 1256 | .configure = l2c310_configure, |
98ea2dba TP |
1257 | .outer_cache = { |
1258 | .inv_range = l2c210_inv_range, | |
1259 | .clean_range = l2c210_clean_range, | |
1260 | .flush_range = l2c210_flush_range, | |
1261 | .flush_all = l2c210_flush_all, | |
1262 | .disable = l2c310_disable, | |
1263 | .resume = l2c310_resume, | |
1264 | }, | |
1265 | }; | |
1266 | ||
b8db6b88 GC |
1267 | /* |
1268 | * Note that the end addresses passed to Linux primitives are | |
1269 | * noninclusive, while the hardware cache range operations use | |
1270 | * inclusive start and end addresses. | |
1271 | */ | |
1272 | static unsigned long calc_range_end(unsigned long start, unsigned long end) | |
1273 | { | |
1274 | /* | |
1275 | * Limit the number of cache lines processed at once, | |
1276 | * since cache range operations stall the CPU pipeline | |
1277 | * until completion. | |
1278 | */ | |
1279 | if (end > start + MAX_RANGE_SIZE) | |
1280 | end = start + MAX_RANGE_SIZE; | |
1281 | ||
1282 | /* | |
1283 | * Cache range operations can't straddle a page boundary. | |
1284 | */ | |
1285 | if (end > PAGE_ALIGN(start+1)) | |
1286 | end = PAGE_ALIGN(start+1); | |
1287 | ||
1288 | return end; | |
1289 | } | |
1290 | ||
1291 | /* | |
1292 | * Make sure 'start' and 'end' reference the same page, as L2 is PIPT | |
1293 | * and range operations only do a TLB lookup on the start address. | |
1294 | */ | |
1295 | static void aurora_pa_range(unsigned long start, unsigned long end, | |
1296 | unsigned long offset) | |
1297 | { | |
1298 | unsigned long flags; | |
1299 | ||
1300 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
8a3a180d GC |
1301 | writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); |
1302 | writel_relaxed(end, l2x0_base + offset); | |
b8db6b88 GC |
1303 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
1304 | ||
1305 | cache_sync(); | |
1306 | } | |
1307 | ||
1308 | static void aurora_inv_range(unsigned long start, unsigned long end) | |
1309 | { | |
1310 | /* | |
1311 | * round start and end adresses up to cache line size | |
1312 | */ | |
1313 | start &= ~(CACHE_LINE_SIZE - 1); | |
1314 | end = ALIGN(end, CACHE_LINE_SIZE); | |
1315 | ||
1316 | /* | |
1317 | * Invalidate all full cache lines between 'start' and 'end'. | |
1318 | */ | |
1319 | while (start < end) { | |
1320 | unsigned long range_end = calc_range_end(start, end); | |
1321 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, | |
1322 | AURORA_INVAL_RANGE_REG); | |
1323 | start = range_end; | |
1324 | } | |
1325 | } | |
1326 | ||
1327 | static void aurora_clean_range(unsigned long start, unsigned long end) | |
1328 | { | |
1329 | /* | |
1330 | * If L2 is forced to WT, the L2 will always be clean and we | |
1331 | * don't need to do anything here. | |
1332 | */ | |
1333 | if (!l2_wt_override) { | |
1334 | start &= ~(CACHE_LINE_SIZE - 1); | |
1335 | end = ALIGN(end, CACHE_LINE_SIZE); | |
1336 | while (start != end) { | |
1337 | unsigned long range_end = calc_range_end(start, end); | |
1338 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, | |
1339 | AURORA_CLEAN_RANGE_REG); | |
1340 | start = range_end; | |
1341 | } | |
1342 | } | |
1343 | } | |
1344 | ||
1345 | static void aurora_flush_range(unsigned long start, unsigned long end) | |
1346 | { | |
8b827c60 GC |
1347 | start &= ~(CACHE_LINE_SIZE - 1); |
1348 | end = ALIGN(end, CACHE_LINE_SIZE); | |
1349 | while (start != end) { | |
1350 | unsigned long range_end = calc_range_end(start, end); | |
1351 | /* | |
1352 | * If L2 is forced to WT, the L2 will always be clean and we | |
1353 | * just need to invalidate. | |
1354 | */ | |
1355 | if (l2_wt_override) | |
b8db6b88 | 1356 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, |
8b827c60 GC |
1357 | AURORA_INVAL_RANGE_REG); |
1358 | else | |
1359 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, | |
1360 | AURORA_FLUSH_RANGE_REG); | |
1361 | start = range_end; | |
b8db6b88 GC |
1362 | } |
1363 | } | |
1364 | ||
da3627fb RK |
1365 | static void aurora_save(void __iomem *base) |
1366 | { | |
1367 | l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); | |
1368 | l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); | |
1369 | } | |
1370 | ||
40266d6f RK |
1371 | /* |
1372 | * For Aurora cache in no outer mode, enable via the CP15 coprocessor | |
1373 | * broadcasting of cache commands to L2. | |
1374 | */ | |
1375 | static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, | |
1376 | unsigned num_lock) | |
da3627fb | 1377 | { |
40266d6f RK |
1378 | u32 u; |
1379 | ||
1380 | asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); | |
da3627fb | 1381 | u |= AURORA_CTRL_FW; /* Set the FW bit */ |
40266d6f RK |
1382 | asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); |
1383 | ||
da3627fb | 1384 | isb(); |
40266d6f RK |
1385 | |
1386 | l2c_enable(base, aux, num_lock); | |
da3627fb RK |
1387 | } |
1388 | ||
75461f5c RK |
1389 | static void __init aurora_fixup(void __iomem *base, u32 cache_id, |
1390 | struct outer_cache_fns *fns) | |
1391 | { | |
1392 | sync_reg_offset = AURORA_SYNC_REG; | |
1393 | } | |
1394 | ||
da3627fb RK |
1395 | static void __init aurora_of_parse(const struct device_node *np, |
1396 | u32 *aux_val, u32 *aux_mask) | |
1397 | { | |
1398 | u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; | |
1399 | u32 mask = AURORA_ACR_REPLACEMENT_MASK; | |
1400 | ||
1401 | of_property_read_u32(np, "cache-id-part", | |
1402 | &cache_id_part_number_from_dt); | |
1403 | ||
1404 | /* Determine and save the write policy */ | |
1405 | l2_wt_override = of_property_read_bool(np, "wt-override"); | |
1406 | ||
1407 | if (l2_wt_override) { | |
1408 | val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; | |
1409 | mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; | |
1410 | } | |
1411 | ||
1412 | *aux_val &= ~mask; | |
1413 | *aux_val |= val; | |
1414 | *aux_mask &= ~mask; | |
1415 | } | |
1416 | ||
1417 | static const struct l2c_init_data of_aurora_with_outer_data __initconst = { | |
051334bd | 1418 | .type = "Aurora", |
0493aef4 | 1419 | .way_size_0 = SZ_4K, |
3b8bad57 | 1420 | .num_lock = 4, |
da3627fb | 1421 | .of_parse = aurora_of_parse, |
3b8bad57 | 1422 | .enable = l2c_enable, |
75461f5c | 1423 | .fixup = aurora_fixup, |
da3627fb RK |
1424 | .save = aurora_save, |
1425 | .outer_cache = { | |
1426 | .inv_range = aurora_inv_range, | |
1427 | .clean_range = aurora_clean_range, | |
1428 | .flush_range = aurora_flush_range, | |
1429 | .flush_all = l2x0_flush_all, | |
1430 | .disable = l2x0_disable, | |
1431 | .sync = l2x0_cache_sync, | |
6b49241a | 1432 | .resume = l2c_resume, |
da3627fb RK |
1433 | }, |
1434 | }; | |
1435 | ||
1436 | static const struct l2c_init_data of_aurora_no_outer_data __initconst = { | |
051334bd | 1437 | .type = "Aurora", |
0493aef4 | 1438 | .way_size_0 = SZ_4K, |
3b8bad57 | 1439 | .num_lock = 4, |
da3627fb | 1440 | .of_parse = aurora_of_parse, |
40266d6f | 1441 | .enable = aurora_enable_no_outer, |
75461f5c | 1442 | .fixup = aurora_fixup, |
da3627fb RK |
1443 | .save = aurora_save, |
1444 | .outer_cache = { | |
6b49241a | 1445 | .resume = l2c_resume, |
da3627fb RK |
1446 | }, |
1447 | }; | |
1448 | ||
3b656fed CD |
1449 | /* |
1450 | * For certain Broadcom SoCs, depending on the address range, different offsets | |
1451 | * need to be added to the address before passing it to L2 for | |
1452 | * invalidation/clean/flush | |
1453 | * | |
1454 | * Section Address Range Offset EMI | |
1455 | * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC | |
1456 | * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS | |
1457 | * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC | |
1458 | * | |
1459 | * When the start and end addresses have crossed two different sections, we | |
1460 | * need to break the L2 operation into two, each within its own section. | |
1461 | * For example, if we need to invalidate addresses starts at 0xBFFF0000 and | |
1462 | * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) | |
1463 | * 0xC0000000 - 0xC0001000 | |
1464 | * | |
1465 | * Note 1: | |
1466 | * By breaking a single L2 operation into two, we may potentially suffer some | |
1467 | * performance hit, but keep in mind the cross section case is very rare | |
1468 | * | |
1469 | * Note 2: | |
1470 | * We do not need to handle the case when the start address is in | |
1471 | * Section 1 and the end address is in Section 3, since it is not a valid use | |
1472 | * case | |
1473 | * | |
1474 | * Note 3: | |
1475 | * Section 1 in practical terms can no longer be used on rev A2. Because of | |
1476 | * that the code does not need to handle section 1 at all. | |
1477 | * | |
1478 | */ | |
1479 | #define BCM_SYS_EMI_START_ADDR 0x40000000UL | |
1480 | #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL | |
1481 | ||
1482 | #define BCM_SYS_EMI_OFFSET 0x40000000UL | |
1483 | #define BCM_VC_EMI_OFFSET 0x80000000UL | |
1484 | ||
1485 | static inline int bcm_addr_is_sys_emi(unsigned long addr) | |
1486 | { | |
1487 | return (addr >= BCM_SYS_EMI_START_ADDR) && | |
1488 | (addr < BCM_VC_EMI_SEC3_START_ADDR); | |
1489 | } | |
1490 | ||
1491 | static inline unsigned long bcm_l2_phys_addr(unsigned long addr) | |
1492 | { | |
1493 | if (bcm_addr_is_sys_emi(addr)) | |
1494 | return addr + BCM_SYS_EMI_OFFSET; | |
1495 | else | |
1496 | return addr + BCM_VC_EMI_OFFSET; | |
1497 | } | |
1498 | ||
1499 | static void bcm_inv_range(unsigned long start, unsigned long end) | |
1500 | { | |
1501 | unsigned long new_start, new_end; | |
1502 | ||
1503 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1504 | ||
1505 | if (unlikely(end <= start)) | |
1506 | return; | |
1507 | ||
1508 | new_start = bcm_l2_phys_addr(start); | |
1509 | new_end = bcm_l2_phys_addr(end); | |
1510 | ||
1511 | /* normal case, no cross section between start and end */ | |
1512 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
90811148 | 1513 | l2c210_inv_range(new_start, new_end); |
3b656fed CD |
1514 | return; |
1515 | } | |
1516 | ||
1517 | /* They cross sections, so it can only be a cross from section | |
1518 | * 2 to section 3 | |
1519 | */ | |
90811148 | 1520 | l2c210_inv_range(new_start, |
3b656fed | 1521 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); |
90811148 | 1522 | l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), |
3b656fed CD |
1523 | new_end); |
1524 | } | |
1525 | ||
1526 | static void bcm_clean_range(unsigned long start, unsigned long end) | |
1527 | { | |
1528 | unsigned long new_start, new_end; | |
1529 | ||
1530 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1531 | ||
1532 | if (unlikely(end <= start)) | |
1533 | return; | |
1534 | ||
3b656fed CD |
1535 | new_start = bcm_l2_phys_addr(start); |
1536 | new_end = bcm_l2_phys_addr(end); | |
1537 | ||
1538 | /* normal case, no cross section between start and end */ | |
1539 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
90811148 | 1540 | l2c210_clean_range(new_start, new_end); |
3b656fed CD |
1541 | return; |
1542 | } | |
1543 | ||
1544 | /* They cross sections, so it can only be a cross from section | |
1545 | * 2 to section 3 | |
1546 | */ | |
90811148 | 1547 | l2c210_clean_range(new_start, |
3b656fed | 1548 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); |
90811148 | 1549 | l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), |
3b656fed CD |
1550 | new_end); |
1551 | } | |
1552 | ||
1553 | static void bcm_flush_range(unsigned long start, unsigned long end) | |
1554 | { | |
1555 | unsigned long new_start, new_end; | |
1556 | ||
1557 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1558 | ||
1559 | if (unlikely(end <= start)) | |
1560 | return; | |
1561 | ||
1562 | if ((end - start) >= l2x0_size) { | |
90811148 | 1563 | outer_cache.flush_all(); |
3b656fed CD |
1564 | return; |
1565 | } | |
1566 | ||
1567 | new_start = bcm_l2_phys_addr(start); | |
1568 | new_end = bcm_l2_phys_addr(end); | |
1569 | ||
1570 | /* normal case, no cross section between start and end */ | |
1571 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
90811148 | 1572 | l2c210_flush_range(new_start, new_end); |
3b656fed CD |
1573 | return; |
1574 | } | |
1575 | ||
1576 | /* They cross sections, so it can only be a cross from section | |
1577 | * 2 to section 3 | |
1578 | */ | |
90811148 | 1579 | l2c210_flush_range(new_start, |
3b656fed | 1580 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); |
90811148 | 1581 | l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), |
3b656fed CD |
1582 | new_end); |
1583 | } | |
1584 | ||
90811148 | 1585 | /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */ |
da3627fb | 1586 | static const struct l2c_init_data of_bcm_l2x0_data __initconst = { |
051334bd | 1587 | .type = "BCM-L2C-310", |
0493aef4 | 1588 | .way_size_0 = SZ_8K, |
3b8bad57 | 1589 | .num_lock = 8, |
f777332b | 1590 | .of_parse = l2c310_of_parse, |
4374d649 | 1591 | .enable = l2c310_enable, |
09a5d180 | 1592 | .save = l2c310_save, |
6b49241a | 1593 | .configure = l2c310_configure, |
da3627fb RK |
1594 | .outer_cache = { |
1595 | .inv_range = bcm_inv_range, | |
1596 | .clean_range = bcm_clean_range, | |
1597 | .flush_range = bcm_flush_range, | |
f777332b | 1598 | .flush_all = l2c210_flush_all, |
8ef418c7 | 1599 | .disable = l2c310_disable, |
f777332b | 1600 | .sync = l2c210_sync, |
09a5d180 | 1601 | .resume = l2c310_resume, |
da3627fb RK |
1602 | }, |
1603 | }; | |
b8db6b88 | 1604 | |
9846dfc9 | 1605 | static void __init tauros3_save(void __iomem *base) |
e68f31f4 | 1606 | { |
ddf7d79b RK |
1607 | l2c_save(base); |
1608 | ||
e68f31f4 | 1609 | l2x0_saved_regs.aux2_ctrl = |
9846dfc9 | 1610 | readl_relaxed(base + TAUROS3_AUX2_CTRL); |
e68f31f4 | 1611 | l2x0_saved_regs.prefetch_ctrl = |
1a5a954c | 1612 | readl_relaxed(base + L310_PREFETCH_CTRL); |
e68f31f4 SH |
1613 | } |
1614 | ||
6b49241a | 1615 | static void tauros3_configure(void __iomem *base) |
e68f31f4 | 1616 | { |
6b49241a TF |
1617 | writel_relaxed(l2x0_saved_regs.aux2_ctrl, |
1618 | base + TAUROS3_AUX2_CTRL); | |
1619 | writel_relaxed(l2x0_saved_regs.prefetch_ctrl, | |
1620 | base + L310_PREFETCH_CTRL); | |
e68f31f4 SH |
1621 | } |
1622 | ||
c02642bc | 1623 | static const struct l2c_init_data of_tauros3_data __initconst = { |
051334bd | 1624 | .type = "Tauros3", |
0493aef4 | 1625 | .way_size_0 = SZ_8K, |
3b8bad57 RK |
1626 | .num_lock = 8, |
1627 | .enable = l2c_enable, | |
e68f31f4 | 1628 | .save = tauros3_save, |
6b49241a | 1629 | .configure = tauros3_configure, |
e68f31f4 SH |
1630 | /* Tauros3 broadcasts L1 cache operations to L2 */ |
1631 | .outer_cache = { | |
6b49241a | 1632 | .resume = l2c_resume, |
e68f31f4 SH |
1633 | }, |
1634 | }; | |
1635 | ||
a65bb925 | 1636 | #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } |
8c369264 | 1637 | static const struct of_device_id l2x0_ids[] __initconst = { |
6a28cf59 | 1638 | L2C_ID("arm,l210-cache", of_l2c210_data), |
733c6bba | 1639 | L2C_ID("arm,l220-cache", of_l2c220_data), |
f777332b | 1640 | L2C_ID("arm,pl310-cache", of_l2c310_data), |
c02642bc RK |
1641 | L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), |
1642 | L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), | |
1643 | L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), | |
1644 | L2C_ID("marvell,tauros3-cache", of_tauros3_data), | |
a65bb925 | 1645 | /* Deprecated IDs */ |
c02642bc | 1646 | L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), |
8c369264 RH |
1647 | {} |
1648 | }; | |
1649 | ||
3e175ca4 | 1650 | int __init l2x0_of_init(u32 aux_val, u32 aux_mask) |
8c369264 | 1651 | { |
c02642bc | 1652 | const struct l2c_init_data *data; |
8c369264 | 1653 | struct device_node *np; |
91c2ebb9 | 1654 | struct resource res; |
560be613 | 1655 | u32 cache_id, old_aux; |
8c369264 RH |
1656 | |
1657 | np = of_find_matching_node(NULL, l2x0_ids); | |
1658 | if (!np) | |
1659 | return -ENODEV; | |
91c2ebb9 BS |
1660 | |
1661 | if (of_address_to_resource(np, 0, &res)) | |
1662 | return -ENODEV; | |
1663 | ||
1664 | l2x0_base = ioremap(res.start, resource_size(&res)); | |
8c369264 RH |
1665 | if (!l2x0_base) |
1666 | return -ENOMEM; | |
1667 | ||
91c2ebb9 BS |
1668 | l2x0_saved_regs.phy_base = res.start; |
1669 | ||
1670 | data = of_match_node(l2x0_ids, np)->data; | |
1671 | ||
98ea2dba TP |
1672 | if (of_device_is_compatible(np, "arm,pl310-cache") && |
1673 | of_property_read_bool(np, "arm,io-coherent")) | |
1674 | data = &of_l2c310_coherent_data; | |
1675 | ||
560be613 RK |
1676 | old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
1677 | if (old_aux != ((old_aux & aux_mask) | aux_val)) { | |
1678 | pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n", | |
1679 | old_aux, (old_aux & aux_mask) | aux_val); | |
1680 | } else if (aux_mask != ~0U && aux_val != 0) { | |
1681 | pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n"); | |
1682 | } | |
1683 | ||
d9d1f3e2 RK |
1684 | /* All L2 caches are unified, so this property should be specified */ |
1685 | if (!of_property_read_bool(np, "cache-unified")) | |
1686 | pr_err("L2C: device tree omits to specify unified cache\n"); | |
1687 | ||
6b49241a TF |
1688 | /* Read back current (default) hardware configuration */ |
1689 | if (data->save) | |
1690 | data->save(l2x0_base); | |
1691 | ||
8c369264 | 1692 | /* L2 configuration can only be changed if the cache is disabled */ |
40266d6f | 1693 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) |
c02642bc RK |
1694 | if (data->of_parse) |
1695 | data->of_parse(np, &aux_val, &aux_mask); | |
b8db6b88 | 1696 | |
96054b0a RK |
1697 | if (cache_id_part_number_from_dt) |
1698 | cache_id = cache_id_part_number_from_dt; | |
1699 | else | |
1700 | cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); | |
1701 | ||
6b49241a | 1702 | return __l2c_init(data, aux_val, aux_mask, cache_id); |
8c369264 RH |
1703 | } |
1704 | #endif |