Commit | Line | Data |
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382266ad | 1 | /* |
b69a7806 | 2 | * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support |
382266ad CM |
3 | * |
4 | * Copyright (C) 2007 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
8ef418c7 | 19 | #include <linux/cpu.h> |
8c369264 | 20 | #include <linux/err.h> |
382266ad | 21 | #include <linux/init.h> |
8ef418c7 | 22 | #include <linux/smp.h> |
07620976 | 23 | #include <linux/spinlock.h> |
f3354ab6 | 24 | #include <linux/log2.h> |
fced80c7 | 25 | #include <linux/io.h> |
8c369264 RH |
26 | #include <linux/of.h> |
27 | #include <linux/of_address.h> | |
382266ad CM |
28 | |
29 | #include <asm/cacheflush.h> | |
8ef418c7 | 30 | #include <asm/cp15.h> |
4374d649 | 31 | #include <asm/cputype.h> |
382266ad | 32 | #include <asm/hardware/cache-l2x0.h> |
e68f31f4 | 33 | #include "cache-tauros3.h" |
b8db6b88 | 34 | #include "cache-aurora-l2.h" |
382266ad | 35 | |
c02642bc | 36 | struct l2c_init_data { |
051334bd | 37 | const char *type; |
0493aef4 | 38 | unsigned way_size_0; |
3b8bad57 | 39 | unsigned num_lock; |
c02642bc | 40 | void (*of_parse)(const struct device_node *, u32 *, u32 *); |
3b8bad57 | 41 | void (*enable)(void __iomem *, u32, unsigned); |
75461f5c | 42 | void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); |
9846dfc9 | 43 | void (*save)(void __iomem *); |
6b49241a | 44 | void (*configure)(void __iomem *); |
c02642bc RK |
45 | struct outer_cache_fns outer_cache; |
46 | }; | |
47 | ||
382266ad CM |
48 | #define CACHE_LINE_SIZE 32 |
49 | ||
50 | static void __iomem *l2x0_base; | |
6b49241a | 51 | static const struct l2c_init_data *l2x0_data; |
bd31b859 | 52 | static DEFINE_RAW_SPINLOCK(l2x0_lock); |
3e175ca4 RK |
53 | static u32 l2x0_way_mask; /* Bitmask of active ways */ |
54 | static u32 l2x0_size; | |
f154fe9b | 55 | static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; |
382266ad | 56 | |
91c2ebb9 BS |
57 | struct l2x0_regs l2x0_saved_regs; |
58 | ||
37abcdb9 RK |
59 | /* |
60 | * Common code for all cache controllers. | |
61 | */ | |
83841fe1 | 62 | static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) |
382266ad | 63 | { |
9a6655e4 | 64 | /* wait for cache operation by line or way to complete */ |
6775a558 | 65 | while (readl_relaxed(reg) & mask) |
1caf3092 | 66 | cpu_relax(); |
382266ad CM |
67 | } |
68 | ||
8abd259f RK |
69 | /* |
70 | * By default, we write directly to secure registers. Platforms must | |
71 | * override this if they are running non-secure. | |
72 | */ | |
73 | static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) | |
74 | { | |
75 | if (val == readl_relaxed(base + reg)) | |
76 | return; | |
77 | if (outer_cache.write_sec) | |
78 | outer_cache.write_sec(val, reg); | |
79 | else | |
80 | writel_relaxed(val, base + reg); | |
81 | } | |
82 | ||
2b2a87a1 RK |
83 | /* |
84 | * This should only be called when we have a requirement that the | |
85 | * register be written due to a work-around, as platforms running | |
86 | * in non-secure mode may not be able to access this register. | |
87 | */ | |
88 | static inline void l2c_set_debug(void __iomem *base, unsigned long val) | |
89 | { | |
678ea28b | 90 | l2c_write_sec(val, base, L2X0_DEBUG_CTRL); |
2b2a87a1 RK |
91 | } |
92 | ||
df5dd4c6 RK |
93 | static void __l2c_op_way(void __iomem *reg) |
94 | { | |
95 | writel_relaxed(l2x0_way_mask, reg); | |
83841fe1 | 96 | l2c_wait_mask(reg, l2x0_way_mask); |
df5dd4c6 RK |
97 | } |
98 | ||
37abcdb9 RK |
99 | static inline void l2c_unlock(void __iomem *base, unsigned num) |
100 | { | |
101 | unsigned i; | |
102 | ||
103 | for (i = 0; i < num; i++) { | |
104 | writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + | |
105 | i * L2X0_LOCKDOWN_STRIDE); | |
106 | writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + | |
107 | i * L2X0_LOCKDOWN_STRIDE); | |
108 | } | |
109 | } | |
110 | ||
6b49241a TF |
111 | static void l2c_configure(void __iomem *base) |
112 | { | |
7705dd25 | 113 | l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); |
6b49241a TF |
114 | } |
115 | ||
3b8bad57 RK |
116 | /* |
117 | * Enable the L2 cache controller. This function must only be | |
118 | * called when the cache controller is known to be disabled. | |
119 | */ | |
120 | static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) | |
121 | { | |
122 | unsigned long flags; | |
123 | ||
6b49241a | 124 | l2x0_saved_regs.aux_ctrl = aux; |
50beefde RK |
125 | |
126 | if (outer_cache.configure) | |
127 | outer_cache.configure(&l2x0_saved_regs); | |
128 | else | |
129 | l2x0_data->configure(base); | |
3b8bad57 | 130 | |
17f3f99f RK |
131 | l2c_unlock(base, num_lock); |
132 | ||
3b8bad57 RK |
133 | local_irq_save(flags); |
134 | __l2c_op_way(base + L2X0_INV_WAY); | |
135 | writel_relaxed(0, base + sync_reg_offset); | |
136 | l2c_wait_mask(base + sync_reg_offset, 1); | |
137 | local_irq_restore(flags); | |
138 | ||
8abd259f | 139 | l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL); |
3b8bad57 RK |
140 | } |
141 | ||
142 | static void l2c_disable(void) | |
143 | { | |
144 | void __iomem *base = l2x0_base; | |
145 | ||
146 | outer_cache.flush_all(); | |
8abd259f | 147 | l2c_write_sec(0, base, L2X0_CTRL); |
3b8bad57 RK |
148 | dsb(st); |
149 | } | |
150 | ||
ddf7d79b | 151 | static void l2c_save(void __iomem *base) |
2fd86589 | 152 | { |
ddf7d79b | 153 | l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
2fd86589 TG |
154 | } |
155 | ||
6b49241a | 156 | static void l2c_resume(void) |
ddf7d79b | 157 | { |
d965b0fc RK |
158 | void __iomem *base = l2x0_base; |
159 | ||
160 | /* Do not touch the controller if already enabled. */ | |
161 | if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) | |
162 | l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock); | |
ddf7d79b RK |
163 | } |
164 | ||
6a28cf59 RK |
165 | /* |
166 | * L2C-210 specific code. | |
167 | * | |
168 | * The L2C-2x0 PA, set/way and sync operations are atomic, but we must | |
169 | * ensure that no background operation is running. The way operations | |
170 | * are all background tasks. | |
171 | * | |
172 | * While a background operation is in progress, any new operation is | |
173 | * ignored (unspecified whether this causes an error.) Thankfully, not | |
174 | * used on SMP. | |
175 | * | |
176 | * Never has a different sync register other than L2X0_CACHE_SYNC, but | |
177 | * we use sync_reg_offset here so we can share some of this with L2C-310. | |
178 | */ | |
179 | static void __l2c210_cache_sync(void __iomem *base) | |
180 | { | |
181 | writel_relaxed(0, base + sync_reg_offset); | |
182 | } | |
183 | ||
184 | static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, | |
185 | unsigned long end) | |
186 | { | |
187 | while (start < end) { | |
188 | writel_relaxed(start, reg); | |
189 | start += CACHE_LINE_SIZE; | |
190 | } | |
191 | } | |
192 | ||
193 | static void l2c210_inv_range(unsigned long start, unsigned long end) | |
194 | { | |
195 | void __iomem *base = l2x0_base; | |
196 | ||
197 | if (start & (CACHE_LINE_SIZE - 1)) { | |
198 | start &= ~(CACHE_LINE_SIZE - 1); | |
199 | writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); | |
200 | start += CACHE_LINE_SIZE; | |
201 | } | |
202 | ||
203 | if (end & (CACHE_LINE_SIZE - 1)) { | |
204 | end &= ~(CACHE_LINE_SIZE - 1); | |
205 | writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); | |
206 | } | |
207 | ||
208 | __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); | |
209 | __l2c210_cache_sync(base); | |
210 | } | |
211 | ||
212 | static void l2c210_clean_range(unsigned long start, unsigned long end) | |
213 | { | |
214 | void __iomem *base = l2x0_base; | |
215 | ||
216 | start &= ~(CACHE_LINE_SIZE - 1); | |
217 | __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); | |
218 | __l2c210_cache_sync(base); | |
219 | } | |
220 | ||
221 | static void l2c210_flush_range(unsigned long start, unsigned long end) | |
222 | { | |
223 | void __iomem *base = l2x0_base; | |
224 | ||
225 | start &= ~(CACHE_LINE_SIZE - 1); | |
226 | __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); | |
227 | __l2c210_cache_sync(base); | |
228 | } | |
229 | ||
230 | static void l2c210_flush_all(void) | |
231 | { | |
232 | void __iomem *base = l2x0_base; | |
233 | ||
234 | BUG_ON(!irqs_disabled()); | |
235 | ||
236 | __l2c_op_way(base + L2X0_CLEAN_INV_WAY); | |
237 | __l2c210_cache_sync(base); | |
238 | } | |
239 | ||
240 | static void l2c210_sync(void) | |
241 | { | |
242 | __l2c210_cache_sync(l2x0_base); | |
243 | } | |
244 | ||
6a28cf59 | 245 | static const struct l2c_init_data l2c210_data __initconst = { |
051334bd | 246 | .type = "L2C-210", |
0493aef4 | 247 | .way_size_0 = SZ_8K, |
6a28cf59 RK |
248 | .num_lock = 1, |
249 | .enable = l2c_enable, | |
ddf7d79b | 250 | .save = l2c_save, |
50beefde | 251 | .configure = l2c_configure, |
6a28cf59 RK |
252 | .outer_cache = { |
253 | .inv_range = l2c210_inv_range, | |
254 | .clean_range = l2c210_clean_range, | |
255 | .flush_range = l2c210_flush_range, | |
256 | .flush_all = l2c210_flush_all, | |
257 | .disable = l2c_disable, | |
258 | .sync = l2c210_sync, | |
6b49241a | 259 | .resume = l2c_resume, |
6a28cf59 RK |
260 | }, |
261 | }; | |
262 | ||
733c6bba RK |
263 | /* |
264 | * L2C-220 specific code. | |
265 | * | |
266 | * All operations are background operations: they have to be waited for. | |
267 | * Conflicting requests generate a slave error (which will cause an | |
268 | * imprecise abort.) Never uses sync_reg_offset, so we hard-code the | |
269 | * sync register here. | |
270 | * | |
271 | * However, we can re-use the l2c210_resume call. | |
272 | */ | |
273 | static inline void __l2c220_cache_sync(void __iomem *base) | |
274 | { | |
275 | writel_relaxed(0, base + L2X0_CACHE_SYNC); | |
276 | l2c_wait_mask(base + L2X0_CACHE_SYNC, 1); | |
277 | } | |
278 | ||
279 | static void l2c220_op_way(void __iomem *base, unsigned reg) | |
280 | { | |
281 | unsigned long flags; | |
282 | ||
283 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
284 | __l2c_op_way(base + reg); | |
285 | __l2c220_cache_sync(base); | |
286 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
287 | } | |
288 | ||
289 | static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, | |
290 | unsigned long end, unsigned long flags) | |
291 | { | |
292 | raw_spinlock_t *lock = &l2x0_lock; | |
293 | ||
294 | while (start < end) { | |
295 | unsigned long blk_end = start + min(end - start, 4096UL); | |
296 | ||
297 | while (start < blk_end) { | |
298 | l2c_wait_mask(reg, 1); | |
299 | writel_relaxed(start, reg); | |
300 | start += CACHE_LINE_SIZE; | |
301 | } | |
302 | ||
303 | if (blk_end < end) { | |
304 | raw_spin_unlock_irqrestore(lock, flags); | |
305 | raw_spin_lock_irqsave(lock, flags); | |
306 | } | |
307 | } | |
308 | ||
309 | return flags; | |
310 | } | |
311 | ||
312 | static void l2c220_inv_range(unsigned long start, unsigned long end) | |
313 | { | |
314 | void __iomem *base = l2x0_base; | |
315 | unsigned long flags; | |
316 | ||
317 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
318 | if ((start | end) & (CACHE_LINE_SIZE - 1)) { | |
319 | if (start & (CACHE_LINE_SIZE - 1)) { | |
320 | start &= ~(CACHE_LINE_SIZE - 1); | |
321 | writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); | |
322 | start += CACHE_LINE_SIZE; | |
323 | } | |
324 | ||
325 | if (end & (CACHE_LINE_SIZE - 1)) { | |
326 | end &= ~(CACHE_LINE_SIZE - 1); | |
327 | l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
328 | writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); | |
329 | } | |
330 | } | |
331 | ||
332 | flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA, | |
333 | start, end, flags); | |
334 | l2c_wait_mask(base + L2X0_INV_LINE_PA, 1); | |
335 | __l2c220_cache_sync(base); | |
336 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
337 | } | |
338 | ||
339 | static void l2c220_clean_range(unsigned long start, unsigned long end) | |
340 | { | |
341 | void __iomem *base = l2x0_base; | |
342 | unsigned long flags; | |
343 | ||
344 | start &= ~(CACHE_LINE_SIZE - 1); | |
345 | if ((end - start) >= l2x0_size) { | |
346 | l2c220_op_way(base, L2X0_CLEAN_WAY); | |
347 | return; | |
348 | } | |
349 | ||
350 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
351 | flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA, | |
352 | start, end, flags); | |
353 | l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
354 | __l2c220_cache_sync(base); | |
355 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
356 | } | |
357 | ||
358 | static void l2c220_flush_range(unsigned long start, unsigned long end) | |
359 | { | |
360 | void __iomem *base = l2x0_base; | |
361 | unsigned long flags; | |
362 | ||
363 | start &= ~(CACHE_LINE_SIZE - 1); | |
364 | if ((end - start) >= l2x0_size) { | |
365 | l2c220_op_way(base, L2X0_CLEAN_INV_WAY); | |
366 | return; | |
367 | } | |
368 | ||
369 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
370 | flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, | |
371 | start, end, flags); | |
372 | l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
373 | __l2c220_cache_sync(base); | |
374 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
375 | } | |
376 | ||
377 | static void l2c220_flush_all(void) | |
378 | { | |
379 | l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY); | |
380 | } | |
381 | ||
382 | static void l2c220_sync(void) | |
383 | { | |
384 | unsigned long flags; | |
385 | ||
386 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
387 | __l2c220_cache_sync(l2x0_base); | |
388 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
389 | } | |
390 | ||
a4b041a0 RK |
391 | static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) |
392 | { | |
393 | /* | |
394 | * Always enable non-secure access to the lockdown registers - | |
395 | * we write to them as part of the L2C enable sequence so they | |
396 | * need to be accessible. | |
397 | */ | |
398 | aux |= L220_AUX_CTRL_NS_LOCKDOWN; | |
399 | ||
400 | l2c_enable(base, aux, num_lock); | |
401 | } | |
402 | ||
733c6bba | 403 | static const struct l2c_init_data l2c220_data = { |
051334bd | 404 | .type = "L2C-220", |
0493aef4 | 405 | .way_size_0 = SZ_8K, |
733c6bba | 406 | .num_lock = 1, |
a4b041a0 | 407 | .enable = l2c220_enable, |
ddf7d79b | 408 | .save = l2c_save, |
50beefde | 409 | .configure = l2c_configure, |
733c6bba RK |
410 | .outer_cache = { |
411 | .inv_range = l2c220_inv_range, | |
412 | .clean_range = l2c220_clean_range, | |
413 | .flush_range = l2c220_flush_range, | |
414 | .flush_all = l2c220_flush_all, | |
415 | .disable = l2c_disable, | |
416 | .sync = l2c220_sync, | |
6b49241a | 417 | .resume = l2c_resume, |
733c6bba RK |
418 | }, |
419 | }; | |
420 | ||
75461f5c RK |
421 | /* |
422 | * L2C-310 specific code. | |
423 | * | |
f777332b RK |
424 | * Very similar to L2C-210, the PA, set/way and sync operations are atomic, |
425 | * and the way operations are all background tasks. However, issuing an | |
426 | * operation while a background operation is in progress results in a | |
427 | * SLVERR response. We can reuse: | |
428 | * | |
429 | * __l2c210_cache_sync (using sync_reg_offset) | |
430 | * l2c210_sync | |
431 | * l2c210_inv_range (if 588369 is not applicable) | |
432 | * l2c210_clean_range | |
433 | * l2c210_flush_range (if 588369 is not applicable) | |
434 | * l2c210_flush_all (if 727915 is not applicable) | |
435 | * | |
75461f5c RK |
436 | * Errata: |
437 | * 588369: PL310 R0P0->R1P0, fixed R2P0. | |
438 | * Affects: all clean+invalidate operations | |
439 | * clean and invalidate skips the invalidate step, so we need to issue | |
440 | * separate operations. We also require the above debug workaround | |
441 | * enclosing this code fragment on affected parts. On unaffected parts, | |
442 | * we must not use this workaround without the debug register writes | |
443 | * to avoid exposing a problem similar to 727915. | |
444 | * | |
445 | * 727915: PL310 R2P0->R3P0, fixed R3P1. | |
446 | * Affects: clean+invalidate by way | |
447 | * clean and invalidate by way runs in the background, and a store can | |
448 | * hit the line between the clean operation and invalidate operation, | |
449 | * resulting in the store being lost. | |
450 | * | |
a8875a09 RK |
451 | * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2. |
452 | * Affects: 8x64-bit (double fill) line fetches | |
453 | * double fill line fetches can fail to cause dirty data to be evicted | |
454 | * from the cache before the new data overwrites the second line. | |
455 | * | |
75461f5c RK |
456 | * 753970: PL310 R3P0, fixed R3P1. |
457 | * Affects: sync | |
458 | * prevents merging writes after the sync operation, until another L2C | |
459 | * operation is performed (or a number of other conditions.) | |
460 | * | |
461 | * 769419: PL310 R0P0->R3P1, fixed R3P2. | |
462 | * Affects: store buffer | |
463 | * store buffer is not automatically drained. | |
464 | */ | |
ebd4219f RK |
465 | static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) |
466 | { | |
467 | void __iomem *base = l2x0_base; | |
468 | ||
469 | if ((start | end) & (CACHE_LINE_SIZE - 1)) { | |
470 | unsigned long flags; | |
471 | ||
472 | /* Erratum 588369 for both clean+invalidate operations */ | |
473 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
474 | l2c_set_debug(base, 0x03); | |
475 | ||
476 | if (start & (CACHE_LINE_SIZE - 1)) { | |
477 | start &= ~(CACHE_LINE_SIZE - 1); | |
478 | writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); | |
479 | writel_relaxed(start, base + L2X0_INV_LINE_PA); | |
480 | start += CACHE_LINE_SIZE; | |
481 | } | |
482 | ||
483 | if (end & (CACHE_LINE_SIZE - 1)) { | |
484 | end &= ~(CACHE_LINE_SIZE - 1); | |
485 | writel_relaxed(end, base + L2X0_CLEAN_LINE_PA); | |
486 | writel_relaxed(end, base + L2X0_INV_LINE_PA); | |
487 | } | |
488 | ||
489 | l2c_set_debug(base, 0x00); | |
490 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
491 | } | |
492 | ||
493 | __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); | |
494 | __l2c210_cache_sync(base); | |
495 | } | |
496 | ||
497 | static void l2c310_flush_range_erratum(unsigned long start, unsigned long end) | |
498 | { | |
499 | raw_spinlock_t *lock = &l2x0_lock; | |
500 | unsigned long flags; | |
501 | void __iomem *base = l2x0_base; | |
502 | ||
503 | raw_spin_lock_irqsave(lock, flags); | |
504 | while (start < end) { | |
505 | unsigned long blk_end = start + min(end - start, 4096UL); | |
506 | ||
507 | l2c_set_debug(base, 0x03); | |
508 | while (start < blk_end) { | |
509 | writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); | |
510 | writel_relaxed(start, base + L2X0_INV_LINE_PA); | |
511 | start += CACHE_LINE_SIZE; | |
512 | } | |
513 | l2c_set_debug(base, 0x00); | |
514 | ||
515 | if (blk_end < end) { | |
516 | raw_spin_unlock_irqrestore(lock, flags); | |
517 | raw_spin_lock_irqsave(lock, flags); | |
518 | } | |
519 | } | |
520 | raw_spin_unlock_irqrestore(lock, flags); | |
521 | __l2c210_cache_sync(base); | |
522 | } | |
523 | ||
99ca1772 RK |
524 | static void l2c310_flush_all_erratum(void) |
525 | { | |
526 | void __iomem *base = l2x0_base; | |
527 | unsigned long flags; | |
528 | ||
529 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
530 | l2c_set_debug(base, 0x03); | |
531 | __l2c_op_way(base + L2X0_CLEAN_INV_WAY); | |
532 | l2c_set_debug(base, 0x00); | |
533 | __l2c210_cache_sync(base); | |
534 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
535 | } | |
536 | ||
09a5d180 | 537 | static void __init l2c310_save(void __iomem *base) |
b98556f2 | 538 | { |
09a5d180 | 539 | unsigned revision; |
b98556f2 | 540 | |
ddf7d79b RK |
541 | l2c_save(base); |
542 | ||
b98556f2 | 543 | l2x0_saved_regs.tag_latency = readl_relaxed(base + |
1a5a954c | 544 | L310_TAG_LATENCY_CTRL); |
b98556f2 | 545 | l2x0_saved_regs.data_latency = readl_relaxed(base + |
1a5a954c | 546 | L310_DATA_LATENCY_CTRL); |
b98556f2 | 547 | l2x0_saved_regs.filter_end = readl_relaxed(base + |
1a5a954c | 548 | L310_ADDR_FILTER_END); |
b98556f2 | 549 | l2x0_saved_regs.filter_start = readl_relaxed(base + |
1a5a954c | 550 | L310_ADDR_FILTER_START); |
b98556f2 | 551 | |
09a5d180 RK |
552 | revision = readl_relaxed(base + L2X0_CACHE_ID) & |
553 | L2X0_CACHE_ID_RTL_MASK; | |
554 | ||
555 | /* From r2p0, there is Prefetch offset/control register */ | |
556 | if (revision >= L310_CACHE_ID_RTL_R2P0) | |
b98556f2 | 557 | l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + |
1a5a954c | 558 | L310_PREFETCH_CTRL); |
09a5d180 RK |
559 | |
560 | /* From r3p0, there is Power control register */ | |
561 | if (revision >= L310_CACHE_ID_RTL_R3P0) | |
562 | l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + | |
1a5a954c | 563 | L310_POWER_CTRL); |
b98556f2 RK |
564 | } |
565 | ||
6b49241a | 566 | static void l2c310_configure(void __iomem *base) |
b98556f2 | 567 | { |
6b49241a | 568 | unsigned revision; |
09a5d180 | 569 | |
50beefde RK |
570 | l2c_configure(base); |
571 | ||
6b49241a TF |
572 | /* restore pl310 setup */ |
573 | l2c_write_sec(l2x0_saved_regs.tag_latency, base, | |
574 | L310_TAG_LATENCY_CTRL); | |
575 | l2c_write_sec(l2x0_saved_regs.data_latency, base, | |
576 | L310_DATA_LATENCY_CTRL); | |
577 | l2c_write_sec(l2x0_saved_regs.filter_end, base, | |
578 | L310_ADDR_FILTER_END); | |
579 | l2c_write_sec(l2x0_saved_regs.filter_start, base, | |
580 | L310_ADDR_FILTER_START); | |
581 | ||
582 | revision = readl_relaxed(base + L2X0_CACHE_ID) & | |
583 | L2X0_CACHE_ID_RTL_MASK; | |
584 | ||
585 | if (revision >= L310_CACHE_ID_RTL_R2P0) | |
586 | l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, | |
587 | L310_PREFETCH_CTRL); | |
588 | if (revision >= L310_CACHE_ID_RTL_R3P0) | |
589 | l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base, | |
590 | L310_POWER_CTRL); | |
8ef418c7 RK |
591 | } |
592 | ||
593 | static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data) | |
594 | { | |
595 | switch (act & ~CPU_TASKS_FROZEN) { | |
596 | case CPU_STARTING: | |
597 | set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); | |
598 | break; | |
599 | case CPU_DYING: | |
600 | set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); | |
601 | break; | |
09a5d180 | 602 | } |
8ef418c7 | 603 | return NOTIFY_OK; |
b98556f2 RK |
604 | } |
605 | ||
4374d649 RK |
606 | static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) |
607 | { | |
9a2c33a4 | 608 | unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; |
af040ffc | 609 | bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9; |
4374d649 RK |
610 | |
611 | if (rev >= L310_CACHE_ID_RTL_R2P0) { | |
612 | if (cortex_a9) { | |
613 | aux |= L310_AUX_CTRL_EARLY_BRESP; | |
614 | pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); | |
615 | } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { | |
616 | pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n"); | |
617 | aux &= ~L310_AUX_CTRL_EARLY_BRESP; | |
618 | } | |
619 | } | |
620 | ||
8ef418c7 RK |
621 | if (cortex_a9) { |
622 | u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); | |
623 | u32 acr = get_auxcr(); | |
624 | ||
625 | pr_debug("Cortex-A9 ACR=0x%08x\n", acr); | |
626 | ||
627 | if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO)) | |
628 | pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n"); | |
629 | ||
630 | if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3))) | |
631 | pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n"); | |
632 | ||
633 | if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) { | |
634 | aux |= L310_AUX_CTRL_FULL_LINE_ZERO; | |
635 | pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n"); | |
636 | } | |
637 | } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) { | |
638 | pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n"); | |
639 | aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP); | |
640 | } | |
641 | ||
6b49241a TF |
642 | /* r3p0 or later has power control register */ |
643 | if (rev >= L310_CACHE_ID_RTL_R3P0) | |
644 | l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN | | |
645 | L310_STNDBY_MODE_EN; | |
646 | ||
647 | /* | |
648 | * Always enable non-secure access to the lockdown registers - | |
649 | * we write to them as part of the L2C enable sequence so they | |
650 | * need to be accessible. | |
651 | */ | |
652 | aux |= L310_AUX_CTRL_NS_LOCKDOWN; | |
653 | ||
654 | l2c_enable(base, aux, num_lock); | |
655 | ||
656 | /* Read back resulting AUX_CTRL value as it could have been altered. */ | |
657 | aux = readl_relaxed(base + L2X0_AUX_CTRL); | |
658 | ||
8ef418c7 RK |
659 | if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) { |
660 | u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL); | |
661 | ||
662 | pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n", | |
663 | aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "", | |
664 | aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "", | |
665 | 1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK)); | |
666 | } | |
667 | ||
3a43b581 RK |
668 | /* r3p0 or later has power control register */ |
669 | if (rev >= L310_CACHE_ID_RTL_R3P0) { | |
670 | u32 power_ctrl; | |
671 | ||
3a43b581 RK |
672 | power_ctrl = readl_relaxed(base + L310_POWER_CTRL); |
673 | pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n", | |
674 | power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis", | |
675 | power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis"); | |
676 | } | |
677 | ||
8ef418c7 RK |
678 | if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) { |
679 | set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); | |
680 | cpu_notifier(l2c310_cpu_enable_flz, 0); | |
681 | } | |
4374d649 RK |
682 | } |
683 | ||
75461f5c RK |
684 | static void __init l2c310_fixup(void __iomem *base, u32 cache_id, |
685 | struct outer_cache_fns *fns) | |
686 | { | |
687 | unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; | |
a8875a09 | 688 | const char *errata[8]; |
75461f5c RK |
689 | unsigned n = 0; |
690 | ||
ebd4219f RK |
691 | if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) && |
692 | revision < L310_CACHE_ID_RTL_R2P0 && | |
693 | /* For bcm compatibility */ | |
f777332b | 694 | fns->inv_range == l2c210_inv_range) { |
ebd4219f RK |
695 | fns->inv_range = l2c310_inv_range_erratum; |
696 | fns->flush_range = l2c310_flush_range_erratum; | |
697 | errata[n++] = "588369"; | |
698 | } | |
699 | ||
99ca1772 RK |
700 | if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) && |
701 | revision >= L310_CACHE_ID_RTL_R2P0 && | |
702 | revision < L310_CACHE_ID_RTL_R3P1) { | |
703 | fns->flush_all = l2c310_flush_all_erratum; | |
704 | errata[n++] = "727915"; | |
705 | } | |
706 | ||
a8875a09 RK |
707 | if (revision >= L310_CACHE_ID_RTL_R3P0 && |
708 | revision < L310_CACHE_ID_RTL_R3P2) { | |
6b49241a | 709 | u32 val = l2x0_saved_regs.prefetch_ctrl; |
a8875a09 RK |
710 | /* I don't think bit23 is required here... but iMX6 does so */ |
711 | if (val & (BIT(30) | BIT(23))) { | |
712 | val &= ~(BIT(30) | BIT(23)); | |
6b49241a | 713 | l2x0_saved_regs.prefetch_ctrl = val; |
a8875a09 RK |
714 | errata[n++] = "752271"; |
715 | } | |
716 | } | |
717 | ||
75461f5c RK |
718 | if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && |
719 | revision == L310_CACHE_ID_RTL_R3P0) { | |
720 | sync_reg_offset = L2X0_DUMMY_REG; | |
721 | errata[n++] = "753970"; | |
722 | } | |
723 | ||
724 | if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) | |
725 | errata[n++] = "769419"; | |
726 | ||
727 | if (n) { | |
728 | unsigned i; | |
729 | ||
730 | pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); | |
731 | for (i = 0; i < n; i++) | |
732 | pr_cont(" %s", errata[i]); | |
733 | pr_cont(" enabled\n"); | |
734 | } | |
735 | } | |
736 | ||
8ef418c7 RK |
737 | static void l2c310_disable(void) |
738 | { | |
739 | /* | |
740 | * If full-line-of-zeros is enabled, we must first disable it in the | |
741 | * Cortex-A9 auxiliary control register before disabling the L2 cache. | |
742 | */ | |
743 | if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) | |
744 | set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1))); | |
745 | ||
746 | l2c_disable(); | |
747 | } | |
748 | ||
6b49241a TF |
749 | static void l2c310_resume(void) |
750 | { | |
751 | l2c_resume(); | |
752 | ||
753 | /* Re-enable full-line-of-zeros for Cortex-A9 */ | |
754 | if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO) | |
755 | set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); | |
756 | } | |
757 | ||
75461f5c | 758 | static const struct l2c_init_data l2c310_init_fns __initconst = { |
051334bd | 759 | .type = "L2C-310", |
0493aef4 | 760 | .way_size_0 = SZ_8K, |
75461f5c | 761 | .num_lock = 8, |
4374d649 | 762 | .enable = l2c310_enable, |
75461f5c | 763 | .fixup = l2c310_fixup, |
09a5d180 | 764 | .save = l2c310_save, |
6b49241a | 765 | .configure = l2c310_configure, |
75461f5c | 766 | .outer_cache = { |
f777332b RK |
767 | .inv_range = l2c210_inv_range, |
768 | .clean_range = l2c210_clean_range, | |
769 | .flush_range = l2c210_flush_range, | |
770 | .flush_all = l2c210_flush_all, | |
8ef418c7 | 771 | .disable = l2c310_disable, |
f777332b | 772 | .sync = l2c210_sync, |
09a5d180 | 773 | .resume = l2c310_resume, |
75461f5c RK |
774 | }, |
775 | }; | |
776 | ||
6b49241a TF |
777 | static int __init __l2c_init(const struct l2c_init_data *data, |
778 | u32 aux_val, u32 aux_mask, u32 cache_id) | |
382266ad | 779 | { |
75461f5c | 780 | struct outer_cache_fns fns; |
0493aef4 | 781 | unsigned way_size_bits, ways; |
560be613 | 782 | u32 aux, old_aux; |
382266ad | 783 | |
6b49241a TF |
784 | /* |
785 | * Save the pointer globally so that callbacks which do not receive | |
786 | * context from callers can access the structure. | |
787 | */ | |
788 | l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL); | |
789 | if (!l2x0_data) | |
790 | return -ENOMEM; | |
791 | ||
560be613 RK |
792 | /* |
793 | * Sanity check the aux values. aux_mask is the bits we preserve | |
794 | * from reading the hardware register, and aux_val is the bits we | |
795 | * set. | |
796 | */ | |
797 | if (aux_val & aux_mask) | |
798 | pr_alert("L2C: platform provided aux values permit register corruption.\n"); | |
64039be8 | 799 | |
560be613 | 800 | old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
4082cfa7 SH |
801 | aux &= aux_mask; |
802 | aux |= aux_val; | |
803 | ||
560be613 RK |
804 | if (old_aux != aux) |
805 | pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n", | |
806 | old_aux, aux); | |
807 | ||
64039be8 | 808 | /* Determine the number of ways */ |
6e7aceeb | 809 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
64039be8 | 810 | case L2X0_CACHE_ID_PART_L310: |
314e47b7 RK |
811 | if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16)) |
812 | pr_warn("L2C: DT/platform tries to modify or specify cache size\n"); | |
64039be8 JM |
813 | if (aux & (1 << 16)) |
814 | ways = 16; | |
815 | else | |
816 | ways = 8; | |
64039be8 | 817 | break; |
75461f5c | 818 | |
64039be8 | 819 | case L2X0_CACHE_ID_PART_L210: |
5f47c387 | 820 | case L2X0_CACHE_ID_PART_L220: |
64039be8 | 821 | ways = (aux >> 13) & 0xf; |
64039be8 | 822 | break; |
b8db6b88 GC |
823 | |
824 | case AURORA_CACHE_ID: | |
b8db6b88 GC |
825 | ways = (aux >> 13) & 0xf; |
826 | ways = 2 << ((ways + 1) >> 2); | |
b8db6b88 | 827 | break; |
75461f5c | 828 | |
64039be8 JM |
829 | default: |
830 | /* Assume unknown chips have 8 ways */ | |
831 | ways = 8; | |
64039be8 JM |
832 | break; |
833 | } | |
834 | ||
835 | l2x0_way_mask = (1 << ways) - 1; | |
836 | ||
5ba70372 | 837 | /* |
0493aef4 RK |
838 | * way_size_0 is the size that a way_size value of zero would be |
839 | * given the calculation: way_size = way_size_0 << way_size_bits. | |
840 | * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k, | |
841 | * then way_size_0 would be 8k. | |
842 | * | |
843 | * L2 cache size = number of ways * way size. | |
5ba70372 | 844 | */ |
1a5a954c RK |
845 | way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >> |
846 | L2C_AUX_CTRL_WAY_SIZE_SHIFT; | |
0493aef4 | 847 | l2x0_size = ways * (data->way_size_0 << way_size_bits); |
5ba70372 | 848 | |
75461f5c | 849 | fns = data->outer_cache; |
8abd259f | 850 | fns.write_sec = outer_cache.write_sec; |
c6d1a2d0 | 851 | fns.configure = outer_cache.configure; |
75461f5c RK |
852 | if (data->fixup) |
853 | data->fixup(l2x0_base, cache_id, &fns); | |
854 | ||
48371cd3 | 855 | /* |
3b8bad57 RK |
856 | * Check if l2x0 controller is already enabled. If we are booting |
857 | * in non-secure mode accessing the below registers will fault. | |
48371cd3 | 858 | */ |
3b8bad57 RK |
859 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) |
860 | data->enable(l2x0_base, aux, data->num_lock); | |
382266ad | 861 | |
ddf7d79b | 862 | outer_cache = fns; |
9d4876f0 | 863 | |
ddf7d79b RK |
864 | /* |
865 | * It is strange to save the register state before initialisation, | |
866 | * but hey, this is what the DT implementations decided to do. | |
867 | */ | |
868 | if (data->save) | |
869 | data->save(l2x0_base); | |
9d4876f0 | 870 | |
ddf7d79b RK |
871 | /* Re-read it in case some bits are reserved. */ |
872 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); | |
382266ad | 873 | |
cdef8689 | 874 | pr_info("%s cache controller enabled, %d ways, %d kB\n", |
051334bd | 875 | data->type, ways, l2x0_size >> 10); |
cdef8689 | 876 | pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", |
051334bd | 877 | data->type, cache_id, aux); |
6b49241a TF |
878 | |
879 | return 0; | |
382266ad | 880 | } |
8c369264 | 881 | |
96054b0a RK |
882 | void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) |
883 | { | |
75461f5c | 884 | const struct l2c_init_data *data; |
96054b0a RK |
885 | u32 cache_id; |
886 | ||
887 | l2x0_base = base; | |
888 | ||
889 | cache_id = readl_relaxed(base + L2X0_CACHE_ID); | |
890 | ||
75461f5c RK |
891 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
892 | default: | |
6a28cf59 RK |
893 | case L2X0_CACHE_ID_PART_L210: |
894 | data = &l2c210_data; | |
895 | break; | |
896 | ||
733c6bba RK |
897 | case L2X0_CACHE_ID_PART_L220: |
898 | data = &l2c220_data; | |
899 | break; | |
900 | ||
75461f5c RK |
901 | case L2X0_CACHE_ID_PART_L310: |
902 | data = &l2c310_init_fns; | |
903 | break; | |
904 | } | |
905 | ||
6b49241a TF |
906 | /* Read back current (default) hardware configuration */ |
907 | if (data->save) | |
908 | data->save(l2x0_base); | |
909 | ||
75461f5c | 910 | __l2c_init(data, aux_val, aux_mask, cache_id); |
96054b0a RK |
911 | } |
912 | ||
8c369264 | 913 | #ifdef CONFIG_OF |
b8db6b88 GC |
914 | static int l2_wt_override; |
915 | ||
96054b0a RK |
916 | /* Aurora don't have the cache ID register available, so we have to |
917 | * pass it though the device tree */ | |
918 | static u32 cache_id_part_number_from_dt; | |
919 | ||
f3354ab6 LW |
920 | /** |
921 | * l2x0_cache_size_of_parse() - read cache size parameters from DT | |
922 | * @np: the device tree node for the l2 cache | |
923 | * @aux_val: pointer to machine-supplied auxilary register value, to | |
924 | * be augmented by the call (bits to be set to 1) | |
925 | * @aux_mask: pointer to machine-supplied auxilary register mask, to | |
926 | * be augmented by the call (bits to be set to 0) | |
927 | * @associativity: variable to return the calculated associativity in | |
928 | * @max_way_size: the maximum size in bytes for the cache ways | |
929 | */ | |
d0b92845 | 930 | static int __init l2x0_cache_size_of_parse(const struct device_node *np, |
f3354ab6 LW |
931 | u32 *aux_val, u32 *aux_mask, |
932 | u32 *associativity, | |
933 | u32 max_way_size) | |
934 | { | |
935 | u32 mask = 0, val = 0; | |
936 | u32 cache_size = 0, sets = 0; | |
937 | u32 way_size_bits = 1; | |
938 | u32 way_size = 0; | |
939 | u32 block_size = 0; | |
940 | u32 line_size = 0; | |
941 | ||
942 | of_property_read_u32(np, "cache-size", &cache_size); | |
943 | of_property_read_u32(np, "cache-sets", &sets); | |
944 | of_property_read_u32(np, "cache-block-size", &block_size); | |
945 | of_property_read_u32(np, "cache-line-size", &line_size); | |
946 | ||
947 | if (!cache_size || !sets) | |
d0b92845 | 948 | return -ENODEV; |
f3354ab6 LW |
949 | |
950 | /* All these l2 caches have the same line = block size actually */ | |
951 | if (!line_size) { | |
952 | if (block_size) { | |
f2c22731 | 953 | /* If linesize is not given, it is equal to blocksize */ |
f3354ab6 LW |
954 | line_size = block_size; |
955 | } else { | |
956 | /* Fall back to known size */ | |
957 | pr_warn("L2C OF: no cache block/line size given: " | |
958 | "falling back to default size %d bytes\n", | |
959 | CACHE_LINE_SIZE); | |
960 | line_size = CACHE_LINE_SIZE; | |
961 | } | |
962 | } | |
963 | ||
964 | if (line_size != CACHE_LINE_SIZE) | |
965 | pr_warn("L2C OF: DT supplied line size %d bytes does " | |
966 | "not match hardware line size of %d bytes\n", | |
967 | line_size, | |
968 | CACHE_LINE_SIZE); | |
969 | ||
970 | /* | |
971 | * Since: | |
972 | * set size = cache size / sets | |
973 | * ways = cache size / (sets * line size) | |
974 | * way size = cache size / (cache size / (sets * line size)) | |
975 | * way size = sets * line size | |
976 | * associativity = ways = cache size / way size | |
977 | */ | |
978 | way_size = sets * line_size; | |
979 | *associativity = cache_size / way_size; | |
980 | ||
981 | if (way_size > max_way_size) { | |
982 | pr_err("L2C OF: set size %dKB is too large\n", way_size); | |
d0b92845 | 983 | return -EINVAL; |
f3354ab6 LW |
984 | } |
985 | ||
986 | pr_info("L2C OF: override cache size: %d bytes (%dKB)\n", | |
987 | cache_size, cache_size >> 10); | |
988 | pr_info("L2C OF: override line size: %d bytes\n", line_size); | |
989 | pr_info("L2C OF: override way size: %d bytes (%dKB)\n", | |
990 | way_size, way_size >> 10); | |
991 | pr_info("L2C OF: override associativity: %d\n", *associativity); | |
992 | ||
993 | /* | |
994 | * Calculates the bits 17:19 to set for way size: | |
995 | * 512KB -> 6, 256KB -> 5, ... 16KB -> 1 | |
996 | */ | |
997 | way_size_bits = ilog2(way_size >> 10) - 3; | |
998 | if (way_size_bits < 1 || way_size_bits > 6) { | |
999 | pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n", | |
1000 | way_size); | |
d0b92845 | 1001 | return -EINVAL; |
f3354ab6 LW |
1002 | } |
1003 | ||
1004 | mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; | |
1005 | val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT); | |
1006 | ||
1007 | *aux_val &= ~mask; | |
1008 | *aux_val |= val; | |
1009 | *aux_mask &= ~mask; | |
d0b92845 FE |
1010 | |
1011 | return 0; | |
f3354ab6 LW |
1012 | } |
1013 | ||
da3627fb RK |
1014 | static void __init l2x0_of_parse(const struct device_node *np, |
1015 | u32 *aux_val, u32 *aux_mask) | |
1016 | { | |
1017 | u32 data[2] = { 0, 0 }; | |
1018 | u32 tag = 0; | |
1019 | u32 dirty = 0; | |
1020 | u32 val = 0, mask = 0; | |
f3354ab6 | 1021 | u32 assoc; |
d0b92845 | 1022 | int ret; |
da3627fb RK |
1023 | |
1024 | of_property_read_u32(np, "arm,tag-latency", &tag); | |
1025 | if (tag) { | |
1026 | mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; | |
1027 | val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; | |
1028 | } | |
1029 | ||
1030 | of_property_read_u32_array(np, "arm,data-latency", | |
1031 | data, ARRAY_SIZE(data)); | |
1032 | if (data[0] && data[1]) { | |
1033 | mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | | |
1034 | L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; | |
1035 | val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | | |
1036 | ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); | |
1037 | } | |
1038 | ||
1039 | of_property_read_u32(np, "arm,dirty-latency", &dirty); | |
1040 | if (dirty) { | |
1041 | mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; | |
1042 | val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; | |
1043 | } | |
1044 | ||
d0b92845 FE |
1045 | ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); |
1046 | if (ret) | |
1047 | return; | |
1048 | ||
f3354ab6 LW |
1049 | if (assoc > 8) { |
1050 | pr_err("l2x0 of: cache setting yield too high associativity\n"); | |
1051 | pr_err("l2x0 of: %d calculated, max 8\n", assoc); | |
1052 | } else { | |
1053 | mask |= L2X0_AUX_CTRL_ASSOC_MASK; | |
1054 | val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT); | |
1055 | } | |
1056 | ||
da3627fb RK |
1057 | *aux_val &= ~mask; |
1058 | *aux_val |= val; | |
1059 | *aux_mask &= ~mask; | |
1060 | } | |
1061 | ||
6a28cf59 | 1062 | static const struct l2c_init_data of_l2c210_data __initconst = { |
051334bd | 1063 | .type = "L2C-210", |
0493aef4 | 1064 | .way_size_0 = SZ_8K, |
6a28cf59 RK |
1065 | .num_lock = 1, |
1066 | .of_parse = l2x0_of_parse, | |
1067 | .enable = l2c_enable, | |
ddf7d79b | 1068 | .save = l2c_save, |
50beefde | 1069 | .configure = l2c_configure, |
6a28cf59 RK |
1070 | .outer_cache = { |
1071 | .inv_range = l2c210_inv_range, | |
1072 | .clean_range = l2c210_clean_range, | |
1073 | .flush_range = l2c210_flush_range, | |
1074 | .flush_all = l2c210_flush_all, | |
1075 | .disable = l2c_disable, | |
1076 | .sync = l2c210_sync, | |
6b49241a | 1077 | .resume = l2c_resume, |
6a28cf59 RK |
1078 | }, |
1079 | }; | |
1080 | ||
733c6bba | 1081 | static const struct l2c_init_data of_l2c220_data __initconst = { |
051334bd | 1082 | .type = "L2C-220", |
0493aef4 | 1083 | .way_size_0 = SZ_8K, |
733c6bba | 1084 | .num_lock = 1, |
da3627fb | 1085 | .of_parse = l2x0_of_parse, |
a4b041a0 | 1086 | .enable = l2c220_enable, |
ddf7d79b | 1087 | .save = l2c_save, |
50beefde | 1088 | .configure = l2c_configure, |
da3627fb | 1089 | .outer_cache = { |
733c6bba RK |
1090 | .inv_range = l2c220_inv_range, |
1091 | .clean_range = l2c220_clean_range, | |
1092 | .flush_range = l2c220_flush_range, | |
1093 | .flush_all = l2c220_flush_all, | |
1094 | .disable = l2c_disable, | |
1095 | .sync = l2c220_sync, | |
6b49241a | 1096 | .resume = l2c_resume, |
da3627fb RK |
1097 | }, |
1098 | }; | |
1099 | ||
f777332b RK |
1100 | static void __init l2c310_of_parse(const struct device_node *np, |
1101 | u32 *aux_val, u32 *aux_mask) | |
da3627fb RK |
1102 | { |
1103 | u32 data[3] = { 0, 0, 0 }; | |
1104 | u32 tag[3] = { 0, 0, 0 }; | |
1105 | u32 filter[2] = { 0, 0 }; | |
f3354ab6 | 1106 | u32 assoc; |
cf0681ca TF |
1107 | u32 prefetch; |
1108 | u32 val; | |
d0b92845 | 1109 | int ret; |
da3627fb RK |
1110 | |
1111 | of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); | |
1112 | if (tag[0] && tag[1] && tag[2]) | |
6b49241a | 1113 | l2x0_saved_regs.tag_latency = |
1a5a954c RK |
1114 | L310_LATENCY_CTRL_RD(tag[0] - 1) | |
1115 | L310_LATENCY_CTRL_WR(tag[1] - 1) | | |
6b49241a | 1116 | L310_LATENCY_CTRL_SETUP(tag[2] - 1); |
da3627fb RK |
1117 | |
1118 | of_property_read_u32_array(np, "arm,data-latency", | |
1119 | data, ARRAY_SIZE(data)); | |
1120 | if (data[0] && data[1] && data[2]) | |
6b49241a | 1121 | l2x0_saved_regs.data_latency = |
1a5a954c RK |
1122 | L310_LATENCY_CTRL_RD(data[0] - 1) | |
1123 | L310_LATENCY_CTRL_WR(data[1] - 1) | | |
6b49241a | 1124 | L310_LATENCY_CTRL_SETUP(data[2] - 1); |
da3627fb RK |
1125 | |
1126 | of_property_read_u32_array(np, "arm,filter-ranges", | |
1127 | filter, ARRAY_SIZE(filter)); | |
1128 | if (filter[1]) { | |
6b49241a TF |
1129 | l2x0_saved_regs.filter_end = |
1130 | ALIGN(filter[0] + filter[1], SZ_1M); | |
1131 | l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1)) | |
1132 | | L310_ADDR_FILTER_EN; | |
da3627fb | 1133 | } |
f3354ab6 | 1134 | |
d0b92845 | 1135 | ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); |
5c95ed47 FG |
1136 | if (!ret) { |
1137 | switch (assoc) { | |
1138 | case 16: | |
1139 | *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1140 | *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16; | |
1141 | *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1142 | break; | |
1143 | case 8: | |
1144 | *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1145 | *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; | |
1146 | break; | |
1147 | default: | |
1148 | pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n", | |
1149 | assoc); | |
1150 | break; | |
1151 | } | |
f3354ab6 | 1152 | } |
cf0681ca TF |
1153 | |
1154 | prefetch = l2x0_saved_regs.prefetch_ctrl; | |
1155 | ||
1156 | ret = of_property_read_u32(np, "arm,double-linefill", &val); | |
1157 | if (ret == 0) { | |
1158 | if (val) | |
1159 | prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL; | |
1160 | else | |
1161 | prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL; | |
1162 | } else if (ret != -EINVAL) { | |
1163 | pr_err("L2C-310 OF arm,double-linefill property value is missing\n"); | |
1164 | } | |
1165 | ||
1166 | ret = of_property_read_u32(np, "arm,double-linefill-incr", &val); | |
1167 | if (ret == 0) { | |
1168 | if (val) | |
1169 | prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; | |
1170 | else | |
1171 | prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; | |
1172 | } else if (ret != -EINVAL) { | |
1173 | pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n"); | |
1174 | } | |
1175 | ||
1176 | ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val); | |
1177 | if (ret == 0) { | |
1178 | if (!val) | |
1179 | prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP; | |
1180 | else | |
1181 | prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP; | |
1182 | } else if (ret != -EINVAL) { | |
1183 | pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n"); | |
1184 | } | |
1185 | ||
1186 | ret = of_property_read_u32(np, "arm,prefetch-drop", &val); | |
1187 | if (ret == 0) { | |
1188 | if (val) | |
1189 | prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP; | |
1190 | else | |
1191 | prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP; | |
1192 | } else if (ret != -EINVAL) { | |
1193 | pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n"); | |
1194 | } | |
1195 | ||
1196 | ret = of_property_read_u32(np, "arm,prefetch-offset", &val); | |
1197 | if (ret == 0) { | |
1198 | prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK; | |
1199 | prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK; | |
1200 | } else if (ret != -EINVAL) { | |
1201 | pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n"); | |
1202 | } | |
1203 | ||
1204 | l2x0_saved_regs.prefetch_ctrl = prefetch; | |
da3627fb RK |
1205 | } |
1206 | ||
f777332b | 1207 | static const struct l2c_init_data of_l2c310_data __initconst = { |
051334bd | 1208 | .type = "L2C-310", |
0493aef4 | 1209 | .way_size_0 = SZ_8K, |
3b8bad57 | 1210 | .num_lock = 8, |
f777332b | 1211 | .of_parse = l2c310_of_parse, |
4374d649 | 1212 | .enable = l2c310_enable, |
75461f5c | 1213 | .fixup = l2c310_fixup, |
09a5d180 | 1214 | .save = l2c310_save, |
6b49241a | 1215 | .configure = l2c310_configure, |
da3627fb | 1216 | .outer_cache = { |
f777332b RK |
1217 | .inv_range = l2c210_inv_range, |
1218 | .clean_range = l2c210_clean_range, | |
1219 | .flush_range = l2c210_flush_range, | |
1220 | .flush_all = l2c210_flush_all, | |
8ef418c7 | 1221 | .disable = l2c310_disable, |
f777332b | 1222 | .sync = l2c210_sync, |
09a5d180 | 1223 | .resume = l2c310_resume, |
da3627fb RK |
1224 | }, |
1225 | }; | |
1226 | ||
98ea2dba TP |
1227 | /* |
1228 | * This is a variant of the of_l2c310_data with .sync set to | |
1229 | * NULL. Outer sync operations are not needed when the system is I/O | |
1230 | * coherent, and potentially harmful in certain situations (PCIe/PL310 | |
1231 | * deadlock on Armada 375/38x due to hardware I/O coherency). The | |
1232 | * other operations are kept because they are infrequent (therefore do | |
1233 | * not cause the deadlock in practice) and needed for secondary CPU | |
1234 | * boot and other power management activities. | |
1235 | */ | |
1236 | static const struct l2c_init_data of_l2c310_coherent_data __initconst = { | |
1237 | .type = "L2C-310 Coherent", | |
1238 | .way_size_0 = SZ_8K, | |
1239 | .num_lock = 8, | |
1240 | .of_parse = l2c310_of_parse, | |
1241 | .enable = l2c310_enable, | |
1242 | .fixup = l2c310_fixup, | |
1243 | .save = l2c310_save, | |
6b49241a | 1244 | .configure = l2c310_configure, |
98ea2dba TP |
1245 | .outer_cache = { |
1246 | .inv_range = l2c210_inv_range, | |
1247 | .clean_range = l2c210_clean_range, | |
1248 | .flush_range = l2c210_flush_range, | |
1249 | .flush_all = l2c210_flush_all, | |
1250 | .disable = l2c310_disable, | |
1251 | .resume = l2c310_resume, | |
1252 | }, | |
1253 | }; | |
1254 | ||
b8db6b88 GC |
1255 | /* |
1256 | * Note that the end addresses passed to Linux primitives are | |
1257 | * noninclusive, while the hardware cache range operations use | |
1258 | * inclusive start and end addresses. | |
1259 | */ | |
1d889679 | 1260 | static unsigned long aurora_range_end(unsigned long start, unsigned long end) |
b8db6b88 GC |
1261 | { |
1262 | /* | |
1263 | * Limit the number of cache lines processed at once, | |
1264 | * since cache range operations stall the CPU pipeline | |
1265 | * until completion. | |
1266 | */ | |
1267 | if (end > start + MAX_RANGE_SIZE) | |
1268 | end = start + MAX_RANGE_SIZE; | |
1269 | ||
1270 | /* | |
1271 | * Cache range operations can't straddle a page boundary. | |
1272 | */ | |
1273 | if (end > PAGE_ALIGN(start+1)) | |
1274 | end = PAGE_ALIGN(start+1); | |
1275 | ||
1276 | return end; | |
1277 | } | |
1278 | ||
b8db6b88 | 1279 | static void aurora_pa_range(unsigned long start, unsigned long end, |
1d889679 | 1280 | unsigned long offset) |
b8db6b88 | 1281 | { |
20e783e3 | 1282 | void __iomem *base = l2x0_base; |
1d889679 | 1283 | unsigned long range_end; |
b8db6b88 GC |
1284 | unsigned long flags; |
1285 | ||
b8db6b88 GC |
1286 | /* |
1287 | * round start and end adresses up to cache line size | |
1288 | */ | |
1289 | start &= ~(CACHE_LINE_SIZE - 1); | |
1290 | end = ALIGN(end, CACHE_LINE_SIZE); | |
1291 | ||
1292 | /* | |
1d889679 | 1293 | * perform operation on all full cache lines between 'start' and 'end' |
b8db6b88 GC |
1294 | */ |
1295 | while (start < end) { | |
1d889679 AB |
1296 | range_end = aurora_range_end(start, end); |
1297 | ||
1298 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
1299 | writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG); | |
1300 | writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset); | |
1301 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
1302 | ||
1303 | writel_relaxed(0, base + AURORA_SYNC_REG); | |
b8db6b88 GC |
1304 | start = range_end; |
1305 | } | |
1306 | } | |
1d889679 AB |
1307 | static void aurora_inv_range(unsigned long start, unsigned long end) |
1308 | { | |
1309 | aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); | |
1310 | } | |
b8db6b88 GC |
1311 | |
1312 | static void aurora_clean_range(unsigned long start, unsigned long end) | |
1313 | { | |
1314 | /* | |
1315 | * If L2 is forced to WT, the L2 will always be clean and we | |
1316 | * don't need to do anything here. | |
1317 | */ | |
1d889679 AB |
1318 | if (!l2_wt_override) |
1319 | aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG); | |
b8db6b88 GC |
1320 | } |
1321 | ||
1322 | static void aurora_flush_range(unsigned long start, unsigned long end) | |
1323 | { | |
1d889679 AB |
1324 | if (l2_wt_override) |
1325 | aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); | |
1326 | else | |
1327 | aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG); | |
b8db6b88 GC |
1328 | } |
1329 | ||
20e783e3 | 1330 | static void aurora_flush_all(void) |
da3627fb | 1331 | { |
20e783e3 AB |
1332 | void __iomem *base = l2x0_base; |
1333 | unsigned long flags; | |
1334 | ||
1335 | /* clean all ways */ | |
1336 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
1337 | __l2c_op_way(base + L2X0_CLEAN_INV_WAY); | |
1338 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
1339 | ||
1340 | writel_relaxed(0, base + AURORA_SYNC_REG); | |
da3627fb RK |
1341 | } |
1342 | ||
20e783e3 AB |
1343 | static void aurora_cache_sync(void) |
1344 | { | |
1345 | writel_relaxed(0, l2x0_base + AURORA_SYNC_REG); | |
1346 | } | |
1347 | ||
1348 | static void aurora_disable(void) | |
da3627fb | 1349 | { |
09a5d180 | 1350 | void __iomem *base = l2x0_base; |
20e783e3 | 1351 | unsigned long flags; |
09a5d180 | 1352 | |
20e783e3 AB |
1353 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
1354 | __l2c_op_way(base + L2X0_CLEAN_INV_WAY); | |
1355 | writel_relaxed(0, base + AURORA_SYNC_REG); | |
1356 | l2c_write_sec(0, base, L2X0_CTRL); | |
1357 | dsb(st); | |
1358 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); | |
1359 | } | |
1360 | ||
da3627fb RK |
1361 | static void aurora_save(void __iomem *base) |
1362 | { | |
1363 | l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); | |
1364 | l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); | |
da3627fb RK |
1365 | } |
1366 | ||
40266d6f RK |
1367 | /* |
1368 | * For Aurora cache in no outer mode, enable via the CP15 coprocessor | |
1369 | * broadcasting of cache commands to L2. | |
1370 | */ | |
1371 | static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, | |
1372 | unsigned num_lock) | |
da3627fb | 1373 | { |
40266d6f RK |
1374 | u32 u; |
1375 | ||
1376 | asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); | |
da3627fb | 1377 | u |= AURORA_CTRL_FW; /* Set the FW bit */ |
40266d6f RK |
1378 | asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); |
1379 | ||
da3627fb | 1380 | isb(); |
40266d6f RK |
1381 | |
1382 | l2c_enable(base, aux, num_lock); | |
da3627fb RK |
1383 | } |
1384 | ||
75461f5c RK |
1385 | static void __init aurora_fixup(void __iomem *base, u32 cache_id, |
1386 | struct outer_cache_fns *fns) | |
1387 | { | |
1388 | sync_reg_offset = AURORA_SYNC_REG; | |
1389 | } | |
1390 | ||
da3627fb RK |
1391 | static void __init aurora_of_parse(const struct device_node *np, |
1392 | u32 *aux_val, u32 *aux_mask) | |
1393 | { | |
1394 | u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; | |
1395 | u32 mask = AURORA_ACR_REPLACEMENT_MASK; | |
1396 | ||
1397 | of_property_read_u32(np, "cache-id-part", | |
1398 | &cache_id_part_number_from_dt); | |
1399 | ||
1400 | /* Determine and save the write policy */ | |
1401 | l2_wt_override = of_property_read_bool(np, "wt-override"); | |
1402 | ||
1403 | if (l2_wt_override) { | |
1404 | val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; | |
1405 | mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; | |
1406 | } | |
1407 | ||
1408 | *aux_val &= ~mask; | |
1409 | *aux_val |= val; | |
1410 | *aux_mask &= ~mask; | |
1411 | } | |
1412 | ||
1413 | static const struct l2c_init_data of_aurora_with_outer_data __initconst = { | |
051334bd | 1414 | .type = "Aurora", |
0493aef4 | 1415 | .way_size_0 = SZ_4K, |
3b8bad57 | 1416 | .num_lock = 4, |
da3627fb | 1417 | .of_parse = aurora_of_parse, |
3b8bad57 | 1418 | .enable = l2c_enable, |
75461f5c | 1419 | .fixup = aurora_fixup, |
da3627fb | 1420 | .save = aurora_save, |
50beefde | 1421 | .configure = l2c_configure, |
da3627fb RK |
1422 | .outer_cache = { |
1423 | .inv_range = aurora_inv_range, | |
1424 | .clean_range = aurora_clean_range, | |
1425 | .flush_range = aurora_flush_range, | |
20e783e3 AB |
1426 | .flush_all = aurora_flush_all, |
1427 | .disable = aurora_disable, | |
1428 | .sync = aurora_cache_sync, | |
6b49241a | 1429 | .resume = l2c_resume, |
da3627fb RK |
1430 | }, |
1431 | }; | |
1432 | ||
1433 | static const struct l2c_init_data of_aurora_no_outer_data __initconst = { | |
051334bd | 1434 | .type = "Aurora", |
0493aef4 | 1435 | .way_size_0 = SZ_4K, |
3b8bad57 | 1436 | .num_lock = 4, |
da3627fb | 1437 | .of_parse = aurora_of_parse, |
40266d6f | 1438 | .enable = aurora_enable_no_outer, |
75461f5c | 1439 | .fixup = aurora_fixup, |
da3627fb | 1440 | .save = aurora_save, |
50beefde | 1441 | .configure = l2c_configure, |
da3627fb | 1442 | .outer_cache = { |
6b49241a | 1443 | .resume = l2c_resume, |
da3627fb RK |
1444 | }, |
1445 | }; | |
1446 | ||
3b656fed CD |
1447 | /* |
1448 | * For certain Broadcom SoCs, depending on the address range, different offsets | |
1449 | * need to be added to the address before passing it to L2 for | |
1450 | * invalidation/clean/flush | |
1451 | * | |
1452 | * Section Address Range Offset EMI | |
1453 | * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC | |
1454 | * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS | |
1455 | * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC | |
1456 | * | |
1457 | * When the start and end addresses have crossed two different sections, we | |
1458 | * need to break the L2 operation into two, each within its own section. | |
1459 | * For example, if we need to invalidate addresses starts at 0xBFFF0000 and | |
1460 | * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) | |
1461 | * 0xC0000000 - 0xC0001000 | |
1462 | * | |
1463 | * Note 1: | |
1464 | * By breaking a single L2 operation into two, we may potentially suffer some | |
1465 | * performance hit, but keep in mind the cross section case is very rare | |
1466 | * | |
1467 | * Note 2: | |
1468 | * We do not need to handle the case when the start address is in | |
1469 | * Section 1 and the end address is in Section 3, since it is not a valid use | |
1470 | * case | |
1471 | * | |
1472 | * Note 3: | |
1473 | * Section 1 in practical terms can no longer be used on rev A2. Because of | |
1474 | * that the code does not need to handle section 1 at all. | |
1475 | * | |
1476 | */ | |
1477 | #define BCM_SYS_EMI_START_ADDR 0x40000000UL | |
1478 | #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL | |
1479 | ||
1480 | #define BCM_SYS_EMI_OFFSET 0x40000000UL | |
1481 | #define BCM_VC_EMI_OFFSET 0x80000000UL | |
1482 | ||
1483 | static inline int bcm_addr_is_sys_emi(unsigned long addr) | |
1484 | { | |
1485 | return (addr >= BCM_SYS_EMI_START_ADDR) && | |
1486 | (addr < BCM_VC_EMI_SEC3_START_ADDR); | |
1487 | } | |
1488 | ||
1489 | static inline unsigned long bcm_l2_phys_addr(unsigned long addr) | |
1490 | { | |
1491 | if (bcm_addr_is_sys_emi(addr)) | |
1492 | return addr + BCM_SYS_EMI_OFFSET; | |
1493 | else | |
1494 | return addr + BCM_VC_EMI_OFFSET; | |
1495 | } | |
1496 | ||
1497 | static void bcm_inv_range(unsigned long start, unsigned long end) | |
1498 | { | |
1499 | unsigned long new_start, new_end; | |
1500 | ||
1501 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1502 | ||
1503 | if (unlikely(end <= start)) | |
1504 | return; | |
1505 | ||
1506 | new_start = bcm_l2_phys_addr(start); | |
1507 | new_end = bcm_l2_phys_addr(end); | |
1508 | ||
1509 | /* normal case, no cross section between start and end */ | |
1510 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
90811148 | 1511 | l2c210_inv_range(new_start, new_end); |
3b656fed CD |
1512 | return; |
1513 | } | |
1514 | ||
1515 | /* They cross sections, so it can only be a cross from section | |
1516 | * 2 to section 3 | |
1517 | */ | |
90811148 | 1518 | l2c210_inv_range(new_start, |
3b656fed | 1519 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); |
90811148 | 1520 | l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), |
3b656fed CD |
1521 | new_end); |
1522 | } | |
1523 | ||
1524 | static void bcm_clean_range(unsigned long start, unsigned long end) | |
1525 | { | |
1526 | unsigned long new_start, new_end; | |
1527 | ||
1528 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1529 | ||
1530 | if (unlikely(end <= start)) | |
1531 | return; | |
1532 | ||
3b656fed CD |
1533 | new_start = bcm_l2_phys_addr(start); |
1534 | new_end = bcm_l2_phys_addr(end); | |
1535 | ||
1536 | /* normal case, no cross section between start and end */ | |
1537 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
90811148 | 1538 | l2c210_clean_range(new_start, new_end); |
3b656fed CD |
1539 | return; |
1540 | } | |
1541 | ||
1542 | /* They cross sections, so it can only be a cross from section | |
1543 | * 2 to section 3 | |
1544 | */ | |
90811148 | 1545 | l2c210_clean_range(new_start, |
3b656fed | 1546 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); |
90811148 | 1547 | l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), |
3b656fed CD |
1548 | new_end); |
1549 | } | |
1550 | ||
1551 | static void bcm_flush_range(unsigned long start, unsigned long end) | |
1552 | { | |
1553 | unsigned long new_start, new_end; | |
1554 | ||
1555 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1556 | ||
1557 | if (unlikely(end <= start)) | |
1558 | return; | |
1559 | ||
1560 | if ((end - start) >= l2x0_size) { | |
90811148 | 1561 | outer_cache.flush_all(); |
3b656fed CD |
1562 | return; |
1563 | } | |
1564 | ||
1565 | new_start = bcm_l2_phys_addr(start); | |
1566 | new_end = bcm_l2_phys_addr(end); | |
1567 | ||
1568 | /* normal case, no cross section between start and end */ | |
1569 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
90811148 | 1570 | l2c210_flush_range(new_start, new_end); |
3b656fed CD |
1571 | return; |
1572 | } | |
1573 | ||
1574 | /* They cross sections, so it can only be a cross from section | |
1575 | * 2 to section 3 | |
1576 | */ | |
90811148 | 1577 | l2c210_flush_range(new_start, |
3b656fed | 1578 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); |
90811148 | 1579 | l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), |
3b656fed CD |
1580 | new_end); |
1581 | } | |
1582 | ||
90811148 | 1583 | /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */ |
da3627fb | 1584 | static const struct l2c_init_data of_bcm_l2x0_data __initconst = { |
051334bd | 1585 | .type = "BCM-L2C-310", |
0493aef4 | 1586 | .way_size_0 = SZ_8K, |
3b8bad57 | 1587 | .num_lock = 8, |
f777332b | 1588 | .of_parse = l2c310_of_parse, |
4374d649 | 1589 | .enable = l2c310_enable, |
09a5d180 | 1590 | .save = l2c310_save, |
6b49241a | 1591 | .configure = l2c310_configure, |
da3627fb RK |
1592 | .outer_cache = { |
1593 | .inv_range = bcm_inv_range, | |
1594 | .clean_range = bcm_clean_range, | |
1595 | .flush_range = bcm_flush_range, | |
f777332b | 1596 | .flush_all = l2c210_flush_all, |
8ef418c7 | 1597 | .disable = l2c310_disable, |
f777332b | 1598 | .sync = l2c210_sync, |
09a5d180 | 1599 | .resume = l2c310_resume, |
da3627fb RK |
1600 | }, |
1601 | }; | |
b8db6b88 | 1602 | |
9846dfc9 | 1603 | static void __init tauros3_save(void __iomem *base) |
e68f31f4 | 1604 | { |
ddf7d79b RK |
1605 | l2c_save(base); |
1606 | ||
e68f31f4 | 1607 | l2x0_saved_regs.aux2_ctrl = |
9846dfc9 | 1608 | readl_relaxed(base + TAUROS3_AUX2_CTRL); |
e68f31f4 | 1609 | l2x0_saved_regs.prefetch_ctrl = |
1a5a954c | 1610 | readl_relaxed(base + L310_PREFETCH_CTRL); |
e68f31f4 SH |
1611 | } |
1612 | ||
6b49241a | 1613 | static void tauros3_configure(void __iomem *base) |
e68f31f4 | 1614 | { |
50beefde | 1615 | l2c_configure(base); |
6b49241a TF |
1616 | writel_relaxed(l2x0_saved_regs.aux2_ctrl, |
1617 | base + TAUROS3_AUX2_CTRL); | |
1618 | writel_relaxed(l2x0_saved_regs.prefetch_ctrl, | |
1619 | base + L310_PREFETCH_CTRL); | |
e68f31f4 SH |
1620 | } |
1621 | ||
c02642bc | 1622 | static const struct l2c_init_data of_tauros3_data __initconst = { |
051334bd | 1623 | .type = "Tauros3", |
0493aef4 | 1624 | .way_size_0 = SZ_8K, |
3b8bad57 RK |
1625 | .num_lock = 8, |
1626 | .enable = l2c_enable, | |
e68f31f4 | 1627 | .save = tauros3_save, |
6b49241a | 1628 | .configure = tauros3_configure, |
e68f31f4 SH |
1629 | /* Tauros3 broadcasts L1 cache operations to L2 */ |
1630 | .outer_cache = { | |
6b49241a | 1631 | .resume = l2c_resume, |
e68f31f4 SH |
1632 | }, |
1633 | }; | |
1634 | ||
a65bb925 | 1635 | #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } |
8c369264 | 1636 | static const struct of_device_id l2x0_ids[] __initconst = { |
6a28cf59 | 1637 | L2C_ID("arm,l210-cache", of_l2c210_data), |
733c6bba | 1638 | L2C_ID("arm,l220-cache", of_l2c220_data), |
f777332b | 1639 | L2C_ID("arm,pl310-cache", of_l2c310_data), |
c02642bc RK |
1640 | L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), |
1641 | L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), | |
1642 | L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), | |
1643 | L2C_ID("marvell,tauros3-cache", of_tauros3_data), | |
a65bb925 | 1644 | /* Deprecated IDs */ |
c02642bc | 1645 | L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), |
8c369264 RH |
1646 | {} |
1647 | }; | |
1648 | ||
3e175ca4 | 1649 | int __init l2x0_of_init(u32 aux_val, u32 aux_mask) |
8c369264 | 1650 | { |
c02642bc | 1651 | const struct l2c_init_data *data; |
8c369264 | 1652 | struct device_node *np; |
91c2ebb9 | 1653 | struct resource res; |
560be613 | 1654 | u32 cache_id, old_aux; |
1b4bd608 | 1655 | u32 cache_level = 2; |
8c369264 RH |
1656 | |
1657 | np = of_find_matching_node(NULL, l2x0_ids); | |
1658 | if (!np) | |
1659 | return -ENODEV; | |
91c2ebb9 BS |
1660 | |
1661 | if (of_address_to_resource(np, 0, &res)) | |
1662 | return -ENODEV; | |
1663 | ||
1664 | l2x0_base = ioremap(res.start, resource_size(&res)); | |
8c369264 RH |
1665 | if (!l2x0_base) |
1666 | return -ENOMEM; | |
1667 | ||
91c2ebb9 BS |
1668 | l2x0_saved_regs.phy_base = res.start; |
1669 | ||
1670 | data = of_match_node(l2x0_ids, np)->data; | |
1671 | ||
98ea2dba TP |
1672 | if (of_device_is_compatible(np, "arm,pl310-cache") && |
1673 | of_property_read_bool(np, "arm,io-coherent")) | |
1674 | data = &of_l2c310_coherent_data; | |
1675 | ||
560be613 RK |
1676 | old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
1677 | if (old_aux != ((old_aux & aux_mask) | aux_val)) { | |
1678 | pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n", | |
1679 | old_aux, (old_aux & aux_mask) | aux_val); | |
1680 | } else if (aux_mask != ~0U && aux_val != 0) { | |
1681 | pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n"); | |
1682 | } | |
1683 | ||
d9d1f3e2 RK |
1684 | /* All L2 caches are unified, so this property should be specified */ |
1685 | if (!of_property_read_bool(np, "cache-unified")) | |
1686 | pr_err("L2C: device tree omits to specify unified cache\n"); | |
1687 | ||
1b4bd608 FF |
1688 | if (of_property_read_u32(np, "cache-level", &cache_level)) |
1689 | pr_err("L2C: device tree omits to specify cache-level\n"); | |
1690 | ||
1691 | if (cache_level != 2) | |
1692 | pr_err("L2C: device tree specifies invalid cache level\n"); | |
1693 | ||
6b49241a TF |
1694 | /* Read back current (default) hardware configuration */ |
1695 | if (data->save) | |
1696 | data->save(l2x0_base); | |
1697 | ||
8c369264 | 1698 | /* L2 configuration can only be changed if the cache is disabled */ |
40266d6f | 1699 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) |
c02642bc RK |
1700 | if (data->of_parse) |
1701 | data->of_parse(np, &aux_val, &aux_mask); | |
b8db6b88 | 1702 | |
96054b0a RK |
1703 | if (cache_id_part_number_from_dt) |
1704 | cache_id = cache_id_part_number_from_dt; | |
1705 | else | |
1706 | cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); | |
1707 | ||
6b49241a | 1708 | return __l2c_init(data, aux_val, aux_mask, cache_id); |
8c369264 RH |
1709 | } |
1710 | #endif |