Commit | Line | Data |
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382266ad CM |
1 | /* |
2 | * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support | |
3 | * | |
4 | * Copyright (C) 2007 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
8c369264 | 19 | #include <linux/err.h> |
382266ad | 20 | #include <linux/init.h> |
07620976 | 21 | #include <linux/spinlock.h> |
fced80c7 | 22 | #include <linux/io.h> |
8c369264 RH |
23 | #include <linux/of.h> |
24 | #include <linux/of_address.h> | |
382266ad CM |
25 | |
26 | #include <asm/cacheflush.h> | |
382266ad | 27 | #include <asm/hardware/cache-l2x0.h> |
e68f31f4 | 28 | #include "cache-tauros3.h" |
b8db6b88 | 29 | #include "cache-aurora-l2.h" |
382266ad | 30 | |
c02642bc | 31 | struct l2c_init_data { |
3b8bad57 | 32 | unsigned num_lock; |
c02642bc | 33 | void (*of_parse)(const struct device_node *, u32 *, u32 *); |
3b8bad57 | 34 | void (*enable)(void __iomem *, u32, unsigned); |
75461f5c | 35 | void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); |
9846dfc9 | 36 | void (*save)(void __iomem *); |
c02642bc RK |
37 | struct outer_cache_fns outer_cache; |
38 | }; | |
39 | ||
382266ad CM |
40 | #define CACHE_LINE_SIZE 32 |
41 | ||
42 | static void __iomem *l2x0_base; | |
bd31b859 | 43 | static DEFINE_RAW_SPINLOCK(l2x0_lock); |
3e175ca4 RK |
44 | static u32 l2x0_way_mask; /* Bitmask of active ways */ |
45 | static u32 l2x0_size; | |
f154fe9b | 46 | static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; |
382266ad | 47 | |
91c2ebb9 BS |
48 | struct l2x0_regs l2x0_saved_regs; |
49 | ||
37abcdb9 RK |
50 | /* |
51 | * Common code for all cache controllers. | |
52 | */ | |
83841fe1 | 53 | static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) |
382266ad | 54 | { |
9a6655e4 | 55 | /* wait for cache operation by line or way to complete */ |
6775a558 | 56 | while (readl_relaxed(reg) & mask) |
1caf3092 | 57 | cpu_relax(); |
382266ad CM |
58 | } |
59 | ||
2b2a87a1 RK |
60 | /* |
61 | * This should only be called when we have a requirement that the | |
62 | * register be written due to a work-around, as platforms running | |
63 | * in non-secure mode may not be able to access this register. | |
64 | */ | |
65 | static inline void l2c_set_debug(void __iomem *base, unsigned long val) | |
66 | { | |
67 | outer_cache.set_debug(val); | |
68 | } | |
69 | ||
df5dd4c6 RK |
70 | static void __l2c_op_way(void __iomem *reg) |
71 | { | |
72 | writel_relaxed(l2x0_way_mask, reg); | |
83841fe1 | 73 | l2c_wait_mask(reg, l2x0_way_mask); |
df5dd4c6 RK |
74 | } |
75 | ||
37abcdb9 RK |
76 | static inline void l2c_unlock(void __iomem *base, unsigned num) |
77 | { | |
78 | unsigned i; | |
79 | ||
80 | for (i = 0; i < num; i++) { | |
81 | writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + | |
82 | i * L2X0_LOCKDOWN_STRIDE); | |
83 | writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + | |
84 | i * L2X0_LOCKDOWN_STRIDE); | |
85 | } | |
86 | } | |
87 | ||
3b8bad57 RK |
88 | /* |
89 | * Enable the L2 cache controller. This function must only be | |
90 | * called when the cache controller is known to be disabled. | |
91 | */ | |
92 | static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) | |
93 | { | |
94 | unsigned long flags; | |
95 | ||
9a07f27b RK |
96 | /* Only write the aux register if it needs changing */ |
97 | if (readl_relaxed(base + L2X0_AUX_CTRL) != aux) | |
98 | writel_relaxed(aux, base + L2X0_AUX_CTRL); | |
3b8bad57 | 99 | |
17f3f99f RK |
100 | l2c_unlock(base, num_lock); |
101 | ||
3b8bad57 RK |
102 | local_irq_save(flags); |
103 | __l2c_op_way(base + L2X0_INV_WAY); | |
104 | writel_relaxed(0, base + sync_reg_offset); | |
105 | l2c_wait_mask(base + sync_reg_offset, 1); | |
106 | local_irq_restore(flags); | |
107 | ||
108 | writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); | |
109 | } | |
110 | ||
111 | static void l2c_disable(void) | |
112 | { | |
113 | void __iomem *base = l2x0_base; | |
114 | ||
115 | outer_cache.flush_all(); | |
116 | writel_relaxed(0, base + L2X0_CTRL); | |
117 | dsb(st); | |
118 | } | |
119 | ||
9a6655e4 CM |
120 | #ifdef CONFIG_CACHE_PL310 |
121 | static inline void cache_wait(void __iomem *reg, unsigned long mask) | |
122 | { | |
123 | /* cache operations by line are atomic on PL310 */ | |
124 | } | |
125 | #else | |
83841fe1 | 126 | #define cache_wait l2c_wait_mask |
9a6655e4 CM |
127 | #endif |
128 | ||
382266ad CM |
129 | static inline void cache_sync(void) |
130 | { | |
3d107434 | 131 | void __iomem *base = l2x0_base; |
885028e4 | 132 | |
f154fe9b | 133 | writel_relaxed(0, base + sync_reg_offset); |
3d107434 | 134 | cache_wait(base + L2X0_CACHE_SYNC, 1); |
382266ad CM |
135 | } |
136 | ||
424d6b14 SS |
137 | static inline void l2x0_clean_line(unsigned long addr) |
138 | { | |
139 | void __iomem *base = l2x0_base; | |
140 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | |
6775a558 | 141 | writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); |
424d6b14 SS |
142 | } |
143 | ||
144 | static inline void l2x0_inv_line(unsigned long addr) | |
145 | { | |
146 | void __iomem *base = l2x0_base; | |
147 | cache_wait(base + L2X0_INV_LINE_PA, 1); | |
6775a558 | 148 | writel_relaxed(addr, base + L2X0_INV_LINE_PA); |
424d6b14 SS |
149 | } |
150 | ||
2839e06c | 151 | #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) |
ab4d5368 WD |
152 | static inline void debug_writel(unsigned long val) |
153 | { | |
154 | if (outer_cache.set_debug) | |
2b2a87a1 | 155 | l2c_set_debug(l2x0_base, val); |
ab4d5368 | 156 | } |
9e65582a | 157 | |
ab4d5368 | 158 | static void pl310_set_debug(unsigned long val) |
2839e06c SS |
159 | { |
160 | writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); | |
9e65582a | 161 | } |
2839e06c SS |
162 | #else |
163 | /* Optimised out for non-errata case */ | |
164 | static inline void debug_writel(unsigned long val) | |
165 | { | |
166 | } | |
167 | ||
ab4d5368 | 168 | #define pl310_set_debug NULL |
2839e06c | 169 | #endif |
9e65582a | 170 | |
2839e06c | 171 | #ifdef CONFIG_PL310_ERRATA_588369 |
9e65582a SS |
172 | static inline void l2x0_flush_line(unsigned long addr) |
173 | { | |
174 | void __iomem *base = l2x0_base; | |
175 | ||
176 | /* Clean by PA followed by Invalidate by PA */ | |
177 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); | |
6775a558 | 178 | writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); |
9e65582a | 179 | cache_wait(base + L2X0_INV_LINE_PA, 1); |
6775a558 | 180 | writel_relaxed(addr, base + L2X0_INV_LINE_PA); |
9e65582a SS |
181 | } |
182 | #else | |
183 | ||
424d6b14 SS |
184 | static inline void l2x0_flush_line(unsigned long addr) |
185 | { | |
186 | void __iomem *base = l2x0_base; | |
187 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); | |
6775a558 | 188 | writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); |
424d6b14 | 189 | } |
9e65582a | 190 | #endif |
424d6b14 | 191 | |
23107c54 CM |
192 | static void l2x0_cache_sync(void) |
193 | { | |
194 | unsigned long flags; | |
195 | ||
bd31b859 | 196 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
23107c54 | 197 | cache_sync(); |
bd31b859 | 198 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
23107c54 CM |
199 | } |
200 | ||
38a8914f | 201 | static void __l2x0_flush_all(void) |
2fd86589 | 202 | { |
2839e06c | 203 | debug_writel(0x03); |
df5dd4c6 | 204 | __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY); |
2fd86589 | 205 | cache_sync(); |
2839e06c | 206 | debug_writel(0x00); |
38a8914f WD |
207 | } |
208 | ||
209 | static void l2x0_flush_all(void) | |
210 | { | |
211 | unsigned long flags; | |
212 | ||
213 | /* clean all ways */ | |
bd31b859 | 214 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
38a8914f | 215 | __l2x0_flush_all(); |
bd31b859 | 216 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
2fd86589 TG |
217 | } |
218 | ||
444457c1 SS |
219 | static void l2x0_clean_all(void) |
220 | { | |
221 | unsigned long flags; | |
222 | ||
223 | /* clean all ways */ | |
bd31b859 | 224 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
df5dd4c6 | 225 | __l2c_op_way(l2x0_base + L2X0_CLEAN_WAY); |
444457c1 | 226 | cache_sync(); |
bd31b859 | 227 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
444457c1 SS |
228 | } |
229 | ||
2fd86589 | 230 | static void l2x0_inv_all(void) |
382266ad | 231 | { |
0eb948dd RK |
232 | unsigned long flags; |
233 | ||
382266ad | 234 | /* invalidate all ways */ |
bd31b859 | 235 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
2fd86589 | 236 | /* Invalidating when L2 is enabled is a nono */ |
b8db6b88 | 237 | BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN); |
df5dd4c6 | 238 | __l2c_op_way(l2x0_base + L2X0_INV_WAY); |
382266ad | 239 | cache_sync(); |
bd31b859 | 240 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
241 | } |
242 | ||
243 | static void l2x0_inv_range(unsigned long start, unsigned long end) | |
244 | { | |
3d107434 | 245 | void __iomem *base = l2x0_base; |
0eb948dd | 246 | unsigned long flags; |
382266ad | 247 | |
bd31b859 | 248 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
4f6627ac RS |
249 | if (start & (CACHE_LINE_SIZE - 1)) { |
250 | start &= ~(CACHE_LINE_SIZE - 1); | |
9e65582a | 251 | debug_writel(0x03); |
424d6b14 | 252 | l2x0_flush_line(start); |
9e65582a | 253 | debug_writel(0x00); |
4f6627ac RS |
254 | start += CACHE_LINE_SIZE; |
255 | } | |
256 | ||
257 | if (end & (CACHE_LINE_SIZE - 1)) { | |
258 | end &= ~(CACHE_LINE_SIZE - 1); | |
9e65582a | 259 | debug_writel(0x03); |
424d6b14 | 260 | l2x0_flush_line(end); |
9e65582a | 261 | debug_writel(0x00); |
4f6627ac RS |
262 | } |
263 | ||
0eb948dd RK |
264 | while (start < end) { |
265 | unsigned long blk_end = start + min(end - start, 4096UL); | |
266 | ||
267 | while (start < blk_end) { | |
424d6b14 | 268 | l2x0_inv_line(start); |
0eb948dd RK |
269 | start += CACHE_LINE_SIZE; |
270 | } | |
271 | ||
272 | if (blk_end < end) { | |
bd31b859 TG |
273 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
274 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
0eb948dd RK |
275 | } |
276 | } | |
3d107434 | 277 | cache_wait(base + L2X0_INV_LINE_PA, 1); |
382266ad | 278 | cache_sync(); |
bd31b859 | 279 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
280 | } |
281 | ||
282 | static void l2x0_clean_range(unsigned long start, unsigned long end) | |
283 | { | |
3d107434 | 284 | void __iomem *base = l2x0_base; |
0eb948dd | 285 | unsigned long flags; |
382266ad | 286 | |
444457c1 SS |
287 | if ((end - start) >= l2x0_size) { |
288 | l2x0_clean_all(); | |
289 | return; | |
290 | } | |
291 | ||
bd31b859 | 292 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
382266ad | 293 | start &= ~(CACHE_LINE_SIZE - 1); |
0eb948dd RK |
294 | while (start < end) { |
295 | unsigned long blk_end = start + min(end - start, 4096UL); | |
296 | ||
297 | while (start < blk_end) { | |
424d6b14 | 298 | l2x0_clean_line(start); |
0eb948dd RK |
299 | start += CACHE_LINE_SIZE; |
300 | } | |
301 | ||
302 | if (blk_end < end) { | |
bd31b859 TG |
303 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
304 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
0eb948dd RK |
305 | } |
306 | } | |
3d107434 | 307 | cache_wait(base + L2X0_CLEAN_LINE_PA, 1); |
382266ad | 308 | cache_sync(); |
bd31b859 | 309 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
310 | } |
311 | ||
312 | static void l2x0_flush_range(unsigned long start, unsigned long end) | |
313 | { | |
3d107434 | 314 | void __iomem *base = l2x0_base; |
0eb948dd | 315 | unsigned long flags; |
382266ad | 316 | |
444457c1 SS |
317 | if ((end - start) >= l2x0_size) { |
318 | l2x0_flush_all(); | |
319 | return; | |
320 | } | |
321 | ||
bd31b859 | 322 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
382266ad | 323 | start &= ~(CACHE_LINE_SIZE - 1); |
0eb948dd RK |
324 | while (start < end) { |
325 | unsigned long blk_end = start + min(end - start, 4096UL); | |
326 | ||
9e65582a | 327 | debug_writel(0x03); |
0eb948dd | 328 | while (start < blk_end) { |
424d6b14 | 329 | l2x0_flush_line(start); |
0eb948dd RK |
330 | start += CACHE_LINE_SIZE; |
331 | } | |
9e65582a | 332 | debug_writel(0x00); |
0eb948dd RK |
333 | |
334 | if (blk_end < end) { | |
bd31b859 TG |
335 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
336 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
0eb948dd RK |
337 | } |
338 | } | |
3d107434 | 339 | cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); |
382266ad | 340 | cache_sync(); |
bd31b859 | 341 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
342 | } |
343 | ||
2fd86589 TG |
344 | static void l2x0_disable(void) |
345 | { | |
346 | unsigned long flags; | |
347 | ||
bd31b859 | 348 | raw_spin_lock_irqsave(&l2x0_lock, flags); |
38a8914f WD |
349 | __l2x0_flush_all(); |
350 | writel_relaxed(0, l2x0_base + L2X0_CTRL); | |
9781aa8a | 351 | dsb(st); |
bd31b859 | 352 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
2fd86589 TG |
353 | } |
354 | ||
3e175ca4 | 355 | static void l2x0_unlock(u32 cache_id) |
bac7e6ec LW |
356 | { |
357 | int lockregs; | |
bac7e6ec | 358 | |
6e7aceeb | 359 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
b8db6b88 | 360 | case L2X0_CACHE_ID_PART_L310: |
bac7e6ec | 361 | lockregs = 8; |
b8db6b88 | 362 | break; |
b8db6b88 | 363 | default: |
bac7e6ec LW |
364 | /* L210 and unknown types */ |
365 | lockregs = 1; | |
b8db6b88 GC |
366 | break; |
367 | } | |
bac7e6ec | 368 | |
37abcdb9 | 369 | l2c_unlock(l2x0_base, lockregs); |
bac7e6ec LW |
370 | } |
371 | ||
3b8bad57 RK |
372 | static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock) |
373 | { | |
3b8bad57 RK |
374 | /* l2x0 controller is disabled */ |
375 | writel_relaxed(aux, base + L2X0_AUX_CTRL); | |
376 | ||
17f3f99f RK |
377 | /* Make sure that I&D is not locked down when starting */ |
378 | l2x0_unlock(readl_relaxed(base + L2X0_CACHE_ID)); | |
379 | ||
3b8bad57 RK |
380 | l2x0_inv_all(); |
381 | ||
382 | /* enable L2X0 */ | |
383 | writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); | |
384 | } | |
385 | ||
b98556f2 RK |
386 | static void l2x0_resume(void) |
387 | { | |
388 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { | |
389 | /* restore aux ctrl and enable l2 */ | |
390 | l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID)); | |
391 | ||
392 | writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base + | |
393 | L2X0_AUX_CTRL); | |
394 | ||
395 | l2x0_inv_all(); | |
396 | ||
397 | writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL); | |
398 | } | |
399 | } | |
400 | ||
96054b0a | 401 | static const struct l2c_init_data l2x0_init_fns __initconst = { |
3b8bad57 | 402 | .enable = l2x0_enable, |
96054b0a RK |
403 | .outer_cache = { |
404 | .inv_range = l2x0_inv_range, | |
405 | .clean_range = l2x0_clean_range, | |
406 | .flush_range = l2x0_flush_range, | |
407 | .flush_all = l2x0_flush_all, | |
408 | .disable = l2x0_disable, | |
409 | .sync = l2x0_cache_sync, | |
b98556f2 | 410 | .resume = l2x0_resume, |
96054b0a RK |
411 | }, |
412 | }; | |
413 | ||
75461f5c RK |
414 | /* |
415 | * L2C-310 specific code. | |
416 | * | |
417 | * Errata: | |
418 | * 588369: PL310 R0P0->R1P0, fixed R2P0. | |
419 | * Affects: all clean+invalidate operations | |
420 | * clean and invalidate skips the invalidate step, so we need to issue | |
421 | * separate operations. We also require the above debug workaround | |
422 | * enclosing this code fragment on affected parts. On unaffected parts, | |
423 | * we must not use this workaround without the debug register writes | |
424 | * to avoid exposing a problem similar to 727915. | |
425 | * | |
426 | * 727915: PL310 R2P0->R3P0, fixed R3P1. | |
427 | * Affects: clean+invalidate by way | |
428 | * clean and invalidate by way runs in the background, and a store can | |
429 | * hit the line between the clean operation and invalidate operation, | |
430 | * resulting in the store being lost. | |
431 | * | |
432 | * 753970: PL310 R3P0, fixed R3P1. | |
433 | * Affects: sync | |
434 | * prevents merging writes after the sync operation, until another L2C | |
435 | * operation is performed (or a number of other conditions.) | |
436 | * | |
437 | * 769419: PL310 R0P0->R3P1, fixed R3P2. | |
438 | * Affects: store buffer | |
439 | * store buffer is not automatically drained. | |
440 | */ | |
b98556f2 RK |
441 | static void __init pl310_save(void __iomem *base) |
442 | { | |
443 | u32 l2x0_revision = readl_relaxed(base + L2X0_CACHE_ID) & | |
444 | L2X0_CACHE_ID_RTL_MASK; | |
445 | ||
446 | l2x0_saved_regs.tag_latency = readl_relaxed(base + | |
447 | L2X0_TAG_LATENCY_CTRL); | |
448 | l2x0_saved_regs.data_latency = readl_relaxed(base + | |
449 | L2X0_DATA_LATENCY_CTRL); | |
450 | l2x0_saved_regs.filter_end = readl_relaxed(base + | |
451 | L2X0_ADDR_FILTER_END); | |
452 | l2x0_saved_regs.filter_start = readl_relaxed(base + | |
453 | L2X0_ADDR_FILTER_START); | |
454 | ||
455 | if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) { | |
456 | /* | |
457 | * From r2p0, there is Prefetch offset/control register | |
458 | */ | |
459 | l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + | |
460 | L2X0_PREFETCH_CTRL); | |
461 | /* | |
462 | * From r3p0, there is Power control register | |
463 | */ | |
464 | if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0) | |
465 | l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + | |
466 | L2X0_POWER_CTRL); | |
467 | } | |
468 | } | |
469 | ||
470 | static void pl310_resume(void) | |
471 | { | |
472 | u32 l2x0_revision; | |
473 | ||
474 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { | |
475 | /* restore pl310 setup */ | |
476 | writel_relaxed(l2x0_saved_regs.tag_latency, | |
477 | l2x0_base + L2X0_TAG_LATENCY_CTRL); | |
478 | writel_relaxed(l2x0_saved_regs.data_latency, | |
479 | l2x0_base + L2X0_DATA_LATENCY_CTRL); | |
480 | writel_relaxed(l2x0_saved_regs.filter_end, | |
481 | l2x0_base + L2X0_ADDR_FILTER_END); | |
482 | writel_relaxed(l2x0_saved_regs.filter_start, | |
483 | l2x0_base + L2X0_ADDR_FILTER_START); | |
484 | ||
485 | l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & | |
486 | L2X0_CACHE_ID_RTL_MASK; | |
487 | ||
488 | if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) { | |
489 | writel_relaxed(l2x0_saved_regs.prefetch_ctrl, | |
490 | l2x0_base + L2X0_PREFETCH_CTRL); | |
491 | if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0) | |
492 | writel_relaxed(l2x0_saved_regs.pwr_ctrl, | |
493 | l2x0_base + L2X0_POWER_CTRL); | |
494 | } | |
495 | } | |
496 | ||
497 | l2x0_resume(); | |
498 | } | |
499 | ||
75461f5c RK |
500 | static void __init l2c310_fixup(void __iomem *base, u32 cache_id, |
501 | struct outer_cache_fns *fns) | |
502 | { | |
503 | unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; | |
504 | const char *errata[4]; | |
505 | unsigned n = 0; | |
506 | ||
507 | if (revision <= L310_CACHE_ID_RTL_R3P0) | |
508 | fns->set_debug = pl310_set_debug; | |
509 | ||
510 | if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && | |
511 | revision == L310_CACHE_ID_RTL_R3P0) { | |
512 | sync_reg_offset = L2X0_DUMMY_REG; | |
513 | errata[n++] = "753970"; | |
514 | } | |
515 | ||
516 | if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) | |
517 | errata[n++] = "769419"; | |
518 | ||
519 | if (n) { | |
520 | unsigned i; | |
521 | ||
522 | pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); | |
523 | for (i = 0; i < n; i++) | |
524 | pr_cont(" %s", errata[i]); | |
525 | pr_cont(" enabled\n"); | |
526 | } | |
527 | } | |
528 | ||
529 | static const struct l2c_init_data l2c310_init_fns __initconst = { | |
530 | .num_lock = 8, | |
531 | .enable = l2c_enable, | |
532 | .fixup = l2c310_fixup, | |
b98556f2 | 533 | .save = pl310_save, |
75461f5c RK |
534 | .outer_cache = { |
535 | .inv_range = l2x0_inv_range, | |
536 | .clean_range = l2x0_clean_range, | |
537 | .flush_range = l2x0_flush_range, | |
538 | .flush_all = l2x0_flush_all, | |
539 | .disable = l2x0_disable, | |
540 | .sync = l2x0_cache_sync, | |
b98556f2 | 541 | .resume = pl310_resume, |
75461f5c RK |
542 | }, |
543 | }; | |
544 | ||
96054b0a RK |
545 | static void __init __l2c_init(const struct l2c_init_data *data, |
546 | u32 aux_val, u32 aux_mask, u32 cache_id) | |
382266ad | 547 | { |
75461f5c | 548 | struct outer_cache_fns fns; |
3e175ca4 | 549 | u32 aux; |
3e175ca4 | 550 | u32 way_size = 0; |
64039be8 | 551 | int ways; |
b8db6b88 | 552 | int way_size_shift = L2X0_WAY_SIZE_SHIFT; |
64039be8 | 553 | const char *type; |
382266ad | 554 | |
c40e7eb6 RK |
555 | /* |
556 | * It is strange to save the register state before initialisation, | |
557 | * but hey, this is what the DT implementations decided to do. | |
558 | */ | |
559 | if (data->save) | |
560 | data->save(l2x0_base); | |
561 | ||
6775a558 | 562 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); |
64039be8 | 563 | |
4082cfa7 SH |
564 | aux &= aux_mask; |
565 | aux |= aux_val; | |
566 | ||
64039be8 | 567 | /* Determine the number of ways */ |
6e7aceeb | 568 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
64039be8 JM |
569 | case L2X0_CACHE_ID_PART_L310: |
570 | if (aux & (1 << 16)) | |
571 | ways = 16; | |
572 | else | |
573 | ways = 8; | |
574 | type = "L310"; | |
575 | break; | |
75461f5c | 576 | |
64039be8 JM |
577 | case L2X0_CACHE_ID_PART_L210: |
578 | ways = (aux >> 13) & 0xf; | |
579 | type = "L210"; | |
580 | break; | |
b8db6b88 GC |
581 | |
582 | case AURORA_CACHE_ID: | |
b8db6b88 GC |
583 | ways = (aux >> 13) & 0xf; |
584 | ways = 2 << ((ways + 1) >> 2); | |
585 | way_size_shift = AURORA_WAY_SIZE_SHIFT; | |
586 | type = "Aurora"; | |
587 | break; | |
75461f5c | 588 | |
64039be8 JM |
589 | default: |
590 | /* Assume unknown chips have 8 ways */ | |
591 | ways = 8; | |
592 | type = "L2x0 series"; | |
593 | break; | |
594 | } | |
595 | ||
596 | l2x0_way_mask = (1 << ways) - 1; | |
597 | ||
5ba70372 SS |
598 | /* |
599 | * L2 cache Size = Way size * Number of ways | |
600 | */ | |
601 | way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; | |
b8db6b88 GC |
602 | way_size = 1 << (way_size + way_size_shift); |
603 | ||
5ba70372 SS |
604 | l2x0_size = ways * way_size * SZ_1K; |
605 | ||
75461f5c RK |
606 | fns = data->outer_cache; |
607 | if (data->fixup) | |
608 | data->fixup(l2x0_base, cache_id, &fns); | |
609 | ||
48371cd3 | 610 | /* |
3b8bad57 RK |
611 | * Check if l2x0 controller is already enabled. If we are booting |
612 | * in non-secure mode accessing the below registers will fault. | |
48371cd3 | 613 | */ |
3b8bad57 RK |
614 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) |
615 | data->enable(l2x0_base, aux, data->num_lock); | |
382266ad | 616 | |
9d4876f0 YM |
617 | /* Re-read it in case some bits are reserved. */ |
618 | aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); | |
619 | ||
620 | /* Save the value for resuming. */ | |
621 | l2x0_saved_regs.aux_ctrl = aux; | |
622 | ||
75461f5c | 623 | outer_cache = fns; |
382266ad | 624 | |
cdef8689 RK |
625 | pr_info("%s cache controller enabled, %d ways, %d kB\n", |
626 | type, ways, l2x0_size >> 10); | |
627 | pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", | |
628 | type, cache_id, aux); | |
382266ad | 629 | } |
8c369264 | 630 | |
96054b0a RK |
631 | void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) |
632 | { | |
75461f5c | 633 | const struct l2c_init_data *data; |
96054b0a RK |
634 | u32 cache_id; |
635 | ||
636 | l2x0_base = base; | |
637 | ||
638 | cache_id = readl_relaxed(base + L2X0_CACHE_ID); | |
639 | ||
75461f5c RK |
640 | switch (cache_id & L2X0_CACHE_ID_PART_MASK) { |
641 | default: | |
642 | data = &l2x0_init_fns; | |
643 | break; | |
644 | ||
645 | case L2X0_CACHE_ID_PART_L310: | |
646 | data = &l2c310_init_fns; | |
647 | break; | |
648 | } | |
649 | ||
650 | __l2c_init(data, aux_val, aux_mask, cache_id); | |
96054b0a RK |
651 | } |
652 | ||
8c369264 | 653 | #ifdef CONFIG_OF |
b8db6b88 GC |
654 | static int l2_wt_override; |
655 | ||
96054b0a RK |
656 | /* Aurora don't have the cache ID register available, so we have to |
657 | * pass it though the device tree */ | |
658 | static u32 cache_id_part_number_from_dt; | |
659 | ||
da3627fb RK |
660 | static void __init l2x0_of_parse(const struct device_node *np, |
661 | u32 *aux_val, u32 *aux_mask) | |
662 | { | |
663 | u32 data[2] = { 0, 0 }; | |
664 | u32 tag = 0; | |
665 | u32 dirty = 0; | |
666 | u32 val = 0, mask = 0; | |
667 | ||
668 | of_property_read_u32(np, "arm,tag-latency", &tag); | |
669 | if (tag) { | |
670 | mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; | |
671 | val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; | |
672 | } | |
673 | ||
674 | of_property_read_u32_array(np, "arm,data-latency", | |
675 | data, ARRAY_SIZE(data)); | |
676 | if (data[0] && data[1]) { | |
677 | mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | | |
678 | L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; | |
679 | val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | | |
680 | ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); | |
681 | } | |
682 | ||
683 | of_property_read_u32(np, "arm,dirty-latency", &dirty); | |
684 | if (dirty) { | |
685 | mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; | |
686 | val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; | |
687 | } | |
688 | ||
689 | *aux_val &= ~mask; | |
690 | *aux_val |= val; | |
691 | *aux_mask &= ~mask; | |
692 | } | |
693 | ||
da3627fb RK |
694 | static const struct l2c_init_data of_l2x0_data __initconst = { |
695 | .of_parse = l2x0_of_parse, | |
3b8bad57 | 696 | .enable = l2x0_enable, |
da3627fb RK |
697 | .outer_cache = { |
698 | .inv_range = l2x0_inv_range, | |
699 | .clean_range = l2x0_clean_range, | |
700 | .flush_range = l2x0_flush_range, | |
701 | .flush_all = l2x0_flush_all, | |
702 | .disable = l2x0_disable, | |
703 | .sync = l2x0_cache_sync, | |
704 | .resume = l2x0_resume, | |
705 | }, | |
706 | }; | |
707 | ||
708 | static void __init pl310_of_parse(const struct device_node *np, | |
709 | u32 *aux_val, u32 *aux_mask) | |
710 | { | |
711 | u32 data[3] = { 0, 0, 0 }; | |
712 | u32 tag[3] = { 0, 0, 0 }; | |
713 | u32 filter[2] = { 0, 0 }; | |
714 | ||
715 | of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); | |
716 | if (tag[0] && tag[1] && tag[2]) | |
717 | writel_relaxed( | |
718 | ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | | |
719 | ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | | |
720 | ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), | |
721 | l2x0_base + L2X0_TAG_LATENCY_CTRL); | |
722 | ||
723 | of_property_read_u32_array(np, "arm,data-latency", | |
724 | data, ARRAY_SIZE(data)); | |
725 | if (data[0] && data[1] && data[2]) | |
726 | writel_relaxed( | |
727 | ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | | |
728 | ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | | |
729 | ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), | |
730 | l2x0_base + L2X0_DATA_LATENCY_CTRL); | |
731 | ||
732 | of_property_read_u32_array(np, "arm,filter-ranges", | |
733 | filter, ARRAY_SIZE(filter)); | |
734 | if (filter[1]) { | |
735 | writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), | |
736 | l2x0_base + L2X0_ADDR_FILTER_END); | |
737 | writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, | |
738 | l2x0_base + L2X0_ADDR_FILTER_START); | |
739 | } | |
740 | } | |
741 | ||
da3627fb | 742 | static const struct l2c_init_data of_pl310_data __initconst = { |
3b8bad57 | 743 | .num_lock = 8, |
da3627fb | 744 | .of_parse = pl310_of_parse, |
3b8bad57 | 745 | .enable = l2c_enable, |
75461f5c | 746 | .fixup = l2c310_fixup, |
da3627fb RK |
747 | .save = pl310_save, |
748 | .outer_cache = { | |
749 | .inv_range = l2x0_inv_range, | |
750 | .clean_range = l2x0_clean_range, | |
751 | .flush_range = l2x0_flush_range, | |
752 | .flush_all = l2x0_flush_all, | |
753 | .disable = l2x0_disable, | |
754 | .sync = l2x0_cache_sync, | |
755 | .resume = pl310_resume, | |
756 | }, | |
757 | }; | |
758 | ||
b8db6b88 GC |
759 | /* |
760 | * Note that the end addresses passed to Linux primitives are | |
761 | * noninclusive, while the hardware cache range operations use | |
762 | * inclusive start and end addresses. | |
763 | */ | |
764 | static unsigned long calc_range_end(unsigned long start, unsigned long end) | |
765 | { | |
766 | /* | |
767 | * Limit the number of cache lines processed at once, | |
768 | * since cache range operations stall the CPU pipeline | |
769 | * until completion. | |
770 | */ | |
771 | if (end > start + MAX_RANGE_SIZE) | |
772 | end = start + MAX_RANGE_SIZE; | |
773 | ||
774 | /* | |
775 | * Cache range operations can't straddle a page boundary. | |
776 | */ | |
777 | if (end > PAGE_ALIGN(start+1)) | |
778 | end = PAGE_ALIGN(start+1); | |
779 | ||
780 | return end; | |
781 | } | |
782 | ||
783 | /* | |
784 | * Make sure 'start' and 'end' reference the same page, as L2 is PIPT | |
785 | * and range operations only do a TLB lookup on the start address. | |
786 | */ | |
787 | static void aurora_pa_range(unsigned long start, unsigned long end, | |
788 | unsigned long offset) | |
789 | { | |
790 | unsigned long flags; | |
791 | ||
792 | raw_spin_lock_irqsave(&l2x0_lock, flags); | |
8a3a180d GC |
793 | writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); |
794 | writel_relaxed(end, l2x0_base + offset); | |
b8db6b88 GC |
795 | raw_spin_unlock_irqrestore(&l2x0_lock, flags); |
796 | ||
797 | cache_sync(); | |
798 | } | |
799 | ||
800 | static void aurora_inv_range(unsigned long start, unsigned long end) | |
801 | { | |
802 | /* | |
803 | * round start and end adresses up to cache line size | |
804 | */ | |
805 | start &= ~(CACHE_LINE_SIZE - 1); | |
806 | end = ALIGN(end, CACHE_LINE_SIZE); | |
807 | ||
808 | /* | |
809 | * Invalidate all full cache lines between 'start' and 'end'. | |
810 | */ | |
811 | while (start < end) { | |
812 | unsigned long range_end = calc_range_end(start, end); | |
813 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, | |
814 | AURORA_INVAL_RANGE_REG); | |
815 | start = range_end; | |
816 | } | |
817 | } | |
818 | ||
819 | static void aurora_clean_range(unsigned long start, unsigned long end) | |
820 | { | |
821 | /* | |
822 | * If L2 is forced to WT, the L2 will always be clean and we | |
823 | * don't need to do anything here. | |
824 | */ | |
825 | if (!l2_wt_override) { | |
826 | start &= ~(CACHE_LINE_SIZE - 1); | |
827 | end = ALIGN(end, CACHE_LINE_SIZE); | |
828 | while (start != end) { | |
829 | unsigned long range_end = calc_range_end(start, end); | |
830 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, | |
831 | AURORA_CLEAN_RANGE_REG); | |
832 | start = range_end; | |
833 | } | |
834 | } | |
835 | } | |
836 | ||
837 | static void aurora_flush_range(unsigned long start, unsigned long end) | |
838 | { | |
8b827c60 GC |
839 | start &= ~(CACHE_LINE_SIZE - 1); |
840 | end = ALIGN(end, CACHE_LINE_SIZE); | |
841 | while (start != end) { | |
842 | unsigned long range_end = calc_range_end(start, end); | |
843 | /* | |
844 | * If L2 is forced to WT, the L2 will always be clean and we | |
845 | * just need to invalidate. | |
846 | */ | |
847 | if (l2_wt_override) | |
b8db6b88 | 848 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, |
8b827c60 GC |
849 | AURORA_INVAL_RANGE_REG); |
850 | else | |
851 | aurora_pa_range(start, range_end - CACHE_LINE_SIZE, | |
852 | AURORA_FLUSH_RANGE_REG); | |
853 | start = range_end; | |
b8db6b88 GC |
854 | } |
855 | } | |
856 | ||
da3627fb RK |
857 | static void aurora_save(void __iomem *base) |
858 | { | |
859 | l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); | |
860 | l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); | |
861 | } | |
862 | ||
863 | static void aurora_resume(void) | |
864 | { | |
865 | if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { | |
866 | writel_relaxed(l2x0_saved_regs.aux_ctrl, | |
867 | l2x0_base + L2X0_AUX_CTRL); | |
868 | writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); | |
869 | } | |
870 | } | |
871 | ||
40266d6f RK |
872 | /* |
873 | * For Aurora cache in no outer mode, enable via the CP15 coprocessor | |
874 | * broadcasting of cache commands to L2. | |
875 | */ | |
876 | static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, | |
877 | unsigned num_lock) | |
da3627fb | 878 | { |
40266d6f RK |
879 | u32 u; |
880 | ||
881 | asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); | |
da3627fb | 882 | u |= AURORA_CTRL_FW; /* Set the FW bit */ |
40266d6f RK |
883 | asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); |
884 | ||
da3627fb | 885 | isb(); |
40266d6f RK |
886 | |
887 | l2c_enable(base, aux, num_lock); | |
da3627fb RK |
888 | } |
889 | ||
75461f5c RK |
890 | static void __init aurora_fixup(void __iomem *base, u32 cache_id, |
891 | struct outer_cache_fns *fns) | |
892 | { | |
893 | sync_reg_offset = AURORA_SYNC_REG; | |
894 | } | |
895 | ||
da3627fb RK |
896 | static void __init aurora_of_parse(const struct device_node *np, |
897 | u32 *aux_val, u32 *aux_mask) | |
898 | { | |
899 | u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; | |
900 | u32 mask = AURORA_ACR_REPLACEMENT_MASK; | |
901 | ||
902 | of_property_read_u32(np, "cache-id-part", | |
903 | &cache_id_part_number_from_dt); | |
904 | ||
905 | /* Determine and save the write policy */ | |
906 | l2_wt_override = of_property_read_bool(np, "wt-override"); | |
907 | ||
908 | if (l2_wt_override) { | |
909 | val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; | |
910 | mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; | |
911 | } | |
912 | ||
913 | *aux_val &= ~mask; | |
914 | *aux_val |= val; | |
915 | *aux_mask &= ~mask; | |
916 | } | |
917 | ||
918 | static const struct l2c_init_data of_aurora_with_outer_data __initconst = { | |
3b8bad57 | 919 | .num_lock = 4, |
da3627fb | 920 | .of_parse = aurora_of_parse, |
3b8bad57 | 921 | .enable = l2c_enable, |
75461f5c | 922 | .fixup = aurora_fixup, |
da3627fb RK |
923 | .save = aurora_save, |
924 | .outer_cache = { | |
925 | .inv_range = aurora_inv_range, | |
926 | .clean_range = aurora_clean_range, | |
927 | .flush_range = aurora_flush_range, | |
928 | .flush_all = l2x0_flush_all, | |
929 | .disable = l2x0_disable, | |
930 | .sync = l2x0_cache_sync, | |
931 | .resume = aurora_resume, | |
932 | }, | |
933 | }; | |
934 | ||
935 | static const struct l2c_init_data of_aurora_no_outer_data __initconst = { | |
3b8bad57 | 936 | .num_lock = 4, |
da3627fb | 937 | .of_parse = aurora_of_parse, |
40266d6f | 938 | .enable = aurora_enable_no_outer, |
75461f5c | 939 | .fixup = aurora_fixup, |
da3627fb RK |
940 | .save = aurora_save, |
941 | .outer_cache = { | |
942 | .resume = aurora_resume, | |
943 | }, | |
944 | }; | |
945 | ||
3b656fed CD |
946 | /* |
947 | * For certain Broadcom SoCs, depending on the address range, different offsets | |
948 | * need to be added to the address before passing it to L2 for | |
949 | * invalidation/clean/flush | |
950 | * | |
951 | * Section Address Range Offset EMI | |
952 | * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC | |
953 | * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS | |
954 | * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC | |
955 | * | |
956 | * When the start and end addresses have crossed two different sections, we | |
957 | * need to break the L2 operation into two, each within its own section. | |
958 | * For example, if we need to invalidate addresses starts at 0xBFFF0000 and | |
959 | * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) | |
960 | * 0xC0000000 - 0xC0001000 | |
961 | * | |
962 | * Note 1: | |
963 | * By breaking a single L2 operation into two, we may potentially suffer some | |
964 | * performance hit, but keep in mind the cross section case is very rare | |
965 | * | |
966 | * Note 2: | |
967 | * We do not need to handle the case when the start address is in | |
968 | * Section 1 and the end address is in Section 3, since it is not a valid use | |
969 | * case | |
970 | * | |
971 | * Note 3: | |
972 | * Section 1 in practical terms can no longer be used on rev A2. Because of | |
973 | * that the code does not need to handle section 1 at all. | |
974 | * | |
975 | */ | |
976 | #define BCM_SYS_EMI_START_ADDR 0x40000000UL | |
977 | #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL | |
978 | ||
979 | #define BCM_SYS_EMI_OFFSET 0x40000000UL | |
980 | #define BCM_VC_EMI_OFFSET 0x80000000UL | |
981 | ||
982 | static inline int bcm_addr_is_sys_emi(unsigned long addr) | |
983 | { | |
984 | return (addr >= BCM_SYS_EMI_START_ADDR) && | |
985 | (addr < BCM_VC_EMI_SEC3_START_ADDR); | |
986 | } | |
987 | ||
988 | static inline unsigned long bcm_l2_phys_addr(unsigned long addr) | |
989 | { | |
990 | if (bcm_addr_is_sys_emi(addr)) | |
991 | return addr + BCM_SYS_EMI_OFFSET; | |
992 | else | |
993 | return addr + BCM_VC_EMI_OFFSET; | |
994 | } | |
995 | ||
996 | static void bcm_inv_range(unsigned long start, unsigned long end) | |
997 | { | |
998 | unsigned long new_start, new_end; | |
999 | ||
1000 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1001 | ||
1002 | if (unlikely(end <= start)) | |
1003 | return; | |
1004 | ||
1005 | new_start = bcm_l2_phys_addr(start); | |
1006 | new_end = bcm_l2_phys_addr(end); | |
1007 | ||
1008 | /* normal case, no cross section between start and end */ | |
1009 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
1010 | l2x0_inv_range(new_start, new_end); | |
1011 | return; | |
1012 | } | |
1013 | ||
1014 | /* They cross sections, so it can only be a cross from section | |
1015 | * 2 to section 3 | |
1016 | */ | |
1017 | l2x0_inv_range(new_start, | |
1018 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); | |
1019 | l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), | |
1020 | new_end); | |
1021 | } | |
1022 | ||
1023 | static void bcm_clean_range(unsigned long start, unsigned long end) | |
1024 | { | |
1025 | unsigned long new_start, new_end; | |
1026 | ||
1027 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1028 | ||
1029 | if (unlikely(end <= start)) | |
1030 | return; | |
1031 | ||
1032 | if ((end - start) >= l2x0_size) { | |
1033 | l2x0_clean_all(); | |
1034 | return; | |
1035 | } | |
1036 | ||
1037 | new_start = bcm_l2_phys_addr(start); | |
1038 | new_end = bcm_l2_phys_addr(end); | |
1039 | ||
1040 | /* normal case, no cross section between start and end */ | |
1041 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
1042 | l2x0_clean_range(new_start, new_end); | |
1043 | return; | |
1044 | } | |
1045 | ||
1046 | /* They cross sections, so it can only be a cross from section | |
1047 | * 2 to section 3 | |
1048 | */ | |
1049 | l2x0_clean_range(new_start, | |
1050 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); | |
1051 | l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), | |
1052 | new_end); | |
1053 | } | |
1054 | ||
1055 | static void bcm_flush_range(unsigned long start, unsigned long end) | |
1056 | { | |
1057 | unsigned long new_start, new_end; | |
1058 | ||
1059 | BUG_ON(start < BCM_SYS_EMI_START_ADDR); | |
1060 | ||
1061 | if (unlikely(end <= start)) | |
1062 | return; | |
1063 | ||
1064 | if ((end - start) >= l2x0_size) { | |
1065 | l2x0_flush_all(); | |
1066 | return; | |
1067 | } | |
1068 | ||
1069 | new_start = bcm_l2_phys_addr(start); | |
1070 | new_end = bcm_l2_phys_addr(end); | |
1071 | ||
1072 | /* normal case, no cross section between start and end */ | |
1073 | if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { | |
1074 | l2x0_flush_range(new_start, new_end); | |
1075 | return; | |
1076 | } | |
1077 | ||
1078 | /* They cross sections, so it can only be a cross from section | |
1079 | * 2 to section 3 | |
1080 | */ | |
1081 | l2x0_flush_range(new_start, | |
1082 | bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); | |
1083 | l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), | |
1084 | new_end); | |
1085 | } | |
1086 | ||
da3627fb | 1087 | static const struct l2c_init_data of_bcm_l2x0_data __initconst = { |
3b8bad57 | 1088 | .num_lock = 8, |
da3627fb | 1089 | .of_parse = pl310_of_parse, |
3b8bad57 | 1090 | .enable = l2c_enable, |
75461f5c | 1091 | .fixup = l2c310_fixup, |
da3627fb RK |
1092 | .save = pl310_save, |
1093 | .outer_cache = { | |
1094 | .inv_range = bcm_inv_range, | |
1095 | .clean_range = bcm_clean_range, | |
1096 | .flush_range = bcm_flush_range, | |
1097 | .flush_all = l2x0_flush_all, | |
1098 | .disable = l2x0_disable, | |
1099 | .sync = l2x0_cache_sync, | |
1100 | .resume = pl310_resume, | |
1101 | }, | |
1102 | }; | |
b8db6b88 | 1103 | |
9846dfc9 | 1104 | static void __init tauros3_save(void __iomem *base) |
e68f31f4 SH |
1105 | { |
1106 | l2x0_saved_regs.aux2_ctrl = | |
9846dfc9 | 1107 | readl_relaxed(base + TAUROS3_AUX2_CTRL); |
e68f31f4 | 1108 | l2x0_saved_regs.prefetch_ctrl = |
9846dfc9 | 1109 | readl_relaxed(base + L2X0_PREFETCH_CTRL); |
e68f31f4 SH |
1110 | } |
1111 | ||
e68f31f4 SH |
1112 | static void tauros3_resume(void) |
1113 | { | |
1114 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { | |
1115 | writel_relaxed(l2x0_saved_regs.aux2_ctrl, | |
1116 | l2x0_base + TAUROS3_AUX2_CTRL); | |
1117 | writel_relaxed(l2x0_saved_regs.prefetch_ctrl, | |
1118 | l2x0_base + L2X0_PREFETCH_CTRL); | |
1119 | } | |
1120 | ||
1121 | l2x0_resume(); | |
1122 | } | |
1123 | ||
c02642bc | 1124 | static const struct l2c_init_data of_tauros3_data __initconst = { |
3b8bad57 RK |
1125 | .num_lock = 8, |
1126 | .enable = l2c_enable, | |
e68f31f4 SH |
1127 | .save = tauros3_save, |
1128 | /* Tauros3 broadcasts L1 cache operations to L2 */ | |
1129 | .outer_cache = { | |
1130 | .resume = tauros3_resume, | |
1131 | }, | |
1132 | }; | |
1133 | ||
a65bb925 | 1134 | #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } |
8c369264 | 1135 | static const struct of_device_id l2x0_ids[] __initconst = { |
c02642bc RK |
1136 | L2C_ID("arm,l210-cache", of_l2x0_data), |
1137 | L2C_ID("arm,l220-cache", of_l2x0_data), | |
1138 | L2C_ID("arm,pl310-cache", of_pl310_data), | |
1139 | L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), | |
1140 | L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), | |
1141 | L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), | |
1142 | L2C_ID("marvell,tauros3-cache", of_tauros3_data), | |
a65bb925 | 1143 | /* Deprecated IDs */ |
c02642bc | 1144 | L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), |
8c369264 RH |
1145 | {} |
1146 | }; | |
1147 | ||
3e175ca4 | 1148 | int __init l2x0_of_init(u32 aux_val, u32 aux_mask) |
8c369264 | 1149 | { |
c02642bc | 1150 | const struct l2c_init_data *data; |
8c369264 | 1151 | struct device_node *np; |
91c2ebb9 | 1152 | struct resource res; |
96054b0a | 1153 | u32 cache_id; |
8c369264 RH |
1154 | |
1155 | np = of_find_matching_node(NULL, l2x0_ids); | |
1156 | if (!np) | |
1157 | return -ENODEV; | |
91c2ebb9 BS |
1158 | |
1159 | if (of_address_to_resource(np, 0, &res)) | |
1160 | return -ENODEV; | |
1161 | ||
1162 | l2x0_base = ioremap(res.start, resource_size(&res)); | |
8c369264 RH |
1163 | if (!l2x0_base) |
1164 | return -ENOMEM; | |
1165 | ||
91c2ebb9 BS |
1166 | l2x0_saved_regs.phy_base = res.start; |
1167 | ||
1168 | data = of_match_node(l2x0_ids, np)->data; | |
1169 | ||
8c369264 | 1170 | /* L2 configuration can only be changed if the cache is disabled */ |
40266d6f | 1171 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) |
c02642bc RK |
1172 | if (data->of_parse) |
1173 | data->of_parse(np, &aux_val, &aux_mask); | |
b8db6b88 | 1174 | |
96054b0a RK |
1175 | if (cache_id_part_number_from_dt) |
1176 | cache_id = cache_id_part_number_from_dt; | |
1177 | else | |
1178 | cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); | |
1179 | ||
1180 | __l2c_init(data, aux_val, aux_mask, cache_id); | |
6248d060 | 1181 | |
8c369264 RH |
1182 | return 0; |
1183 | } | |
1184 | #endif |