[deliverable/linux.git] / arch / arm / mm / cache-tauros2.c

/*
 * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
 *
 * Copyright (C) 2008 Marvell Semiconductor
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * References:
 * - PJ1 CPU Core Datasheet,
 *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
 * - PJ4 CPU Core Datasheet,
 *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
 */

#include <linux/init.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/cputype.h>
#include <asm/hardware/cache-tauros2.h>


/*
 * When Tauros2 is used on a CPU that supports the v7 hierarchical
 * cache operations, the cache handling code in proc-v7.S takes care
 * of everything, including handling DMA coherency.
 *
 * So, we only need to register outer cache operations here if we're
 * being used on a pre-v7 CPU, and we only need to build support for
 * outer cache operations into the kernel image if the kernel has been
 * configured to support a pre-v7 CPU.
 */
#if __LINUX_ARM_ARCH__ < 7
/*
 * Low-level cache maintenance operations.
 */
static inline void tauros2_clean_pa(unsigned long addr)
{
	__asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
}

static inline void tauros2_clean_inv_pa(unsigned long addr)
{
	__asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
}

static inline void tauros2_inv_pa(unsigned long addr)
{
	__asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
}


/*
 * Linux primitives.
 *
 * Note that the end addresses passed to Linux primitives are
 * noninclusive.
 */
#define CACHE_LINE_SIZE		32

static void tauros2_inv_range(unsigned long start, unsigned long end)
{
	/*
	 * Clean and invalidate partial first cache line.
	 */
	if (start & (CACHE_LINE_SIZE - 1)) {
		tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
	}

	/*
	 * Clean and invalidate partial last cache line.
	 */
	if (end & (CACHE_LINE_SIZE - 1)) {
		tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
		end &= ~(CACHE_LINE_SIZE - 1);
	}

	/*
	 * Invalidate all full cache lines between 'start' and 'end'.
	 */
	while (start < end) {
		tauros2_inv_pa(start);
		start += CACHE_LINE_SIZE;
	}

	dsb();
}

static void tauros2_clean_range(unsigned long start, unsigned long end)
{
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		tauros2_clean_pa(start);
		start += CACHE_LINE_SIZE;
	}

	dsb();
}

static void tauros2_flush_range(unsigned long start, unsigned long end)
{
	start &= ~(CACHE_LINE_SIZE - 1);
	while (start < end) {
		tauros2_clean_inv_pa(start);
		start += CACHE_LINE_SIZE;
	}

	dsb();
}

static void tauros2_disable(void)
{
	__asm__ __volatile__ (
	"mcr	p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"
	"mrc	p15, 0, %0, c1, c0, 0\n\t"
	"bic	%0, %0, #(1 << 26)\n\t"
	"mcr	p15, 0, %0, c1, c0, 0  @Disable L2 Cache\n\t"
	: : "r" (0x0));
}

static void tauros2_resume(void)
{
	__asm__ __volatile__ (
	"mcr	p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"
	"mrc	p15, 0, %0, c1, c0, 0\n\t"
	"orr	%0, %0, #(1 << 26)\n\t"
	"mcr	p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"
	: : "r" (0x0));
}
#endif

static inline u32 __init read_extra_features(void)
{
	u32 u;

	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));

	return u;
}

static inline void __init write_extra_features(u32 u)
{
	__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
}

static inline int __init cpuid_scheme(void)
{
	return !!((processor_id & 0x000f0000) == 0x000f0000);
}

static inline u32 __init read_mmfr3(void)
{
	u32 mmfr3;

	__asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));

	return mmfr3;
}

static inline u32 __init read_actlr(void)
{
	u32 actlr;

	__asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));

	return actlr;
}

static inline void __init write_actlr(u32 actlr)
{
	__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
}

static void enable_extra_feature(unsigned int features)
{
	u32 u;

	u = read_extra_features();

	if (features & CACHE_TAUROS2_PREFETCH_ON)
		u &= ~0x01000000;
	else
		u |= 0x01000000;
	printk(KERN_INFO "Tauros2: %s L2 prefetch.\n",
			(features & CACHE_TAUROS2_PREFETCH_ON)
			? "Enabling" : "Disabling");

	if (features & CACHE_TAUROS2_LINEFILL_BURST8)
		u |= 0x00100000;
	else
		u &= ~0x00100000;
	printk(KERN_INFO "Tauros2: %s line fill burt8.\n",
			(features & CACHE_TAUROS2_LINEFILL_BURST8)
			? "Enabling" : "Disabling");

	write_extra_features(u);
}

void __init tauros2_init(unsigned int features)
{
	char *mode = NULL;

	enable_extra_feature(features);

#ifdef CONFIG_CPU_32v5
	if ((processor_id & 0xff0f0000) == 0x56050000) {
		u32 feat;

		/*
		 * v5 CPUs with Tauros2 have the L2 cache enable bit
		 * located in the CPU Extra Features register.
		 */
		feat = read_extra_features();
		if (!(feat & 0x00400000)) {
			printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
			write_extra_features(feat | 0x00400000);
		}

		mode = "ARMv5";
		outer_cache.inv_range = tauros2_inv_range;
		outer_cache.clean_range = tauros2_clean_range;
		outer_cache.flush_range = tauros2_flush_range;
		outer_cache.disable = tauros2_disable;
		outer_cache.resume = tauros2_resume;
	}
#endif

#ifdef CONFIG_CPU_32v6
	/*
	 * Check whether this CPU lacks support for the v7 hierarchical
	 * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
	 * register indicates no support for the v7 hierarchical cache
	 * ops.)
	 */
	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
		/*
		 * When Tauros2 is used in an ARMv6 system, the L2
		 * enable bit is in the ARMv6 ARM-mandated position
		 * (bit [26] of the System Control Register).
		 */
		if (!(get_cr() & 0x04000000)) {
			printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
			adjust_cr(0x04000000, 0x04000000);
		}

		mode = "ARMv6";
		outer_cache.inv_range = tauros2_inv_range;
		outer_cache.clean_range = tauros2_clean_range;
		outer_cache.flush_range = tauros2_flush_range;
		outer_cache.disable = tauros2_disable;
		outer_cache.resume = tauros2_resume;
	}
#endif

#ifdef CONFIG_CPU_32v7
	/*
	 * Check whether this CPU has support for the v7 hierarchical
	 * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3
	 * register indicates support for the v7 hierarchical cache
	 * ops.)
	 *
	 * (Although strictly speaking there may exist CPUs that
	 * implement the v7 cache ops but are only ARMv6 CPUs (due to
	 * not complying with all of the other ARMv7 requirements),
	 * there are no real-life examples of Tauros2 being used on
	 * such CPUs as of yet.)
	 */
	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
		u32 actlr;

		/*
		 * When Tauros2 is used in an ARMv7 system, the L2
		 * enable bit is located in the Auxiliary System Control
		 * Register (which is the only register allowed by the
		 * ARMv7 spec to contain fine-grained cache control bits).
		 */
		actlr = read_actlr();
		if (!(actlr & 0x00000002)) {
			printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
			write_actlr(actlr | 0x00000002);
		}

		mode = "ARMv7";
	}
#endif

	if (mode == NULL) {
		printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n");
		return;
	}

	printk(KERN_INFO "Tauros2: L2 cache support initialised "
			 "in %s mode.\n", mode);
}
Commit	Line	Data
573a652f LB	1	/*
	2	* arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
	3	*
	4	* Copyright (C) 2008 Marvell Semiconductor
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*
	10	* References:
	11	* - PJ1 CPU Core Datasheet,
	12	* Document ID MV-S104837-01, Rev 0.7, January 24 2008.
	13	* - PJ4 CPU Core Datasheet,
	14	* Document ID MV-S105190-00, Rev 0.7, March 14 2008.
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <asm/cacheflush.h>
15d07dc9	19	#include <asm/cp15.h>
fa79b8d6	20	#include <asm/cputype.h>
573a652f LB	21	#include <asm/hardware/cache-tauros2.h>
	22
	23
	24	/*
	25	* When Tauros2 is used on a CPU that supports the v7 hierarchical
	26	* cache operations, the cache handling code in proc-v7.S takes care
	27	* of everything, including handling DMA coherency.
	28	*
	29	* So, we only need to register outer cache operations here if we're
	30	* being used on a pre-v7 CPU, and we only need to build support for
	31	* outer cache operations into the kernel image if the kernel has been
	32	* configured to support a pre-v7 CPU.
	33	*/
	34	#if __LINUX_ARM_ARCH__ < 7
	35	/*
	36	* Low-level cache maintenance operations.
	37	*/
	38	static inline void tauros2_clean_pa(unsigned long addr)
	39	{
	40	__asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
	41	}
	42
	43	static inline void tauros2_clean_inv_pa(unsigned long addr)
	44	{
	45	__asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
	46	}
	47
	48	static inline void tauros2_inv_pa(unsigned long addr)
	49	{
	50	__asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
	51	}
	52
	53
	54	/*
	55	* Linux primitives.
	56	*
	57	* Note that the end addresses passed to Linux primitives are
	58	* noninclusive.
	59	*/
	60	#define CACHE_LINE_SIZE 32
	61
	62	static void tauros2_inv_range(unsigned long start, unsigned long end)
	63	{
	64	/*
	65	* Clean and invalidate partial first cache line.
	66	*/
	67	if (start & (CACHE_LINE_SIZE - 1)) {
	68	tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
	69	start = (start \| (CACHE_LINE_SIZE - 1)) + 1;
	70	}
	71
	72	/*
	73	* Clean and invalidate partial last cache line.
	74	*/
	75	if (end & (CACHE_LINE_SIZE - 1)) {
	76	tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
	77	end &= ~(CACHE_LINE_SIZE - 1);
	78	}
	79
	80	/*
	81	* Invalidate all full cache lines between 'start' and 'end'.
	82	*/
	83	while (start < end) {
	84	tauros2_inv_pa(start);
85	start += CACHE_LINE_SIZE;
86	}
87
88	dsb();
89	}
90
91	static void tauros2_clean_range(unsigned long start, unsigned long end)
92	{
93	start &= ~(CACHE_LINE_SIZE - 1);
94	while (start < end) {
95	tauros2_clean_pa(start);
96	start += CACHE_LINE_SIZE;
97	}
98
99	dsb();
100	}
101
102	static void tauros2_flush_range(unsigned long start, unsigned long end)
103	{
104	start &= ~(CACHE_LINE_SIZE - 1);
105	while (start < end) {
106	tauros2_clean_inv_pa(start);
107	start += CACHE_LINE_SIZE;
108	}
109
110	dsb();
111	}
89326f76 CX	112
	113	static void tauros2_disable(void)
	114	{
	115	__asm__ __volatile__ (
	116	"mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"
	117	"mrc p15, 0, %0, c1, c0, 0\n\t"
	118	"bic %0, %0, #(1 << 26)\n\t"
	119	"mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t"
	120	: : "r" (0x0));
	121	}
	122
	123	static void tauros2_resume(void)
	124	{
	125	__asm__ __volatile__ (
	126	"mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"
	127	"mrc p15, 0, %0, c1, c0, 0\n\t"
	128	"orr %0, %0, #(1 << 26)\n\t"
	129	"mcr p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"
	130	: : "r" (0x0));
	131	}
573a652f LB	132	#endif
	133
	134	static inline u32 __init read_extra_features(void)
	135	{
	136	u32 u;
	137
	138	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
	139
	140	return u;
	141	}
	142
	143	static inline void __init write_extra_features(u32 u)
	144	{
	145	__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
	146	}
	147
573a652f LB	148	static inline int __init cpuid_scheme(void)
573a652f LB	149	{
573a652f LB	150	return !!((processor_id & 0x000f0000) == 0x000f0000);
	151	}
	152
	153	static inline u32 __init read_mmfr3(void)
	154	{
	155	u32 mmfr3;
	156
	157	__asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
	158
	159	return mmfr3;
	160	}
	161
	162	static inline u32 __init read_actlr(void)
	163	{
	164	u32 actlr;
	165
	166	__asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
	167
	168	return actlr;
	169	}
	170
	171	static inline void __init write_actlr(u32 actlr)
	172	{
	173	__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
	174	}
	175
38f2e377 CX	176	static void enable_extra_feature(unsigned int features)
	177	{
	178	u32 u;
	179
	180	u = read_extra_features();
	181
	182	if (features & CACHE_TAUROS2_PREFETCH_ON)
	183	u &= ~0x01000000;
	184	else
	185	u \|= 0x01000000;
	186	printk(KERN_INFO "Tauros2: %s L2 prefetch.\n",
	187	(features & CACHE_TAUROS2_PREFETCH_ON)
	188	? "Enabling" : "Disabling");
	189
	190	if (features & CACHE_TAUROS2_LINEFILL_BURST8)
	191	u \|= 0x00100000;
	192	else
	193	u &= ~0x00100000;
	194	printk(KERN_INFO "Tauros2: %s line fill burt8.\n",
	195	(features & CACHE_TAUROS2_LINEFILL_BURST8)
	196	? "Enabling" : "Disabling");
	197
	198	write_extra_features(u);
	199	}
	200
	201	void __init tauros2_init(unsigned int features)
573a652f	202	{
5967b546	203	char *mode = NULL;
573a652f	204
38f2e377	205	enable_extra_feature(features);
573a652f LB	206
	207	#ifdef CONFIG_CPU_32v5
	208	if ((processor_id & 0xff0f0000) == 0x56050000) {
	209	u32 feat;
	210
	211	/*
	212	* v5 CPUs with Tauros2 have the L2 cache enable bit
	213	* located in the CPU Extra Features register.
	214	*/
	215	feat = read_extra_features();
	216	if (!(feat & 0x00400000)) {
	217	printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
	218	write_extra_features(feat \| 0x00400000);
	219	}
	220
	221	mode = "ARMv5";
	222	outer_cache.inv_range = tauros2_inv_range;
	223	outer_cache.clean_range = tauros2_clean_range;
	224	outer_cache.flush_range = tauros2_flush_range;
89326f76 CX	225	outer_cache.disable = tauros2_disable;
89326f76 CX	226	outer_cache.resume = tauros2_resume;
573a652f LB	227	}
	228	#endif
	229
	230	#ifdef CONFIG_CPU_32v6
	231	/*
	232	* Check whether this CPU lacks support for the v7 hierarchical
	233	* cache ops. (PJ4 is in its v6 personality mode if the MMFR3
	234	* register indicates no support for the v7 hierarchical cache
	235	* ops.)
	236	*/
	237	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
	238	/*
	239	* When Tauros2 is used in an ARMv6 system, the L2
	240	* enable bit is in the ARMv6 ARM-mandated position
	241	* (bit [26] of the System Control Register).
	242	*/
	243	if (!(get_cr() & 0x04000000)) {
	244	printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
	245	adjust_cr(0x04000000, 0x04000000);
	246	}
	247
	248	mode = "ARMv6";
	249	outer_cache.inv_range = tauros2_inv_range;
	250	outer_cache.clean_range = tauros2_clean_range;
	251	outer_cache.flush_range = tauros2_flush_range;
89326f76 CX	252	outer_cache.disable = tauros2_disable;
89326f76 CX	253	outer_cache.resume = tauros2_resume;
573a652f LB	254	}
	255	#endif
	256
	257	#ifdef CONFIG_CPU_32v7
	258	/*
	259	* Check whether this CPU has support for the v7 hierarchical
	260	* cache ops. (PJ4 is in its v7 personality mode if the MMFR3
	261	* register indicates support for the v7 hierarchical cache
	262	* ops.)
	263	*
	264	* (Although strictly speaking there may exist CPUs that
	265	* implement the v7 cache ops but are only ARMv6 CPUs (due to
	266	* not complying with all of the other ARMv7 requirements),
	267	* there are no real-life examples of Tauros2 being used on
	268	* such CPUs as of yet.)
	269	*/
	270	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
	271	u32 actlr;
	272
	273	/*
	274	* When Tauros2 is used in an ARMv7 system, the L2
	275	* enable bit is located in the Auxiliary System Control
	276	* Register (which is the only register allowed by the
	277	* ARMv7 spec to contain fine-grained cache control bits).
	278	*/
	279	actlr = read_actlr();
	280	if (!(actlr & 0x00000002)) {
	281	printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
	282	write_actlr(actlr \| 0x00000002);
	283	}
	284
	285	mode = "ARMv7";
	286	}
	287	#endif
	288
	289	if (mode == NULL) {
	290	printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n");
	291	return;
	292	}
	293
	294	printk(KERN_INFO "Tauros2: L2 cache support initialised "
	295	"in %s mode.\n", mode);
	296	}