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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/cache-v4.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell king | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/linkage.h> | |
11 | #include <linux/init.h> | |
1da177e4 LT |
12 | #include <asm/page.h> |
13 | #include "proc-macros.S" | |
14 | ||
c8c90860 MW |
15 | /* |
16 | * flush_icache_all() | |
17 | * | |
18 | * Unconditionally clean and invalidate the entire icache. | |
19 | */ | |
20 | ENTRY(v4_flush_icache_all) | |
21 | mov pc, lr | |
22 | ENDPROC(v4_flush_icache_all) | |
23 | ||
1da177e4 LT |
24 | /* |
25 | * flush_user_cache_all() | |
26 | * | |
27 | * Invalidate all cache entries in a particular address | |
28 | * space. | |
29 | * | |
30 | * - mm - mm_struct describing address space | |
31 | */ | |
32 | ENTRY(v4_flush_user_cache_all) | |
33 | /* FALLTHROUGH */ | |
34 | /* | |
35 | * flush_kern_cache_all() | |
36 | * | |
37 | * Clean and invalidate the entire cache. | |
38 | */ | |
39 | ENTRY(v4_flush_kern_cache_all) | |
e4d2a598 | 40 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
41 | mov r0, #0 |
42 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache | |
43 | mov pc, lr | |
f12d0d7c HC |
44 | #else |
45 | /* FALLTHROUGH */ | |
46 | #endif | |
1da177e4 LT |
47 | |
48 | /* | |
49 | * flush_user_cache_range(start, end, flags) | |
50 | * | |
51 | * Invalidate a range of cache entries in the specified | |
52 | * address space. | |
53 | * | |
54 | * - start - start address (may not be aligned) | |
55 | * - end - end address (exclusive, may not be aligned) | |
56 | * - flags - vma_area_struct flags describing address space | |
57 | */ | |
58 | ENTRY(v4_flush_user_cache_range) | |
e4d2a598 | 59 | #ifdef CONFIG_CPU_CP15 |
1da177e4 | 60 | mov ip, #0 |
794fe85d | 61 | mcr p15, 0, ip, c7, c7, 0 @ flush ID cache |
1da177e4 | 62 | mov pc, lr |
f12d0d7c HC |
63 | #else |
64 | /* FALLTHROUGH */ | |
65 | #endif | |
1da177e4 LT |
66 | |
67 | /* | |
68 | * coherent_kern_range(start, end) | |
69 | * | |
70 | * Ensure coherency between the Icache and the Dcache in the | |
71 | * region described by start. If you have non-snooping | |
72 | * Harvard caches, you need to implement this function. | |
73 | * | |
74 | * - start - virtual start address | |
75 | * - end - virtual end address | |
76 | */ | |
77 | ENTRY(v4_coherent_kern_range) | |
78 | /* FALLTHROUGH */ | |
79 | ||
80 | /* | |
81 | * coherent_user_range(start, end) | |
82 | * | |
83 | * Ensure coherency between the Icache and the Dcache in the | |
84 | * region described by start. If you have non-snooping | |
85 | * Harvard caches, you need to implement this function. | |
86 | * | |
87 | * - start - virtual start address | |
88 | * - end - virtual end address | |
89 | */ | |
90 | ENTRY(v4_coherent_user_range) | |
c5102f59 | 91 | mov r0, #0 |
1da177e4 LT |
92 | mov pc, lr |
93 | ||
94 | /* | |
2c9b9c84 | 95 | * flush_kern_dcache_area(void *addr, size_t size) |
1da177e4 LT |
96 | * |
97 | * Ensure no D cache aliasing occurs, either with itself or | |
98 | * the I cache | |
99 | * | |
2c9b9c84 RK |
100 | * - addr - kernel address |
101 | * - size - region size | |
1da177e4 | 102 | */ |
2c9b9c84 | 103 | ENTRY(v4_flush_kern_dcache_area) |
1da177e4 LT |
104 | /* FALLTHROUGH */ |
105 | ||
1da177e4 LT |
106 | /* |
107 | * dma_flush_range(start, end) | |
108 | * | |
109 | * Clean and invalidate the specified virtual address range. | |
110 | * | |
111 | * - start - virtual start address | |
112 | * - end - virtual end address | |
113 | */ | |
114 | ENTRY(v4_dma_flush_range) | |
e4d2a598 | 115 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
116 | mov r0, #0 |
117 | mcr p15, 0, r0, c7, c7, 0 @ flush ID cache | |
f12d0d7c | 118 | #endif |
1da177e4 LT |
119 | mov pc, lr |
120 | ||
a9c9147e RK |
121 | /* |
122 | * dma_unmap_area(start, size, dir) | |
123 | * - start - kernel virtual start address | |
124 | * - size - size of region | |
125 | * - dir - DMA direction | |
126 | */ | |
127 | ENTRY(v4_dma_unmap_area) | |
128 | teq r2, #DMA_TO_DEVICE | |
702b94bf | 129 | bne v4_dma_flush_range |
a9c9147e RK |
130 | /* FALLTHROUGH */ |
131 | ||
132 | /* | |
133 | * dma_map_area(start, size, dir) | |
134 | * - start - kernel virtual start address | |
135 | * - size - size of region | |
136 | * - dir - DMA direction | |
137 | */ | |
138 | ENTRY(v4_dma_map_area) | |
139 | mov pc, lr | |
140 | ENDPROC(v4_dma_unmap_area) | |
141 | ENDPROC(v4_dma_map_area) | |
142 | ||
031bd879 LP |
143 | .globl v4_flush_kern_cache_louis |
144 | .equ v4_flush_kern_cache_louis, v4_flush_kern_cache_all | |
145 | ||
1da177e4 LT |
146 | __INITDATA |
147 | ||
54d4e9eb DM |
148 | @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) |
149 | define_cache_functions v4 |